論文 - 石原 亨
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A power reduction technique with object code merging for application specific embedded processors 査読有り
Tohru Ishihara, Hiroto Yasuura
Proc. Design, Automation and Test in Europe (DATE) 頁： 617 - 623 2000年3月
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System LSI design methods for low power LSIs 招待有り 査読有り
H. Yasuura; T. Ishihara
IEICE Transactions on Electronics E83-C 巻 ( 2 ) 頁： 143 - 152 2000年2月
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A high-performance and low-power cache architecture with speculative way-selection 査読有り
K. Indue; T. Ishihara; K. Kai; K. Murakami
IEICE Transactions on Electronics E83-C 巻 ( 2 ) 頁： 186 - 193 2000年2月
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A memory power optimization technique for application specific embedded systems 査読有り
T. Ishihara; H. Yasuura
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E82-A 巻 ( 11 ) 頁： 2366 - 2374 1999年11月
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Real-time task scheduling for a variable voltage processor 査読有り
Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
Proc. the 12th International Symposium on System Synthesis (ISSS) 頁： 24 - 29 1999年11月
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Way-predicting set-associative cache for high performance and low energy consumption 査読有り
Koji Inoue, Tohru Ishihara, Kazuaki Murakami
Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 273 - 275 1999年8月
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Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches 査読有り
H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E81-A 巻 ( 12 ) 頁： 2621 - 2629 1998年12月
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Programmable power management architecture for power reduction 査読有り
T. Ishihara; H. Yasuura
IEICE Transactions on Electronics E81-C 巻 ( 9 ) 頁： 1473 - 1479 1998年9月
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Voltage scheduling problem for dynamically variable voltage processors 査読有り
Tohru Ishihara, Hiroto Yasuura
Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 197 - 202 1998年8月
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Instruction Scheduling for Power Reduction in Processor-Based System Design 査読有り
Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
Proc. Design, Automation and Test in Europe (DATE) 頁： 855 - 860 1998年2月
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Power-Pro: Programmable Power Management Architecture 査読有り
Tohru Ishihara, Hiroto Yasuura
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 321 - 322 1998年2月
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Optimization of Supply Voltage Assignment for Power Reduction on Processor Based Systems 査読有り
Tohru Ishihara, Hiroto Yasuura
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 170 - 177 1997年12月
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Experimental analysis of power estimation models of CMOS VLSI circuits 査読有り
Tohru Ishihara, Hiroto Yasuura
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E80-A 巻 ( 3 ) 頁： 480 - 486 1997年3月
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Basic experimentation on accuracy of power estimation for CMOS VLSI circuits 査読有り
Tohru Ishihara, Hiroto Yasuura
Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 117 - 120 1996年8月