論文 - 石原 亨
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An RTOS in hardware for energy efficient software-based TCP/IP processing 査読有り
Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura
Proc. IEEE 8th Symposium on Application Specific Processors (SASP) 頁： 58 - 63 2010年6月
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An implementation of energy efficient multi-performance processor for real-time applications 査読有り
Chengjie Zang, Tohru Ishihara
Proc. the 2010 International Conference on Green Circuits and Systems 頁： 211 - 216 2010年6月
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Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories 査読有り
Lovic Gauthier, Tohru Ishihara
Proc. the 7th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) 頁： 116 - 125 2009年10月
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Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion 査読有り
Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
IPSJ Transactions on System LSI Design Methodology 2 巻 頁： 189-199 2009年2月
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An Optimization Technique for Low-Energy Embedded Memory Systems 査読有り
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
IPSJ Transactions on System LSI Design Methodology 2 巻 頁： 239-249 2009年2月
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Way-Scaling to Reduce Power of Cache with Delay Variation 査読有り
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 91-A 巻 ( 12 ) 頁： 3576-3584 2008年12月
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A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation 査読有り
M. Goudarzi; T. Ishihara; H. Yasuura
Microelectronics Journal 39 巻 ( 12 ) 頁： 1797 - 1808 2008年12月
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Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption 査読有り
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
Proc. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 頁： 62 - 71 2008年9月
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Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation 査読有り
Maziar Goudarzi, Tohru Ishihara
Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 93 - 98 2008年8月
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AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications 査読有り
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato
Proc. IEEE Symposium on Application Specific Processors (SASP) 頁： 83 - 88 2008年6月
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Simultaneous optimization of memory configuration and code allocation for low power embedded systems 査読有り
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
Proc. the 18th ACM Great Lakes Symposium on VLSI 頁： 403 - 406 2008年5月
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Instruction cache leakage reduction by changing register operands and using asymmetric sram cells 査読有り
Maziar Goudarzi, Tohru Ishihara
Proc. the 18th ACM Great Lakes Symposium on VLSI 頁： 383 - 386 2008年5月
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Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems 査読有り
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
IEICE Transactions on Electronics 91-C 巻 ( 4 ) 頁： 410-417 2008年4月
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Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways 査読有り
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 頁： 447 - 450 2008年4月
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Value-dependence of SRAM leakage in deca-nanometer technologies 査読有り
Maziar Goudarzi, Tohru Ishihara
IEICE Electronic Express 5 巻 頁： 23-28 2008年1月
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Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation 査読有り
Maziar Goudarzi, Tohru Ishihara, Mamid Noori
Proc. High Performance Embedded Architectures and Compilers (HiPEAC) 頁： 224 - 239 2008年1月
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Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems 査読有り
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
IEICE Transactions on Electronics 90-C 巻 ( 10 ) 頁： 1983-1991 2007年10月
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A Hybrid Memory Architecture for Low Power Embedded System Design 査読有り
Tadayuki Matsumura, Yuriko Ishitobi, Tohru Ishihara, Maziar Goudarzi, Hiroto Yasuura
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 56 - 62 2007年10月
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Code placement for reducing the energy consumption of embedded processors with scratchpad and cache memories 査読有り
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
Proc. IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia) 頁： 13 - 18 2007年10月
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Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems 査読有り
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
Proc. Design, Automation and Test in Europe (DATE) 頁： 1490 - 1495 2007年4月