研究者詳細 - 石原　亨

論文 - 石原　亨

分割表示 154 件中 41 - 60 件目／全件表示 >>

A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator 査読有り

岸本真, 石原亨, 小野寺秀俊

Japanese Journal of Applied Physics 57 巻 ( 4S ) 頁： 04FF09-1 - 04FF09-6 2018年3月

A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits 査読有り

徐宏傑, 塩見準, 石原亨, 小野寺秀俊

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 56 - 61 2018年3月

On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation 査読有り

岸本真, 石原亨, 小野寺秀俊

Proc. Annual IEEE International Conference on Microelectronic Test Structures (ICMTS) 頁： 111 - 116 2018年3月

Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) 頁： 45 - 50 2018年3月

Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation 査読有り

長岡悠太, 石原亨, 小野寺秀俊

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 290 - 295 2018年3月

An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters 査読有り

今井悠貴, 石原亨, 小野寺秀俊, 新家昭彦, 北翔太, 野崎謙悟, 高田健太, 納富雅也

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 100 - 105 2018年3月

All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors 査読有り

保木本修, 塩見準, 石原亨, 小野寺秀俊

Proc. Annual IEEE International Conference on Microelectronic Test Structures (ICMTS) 頁： 128 - 133 2018年3月

A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies 査読有り

江川巧, 石原亨, 小野寺秀俊, 新家昭彦, 北翔太, 野崎謙悟, 高田健太, 納富雅也

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 320 - 325 2018年3月

Ultralow latency computation based on integrated nanophotonics 招待有り査読有り

Masaya Notomi, Kengo Nozaki, Shota Kita, Akihiko Shinya, Tohru Ishihara, Koji Inoue

Optics InfoBase Conference Papers 2018 巻 2018年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：OSA - The Optical Society

Moore's law for CMOS computers is still continuing, but its near-future saturation is now being discussed. One of the serious saturations is about its latency. The computation delay for a CMOS transistor is already saturated above 10 ps, which will be problematic when ultralow-latency response is required for broad-band data streams, even with parallelization or pipe-line processing. We regard that optical circuits may serve as ultralow-latency computation circuits if they are small enough and tightly combined with electronic circuits. The former requires nanophotonic devices/circuits and the former requires OE/EO conversion with ultrasmall capacitance.

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A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing 査読有り

保木本修, 石原亨, 小野寺秀俊

IEICE Transactions on Fundamentals E100A 巻 ( 12 ) 頁： 2776 - 2784 2017年12月

A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation 査読有り

塩見準, 石原亨, 小野寺秀俊

IEICE Transactions on Fundamentals E100A 巻 ( 12 ) 頁： 2764 - 2775 2017年12月

Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing 査読有り

塩見準, 石原亨, 小野寺秀俊

Elsevier: Integration, the VLSI Journal ( 有り ) 2017年7月

On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator 査読有り

Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) 頁： 1 - 4 2017年4月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a temperature monitoring scheme using a reconfigurable ring oscillator that has been proposed to estimate process variation. New circuit configurations, whose delay characteristics are sensitive to leakage current, are proposed to exploit the exponential dependence of the leakage current to temperature. Based on transistorlevel simulation assuming a 65 nm process technology, the oscillation frequency of the proposed circuit topology shows the temperature sensitivity of 5.0 %/degrees C at 20 degrees C and 2.9 %/ degrees C at 80 degrees C with low voltage sensitivity of 0.28 degrees C/10 mV at 25 degrees C and a supply voltage of 0.9 V. Estimation error of a 65 nm test chip ranges from -0.6 degrees C to 0.4 degrees C after two-point calibration. We also proposed a method to estimate the process variation and the temperature at the same time.

DOI： 10.1109/VLSI-DAT.2017.7939649

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その他リンク： https://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2017.html#KishimotoIO17

Analytical Stability Modeling for CMOS Latches in Low Voltage Operation 査読有り

Kamakari Tatsuya, Shiomi Jun, Ishihara Tohru, Onodera Hidetoshi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A 巻 ( 12 ) 頁： 2463 - 2472 2016年12月

A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 頁： 36 - 41 2016年10月

Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications 査読有り

Kei Yoshizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 頁： 329 - 334 2016年10月

An Integrated Optical Parallel Adder as a First Step Towards Light Speed Data Processing 査読有り国際誌

Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi

2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 頁： 123 - 124 2016年10月

担当区分：筆頭著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Integrated optical circuits with nanophotonic devices have attracted significant attention due to its low power dissipation and light-speed operation. With light interference and resonance phenomena, the nanophotonic device works as a voltage-controlled optical pass-gate like a pass-transistor. This paper first introduces a concept of the optical pass-gate logic, and then proposes a parallel adder circuit based on the optical pass gate logic. Experimental results obtained with an optoelectronic circuit simulator show advantages of our optical parallel adder circuit over a traditional CMOS-based parallel adder circuit.

DOI： 10.1109/ISOCC.2016.7799721

Web of Science

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その他リンク： https://dblp.uni-trier.de/db/conf/isocc/isocc2016.html#IshiharaSINN16

Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

PROCEEDINGS OF 2016 26TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) 頁： 44 - 49 2016年9月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area-and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using 65-nm FDSOI technology shows that the proposed SCM achieves area efficiency of 5.9 mu m(2) per bit (592F(2) per bit), which is less than that of the state of the art SCMs. The results also show that the energy consumption is further improved when the supply voltage scaling and back-gate biasing techniques are applied to our SCM.

DOI： 10.1109/PATMOS.2016.7833424

Web of Science

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その他リンク： https://dblp.uni-trier.de/db/conf/patmos/patmos2016.html#ShiomiIO16

Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing 査読有り

Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera

Proc. IEEE International System-on-Chip Conference (SOCC) 頁： 1 - 6 2016年9月

Guidelines for effective and simplified dynamic supply and threshold voltage scaling 査読有り

Toshinori Takeshita, Tohru Ishihara, Hidetoshi Onodera

Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2016年4月

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