研究者詳細 - 石原　亨

論文 - 石原　亨

分割表示 >> ／全件表示 154 件中 1 - 154 件目

An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing 査読有り

L. Hou, Y. Masuda, and T. Ishihara

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E106-A 巻 ( 3 ) 頁： 532 - 541 2023年3月

DVFS virtualization for energy minimization of mixed-criticality dual-OS platforms 査読有り

T. Komori, Y. Masuda, and T. Ishihara

Proc. 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) 頁： 128 - 137 2022年8月

Power-Aware Pruning for Ultrafast, Energy-Efficient, and Accurate Optical Neural Network Design 査読有り

N. Hattori, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi

Proc. Design Automation Conference (DAC) 2022年7月

Optoelectronic Implementation of Compact and Power-Efficient Recurrent Neural Networks 査読有り

N. Ichikawa, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi

Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 頁： 390 - 393 2022年6月

Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing 査読有り

T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E105-A 巻 ( 3 ) 頁： 497 - 508 2022年3月

Identification of redundant flip-flops using fault injection for low-power approximate computing circuits 査読有り

Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol.E107-A 巻 ( No.3 ) 2024年3月

Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform 査読有り

Takumi Komori, Yutaka Masuda, Tohru Ishihara

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol.E107-A 巻 ( No.1 ) 頁： 3 - 15 2024年1月

A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design 査読有り

T. -F. Chen, Y. Masuda, T. Ishihara

Proc. 36th IEEE International System-On-Chip Conference (SOCC) 頁： 34 - 39 2023年9月

Feedback-tuned fuzzing for accelerating quality verification of approximate computing design 査読有り

Yusei Honda, Yutaka Masuda, Tohru Ishihara

Proc. 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 頁： 1 - 3 2023年7月

An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits 査読有り

Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara

Proc. IEEE Design, Automation and Test in Europe Conference (DATE) 頁： 1 - 2 2023年4月

Dynamic Verification Framework of Approximate Computing Circuits using Quality-aware Coverage-based Grey-box Fuzzing 査読有り

Y. Masuda, Y. Honda, and T. Ishihara

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E106-A 巻 ( 3 ) 頁： 514 - 522 2023年3月

Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits 査読有り

J. Lu, Y. Masuda, T. Ishihara

Proc. 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 頁： 20 - 25 2022年10月

Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits 査読有り

Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera

IEEE 35th International System-on-Chip Conference (SOCC) 頁： 1 - 6 2022年9月

Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling 査読有り

Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E105-A 巻 ( 3 ) 頁： 509 - 517 2022年3月

Energy efficient OEO conversion and its applications to photonic integrated systems 査読有り国際誌

Shinya A., Nozaki K., Kita S., Ishihara T., Matsuo S., Notomi M.

Proc. Optical Fiber Communications Conference and Exhibition (OFC) 2022年3月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Optics InfoBase Conference Papers

We describe nanophotonics-based opto-electric devices and their femtofarad integration. The combination of these devices and optical interference units has a potential to provide energy-efficient and ultra-low latency optical information processing.

Scopus

An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers 査読有り

L. Hou, Y. Masuda, and T. Ishihara

Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 568 - 573 2022年1月

Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation 査読有り

N. Hattori, J. Shiomi, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E104-A 巻 ( 11 ) 頁： 1477 - 1487 2021年11月

A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits 査読有り

R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi,

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E104-A 巻 ( 11 ) 頁： 1546 - 1554 2021年11月

Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing 査読有り

K. Yoshisue, Y. Masuda, and T. Ishihara

Proc. IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) 2021年6月

Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing 査読有り

T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara

IEEE International Symposium on Quality Electronic Design (ISQED) 頁： 300 - 306 2021年4月

An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier 査読有り

Lingxiao Hou,Yutaka Masuda,Tohru Ishihara

Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2021年3月

Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing 査読有り

Naoki Hattori,Yutaka Masuda,Tohru Ishihara,Jun Shiomi,Akihiko Shinya,Masaya Notomi

Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics 11703 巻頁： 1E1 - 1E17 2021年3月

Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design 査読有り

Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto

Proc. IEEE Design, Automation and Test in Europe Conference (DATE) 2021年2月

An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. 査読有り

Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

Proc. International Conference on Rebooting Computing (ICRC) 頁： 95 - 101 2020年12月

Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling 査読有り

Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto

Proc. International Workshop on Logic and Synthesis (IWLS) 頁： 136 - 142 2020年7月

A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. 査読有り

Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 頁： 488 - 493 2020年7月

Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. 査読有り国際共著

Khyati Kiyawat,Yutaka Masuda,Jun Shiomi,Tohru Ishihara

Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 頁： 415 - 421 2020年7月

On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing 査読有り

Hongjie Xu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102-A 巻 ( 12 ) 頁： 1741 - 1750 2019年12月

Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits 査読有り

Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102-A 巻 ( 12 ) 頁： 1751 - 1759 2019年12月

An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator 査読有り国際誌

Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi

Photonics-Optics Technology Oriented Networking, Information, and Computing Systems (PHOTONICS) at The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC19) 2019年11月

A Design Method of a Cell-Based Amplifier for Body Bias Generation 査読有り

Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

IEICE Transactions on IEICE Transactions on Electronics E102-C 巻 ( 7 ) 頁： 565 - 572 2019年7月

BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing 査読有り国際誌

Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

Proc. the 24th Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 203 - 209 2019年1月

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms towards Light Speed Data Processing 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

Proc. IEEE International Conference on Rebooting Computing (ICRC) 頁： 62 - 67 2018年11月

Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics 査読有り国際誌

Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

Proc. IEEE International Conference on Rebooting Computing (ICRC) 頁： 43 - 50 2018年11月

Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization 査読有り

Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera

Proc.the 31st IEEE International System-on-Chip Conference (SOCC) 2018年9月

Independent N-well and P-well Biasing for Minimum Leakage Energy Operation 査読有り

Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera

Proc. the International Symposium on On-Line Testing and Robust System Design (IOLTS) 頁： 177 - 182 2018年7月

Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure 査読有り国際誌

Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) 頁： 237 - 242 2018年7月

Minimum Energy Point Tracking with All-Digital On-Chip Sensors

塩見準, 保木本修, 石原亨, 小野寺秀俊

ASP Journal of Low Power Electronics 14 巻 ( 2 ) 2018年6月

An Integrated Nanophotonic Parallel Adder 査読有り

石原亨, 新家昭彦, 井上弘士, 野崎謙悟, 納富雅也

ACM Journal on Emerging Technologies in Computing (JETC) 2018年6月

An optical parallel multiplier using nanophotonic analog adders and optoelectronic analog-to-digital converters 査読有り

Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

Proceedings of Conference on Lasers and Electro-Optics (CLEO) 2018 巻 2018年5月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：OSA - The Optical Society

We proposes an architecture of an optical parallel multiplier based on an optical analog addition. With optoelectronic circuit simulation, we show that the optical multiplier is more than three times faster than the CMOS multiplier.

DOI： 10.1364/CLEO_AT.2018.JW2A.50

Scopus

researchmap

A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator 査読有り

岸本真, 石原亨, 小野寺秀俊

Japanese Journal of Applied Physics 57 巻 ( 4S ) 頁： 04FF09-1 - 04FF09-6 2018年3月

A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits 査読有り

徐宏傑, 塩見準, 石原亨, 小野寺秀俊

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 56 - 61 2018年3月

On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation 査読有り

岸本真, 石原亨, 小野寺秀俊

Proc. Annual IEEE International Conference on Microelectronic Test Structures (ICMTS) 頁： 111 - 116 2018年3月

Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) 頁： 45 - 50 2018年3月

Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation 査読有り

長岡悠太, 石原亨, 小野寺秀俊

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 290 - 295 2018年3月

An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters 査読有り

今井悠貴, 石原亨, 小野寺秀俊, 新家昭彦, 北翔太, 野崎謙悟, 高田健太, 納富雅也

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 100 - 105 2018年3月

All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors 査読有り

保木本修, 塩見準, 石原亨, 小野寺秀俊

Proc. Annual IEEE International Conference on Microelectronic Test Structures (ICMTS) 頁： 128 - 133 2018年3月

A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies 査読有り

江川巧, 石原亨, 小野寺秀俊, 新家昭彦, 北翔太, 野崎謙悟, 高田健太, 納富雅也

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 320 - 325 2018年3月

Ultralow latency computation based on integrated nanophotonics 招待有り査読有り

Masaya Notomi, Kengo Nozaki, Shota Kita, Akihiko Shinya, Tohru Ishihara, Koji Inoue

Optics InfoBase Conference Papers 2018 巻 2018年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：OSA - The Optical Society

Moore's law for CMOS computers is still continuing, but its near-future saturation is now being discussed. One of the serious saturations is about its latency. The computation delay for a CMOS transistor is already saturated above 10 ps, which will be problematic when ultralow-latency response is required for broad-band data streams, even with parallelization or pipe-line processing. We regard that optical circuits may serve as ultralow-latency computation circuits if they are small enough and tightly combined with electronic circuits. The former requires nanophotonic devices/circuits and the former requires OE/EO conversion with ultrasmall capacitance.

Scopus

researchmap

A Minimum Energy Point Tracking Algorithm based on Dynamic Voltage Scaling and Adaptive Body Biasing 査読有り

保木本修, 石原亨, 小野寺秀俊

IEICE Transactions on Fundamentals E100A 巻 ( 12 ) 頁： 2776 - 2784 2017年12月

A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation 査読有り

塩見準, 石原亨, 小野寺秀俊

IEICE Transactions on Fundamentals E100A 巻 ( 12 ) 頁： 2764 - 2775 2017年12月

Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing 査読有り

塩見準, 石原亨, 小野寺秀俊

Elsevier: Integration, the VLSI Journal ( 有り ) 2017年7月

On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator 査読有り

Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) 頁： 1 - 4 2017年4月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a temperature monitoring scheme using a reconfigurable ring oscillator that has been proposed to estimate process variation. New circuit configurations, whose delay characteristics are sensitive to leakage current, are proposed to exploit the exponential dependence of the leakage current to temperature. Based on transistorlevel simulation assuming a 65 nm process technology, the oscillation frequency of the proposed circuit topology shows the temperature sensitivity of 5.0 %/degrees C at 20 degrees C and 2.9 %/ degrees C at 80 degrees C with low voltage sensitivity of 0.28 degrees C/10 mV at 25 degrees C and a supply voltage of 0.9 V. Estimation error of a 65 nm test chip ranges from -0.6 degrees C to 0.4 degrees C after two-point calibration. We also proposed a method to estimate the process variation and the temperature at the same time.

DOI： 10.1109/VLSI-DAT.2017.7939649

Web of Science

researchmap

その他リンク： https://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2017.html#KishimotoIO17

Analytical Stability Modeling for CMOS Latches in Low Voltage Operation 査読有り

Kamakari Tatsuya, Shiomi Jun, Ishihara Tohru, Onodera Hidetoshi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E99A 巻 ( 12 ) 頁： 2463 - 2472 2016年12月

A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 頁： 36 - 41 2016年10月

Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications 査読有り

Kei Yoshizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 頁： 329 - 334 2016年10月

An Integrated Optical Parallel Adder as a First Step Towards Light Speed Data Processing 査読有り国際誌

Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi

2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 頁： 123 - 124 2016年10月

担当区分：筆頭著者,　責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Integrated optical circuits with nanophotonic devices have attracted significant attention due to its low power dissipation and light-speed operation. With light interference and resonance phenomena, the nanophotonic device works as a voltage-controlled optical pass-gate like a pass-transistor. This paper first introduces a concept of the optical pass-gate logic, and then proposes a parallel adder circuit based on the optical pass gate logic. Experimental results obtained with an optoelectronic circuit simulator show advantages of our optical parallel adder circuit over a traditional CMOS-based parallel adder circuit.

DOI： 10.1109/ISOCC.2016.7799721

Web of Science

researchmap

その他リンク： https://dblp.uni-trier.de/db/conf/isocc/isocc2016.html#IshiharaSINN16

Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

PROCEEDINGS OF 2016 26TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) 頁： 44 - 49 2016年9月

担当区分：責任著者記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area-and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using 65-nm FDSOI technology shows that the proposed SCM achieves area efficiency of 5.9 mu m(2) per bit (592F(2) per bit), which is less than that of the state of the art SCMs. The results also show that the energy consumption is further improved when the supply voltage scaling and back-gate biasing techniques are applied to our SCM.

DOI： 10.1109/PATMOS.2016.7833424

Web of Science

researchmap

その他リンク： https://dblp.uni-trier.de/db/conf/patmos/patmos2016.html#ShiomiIO16

Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing 査読有り

Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera

Proc. IEEE International System-on-Chip Conference (SOCC) 頁： 1 - 6 2016年9月

Guidelines for effective and simplified dynamic supply and threshold voltage scaling 査読有り

Toshinori Takeshita, Tohru Ishihara, Hidetoshi Onodera

Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2016年4月

Variability- and correlation-aware logical effort for near-threshold circuit design 招待有り査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the17th International Symposium on Quality Electronic Design (ISQED) 頁： 18 - 23 2016年3月

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. 査読有り

Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

21st Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 691 - 696 2016年1月

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring 査読有り

イスラムマーフズ, 塩見準, 石原亨, 小野寺秀俊

IEEE Journal of Solid-State Circuits 50 巻 ( 11 ) 頁： 2475 - 2490 2015年11月

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization 査読有り

Shiomi Jun, Ishihara Tohru, Onodera Hidetoshi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A 巻 ( 7 ) 頁： 1455 - 1466 2015年7月

An impact of process variation on supply voltage dependence of logic path delay variation. 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. VLSI Design, Automation and Test (VLSI-DAT) 頁： 1 - 4 2015年4月

A Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation using Cell-Based Structure 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 2015年3月

An energy-efficient on-chip memory structure for variability-aware near-threshold operation. 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the 16th International Symposium on Quality Electronic Design (ISQED) 頁： 23 - 28 2015年3月

Energy reduction by built-in body biasing with single supply voltage operation. 査読有り

Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

Proc. the 16th International Symposium on Quality Electronic Design (ISQED) 頁： 181 - 185 2015年3月

Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell 査読有り

西澤真一, 石原亨, 小野寺秀俊

IPSJ Transactions on System LSI Design Methodology 8 巻頁： 131 - 135 2015年2月

Microarchitectural-level statistical timing models for near-threshold circuit design. 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the 20th Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 87 - 93 2015年1月

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications 査読有り国際誌

Takase Hideki, Zeng Gang, Gauthier Lovic, Kawashima Hirotaka, Atsumi Noritoshi, Tatematsu Tomohiro, Kobayashi Yoshitake, Koshiro Takenori, Ishihara Tohru, Tomiyama Hiroyuki, Takada Hiroaki

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A 巻 ( 12 ) 頁： 2477 - 2487 2014年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：一般社団法人電子情報通信学会

This paper presents a framework for reducing the energy consumption of embedded real-time systems. We implemented the presented framework as both an optimization toolchain and an energy-aware real-time operating system. The framework consists of the integration of multiple techniques to optimize the energy consumption. The main idea behind our approach is to utilize trade-offs between the energy consumption and the performance of different processor configurations during task checkpoints, and to maintain memory allocation during task context switches. In our framework, a target application is statically analyzed at both intra-task and inter-task levels. Based on these analyzed results, runtime optimization is performed in response to the behavior of the application. A case study shows that our toolchain and real-time operating systems have achieved energy reduction while satisfying the real-time performance. The toolchain has also been successfully applied to a practical application.

DOI： 10.1587/transfun.E97.A.2477

その他リンク： https://dblp.uni-trier.de/db/journals/ieicet/ieicet97a.html#TakaseZGKATKKIT14

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-chip Process and Temperature Monitoring 査読有り国際誌

A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) 頁： 45 - 48 2014年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. An estimation method of threshold voltage variation is then developed. Cell-base design approach is taken so that design cost is minimized. Measurement results from a 65-nm test chip show the validity of the proposed circuit. Total area is 4500 mu m(2) and active power consumption is 50 nW at 1.0 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as testing and post-silicon tuning.

DOI： 10.1109/ASSCC.2014.7008856

Web of Science

researchmap

その他リンク： https://dblp.uni-trier.de/db/conf/asscc/asscc2014.html#MahfuzulSIO14

Variation-aware Flip-Flop energy optimization for ultra low voltage operation. 査読有り

Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. the 27th IEEE International System-on-Chip Conference (SOCC) 頁： 17 - 22 2014年10月

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. the 27th IEEE International System-on-Chip Conference (SOCC) 頁： 42 - 47 2014年9月

Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) 頁： 28 - 32 2014年3月

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 96-A 巻 ( 12 ) 頁： 2499-2507 2013年12月

DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems 査読有り

K. Lee, T. Ishihara

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 96-A 巻 ( 12 ) 頁： 2660-2667 2013年12月

Energy-efficient Dynamic Voltage and Frequency Scaling by P/N-performance Self-adjustment using Adaptive Body Bias, 査読有り

A.K.M. Mahfuzul Islam, Norihiro Kamae, Tohru Ishihara, Hidetoshi Onodera

Proc. the Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2013年10月

A standard cell optimization method for near-threshold voltage operations 査読有り

Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7606 巻頁： 32 - 41 2013年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Springer

Near-threshold voltage operation is a well-known solution for drastically improving the energy efficiency of microprocessors fabricated with the latest process technologies. However, it is not well studied how the optimal gate size of standard cells changes when the supply voltage of the microprocessors gets closer to the threshold voltage. This paper first shows an experimental observation that the optimal gate size for nearthreshold voltage which is 0.6V in this work is far from the optimal gate size for the nominal supply voltage which is 1.2V in our target process technology. Based on this fact, the paper next presents our cell optimization flow which finds the optimal gate sizes of individual standard cells operating at the near-threshold voltage. The experimental results show that, when operating at the 0.6V condition, the energy consumptions of several benchmark circuits synthesized with our standard cells optimized for the 0.6V condition can be reduced by 31% at the best case and by 23% on average compared with those of the same circuits synthesized with the cells optimized for the nominal supply voltage. © Springer-Verlag Berlin Heidelberg 2013.

DOI： 10.1007/978-3-642-36157-9_4

Scopus

J-GLOBAL

researchmap

その他リンク： https://dblp.uni-trier.de/db/conf/patmos/patmos2012.html#KondoNIO12

DLIC: Decoded Loop Instructions Caching for Energy-Aware Embedded Processors 査読有り国際共著国際誌

Gu Ji, Guo Hui, Ishihara Tohru

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 13 巻 ( 1 ) 頁： 6 - 26 2013年8月

An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) 2013年3月

Analysis and comparison of XOR cell structures for low voltage circuit design. 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. International Symposium on Quality Electronic Design (ISQED) 頁： 703 - 708 2013年3月

A flexible structure of standard cell and its optimization method for near-threshold voltage operation 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. the 30th International IEEE Conference on Computer Design (ICCD) 頁： 235 - 240 2012年10月

I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays 査読有り

Kyungsoo Lee, Tohru Ishihara

Proc. IEEE 10th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia) 頁： 48 - 55 2012年10月

Loop instruction caching for energy-efficient embedded multitasking processors 査読有り

Ji Gu, Tohru Ishihara, Kyungsoo Lee

Proc. IEEE 10th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia) 頁： 97 - 106 2012年10月

A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems 査読有り

Ji Gu, Tohru Ishihara

Proc. the 1st International Conference on Smart Grids and Green IT Systems (SMARTGREENS) 頁： 197 - 202 2012年4月

A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems 査読有り

Kyungsoo Lee, Tohru Ishihara

Proc. the 1st International Conference on Smart Grids and Green IT Systems (SMARTGREENS) 頁： 175 - 182 2012年4月

Processor energy characterization for compiler-assisted software energy reduction 査読有り

L. Gauthier; T. Ishihara

Journal of Electrical and Computer Engineering - 英語 2012年1月

Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications 査読有り

Lovic Gauthier, Tohru Ishihara

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 94-A 巻 ( 12 ) 頁： 2597-2608 2011年12月

ＲＴＯＳのハードウェア化によるソフトウェアベースＴＣＰ／ＩＰ処理の高速化と低消費電力化査読有り

丸山修孝;石原亨;安浦寛人

電子情報通信学会論文誌 A J94-A 巻 ( 9 ) 頁： 692 - 701 2011年9月

Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits 査読有り

Takumi Okuhira, Tohru Ishihara

Proc. the 21st International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 頁： 237 - 246 2011年9月

An integrated optimization framework for reducing the energy consumption of embedded real-time applications 査読有り

Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada

Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 271 - 276 2011年8月

Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies 査読有り

Maziar Goudarzi, Tohru Ishihara, Hamid Noori

Transactions on High-Performance Embedded Architectures and Compilers 3 巻頁： 275-299 2011年3月

Developing an integrated verification and debug methodology 査読有り

Akitoshi Matsuda, Tohru Ishihara

Proc. Design, Automation and Test in Europe (DATE) 頁： 503 - 504 2011年3月

A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems 査読有り

Tohru ISHIHARA

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 93-A 巻 ( 12 ) 頁： 2533-2541 2010年12月

SRAM leakage reduction by row/column redundancy under random within-die delay variation 査読有り

M. Goudarzi; T. Ishihara

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 巻 ( 12 ) 頁： 1660 - 1671 2010年12月

Compiler assisted energy reduction techniques for embedded multimedia processors 招待有り査読有り

Lovic Gauthier, Tohru Ishihara

Proc. the 2nd APSIPA Annual Summit and Conference 頁： 27 - 36 2010年12月

Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications 査読有り

Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 7 - 12 2010年10月

Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems 査読有り

Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada

Proc. the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) 頁： 157 - 166 2010年10月

Code and data placement for embedded processors with scratchpad and cache memories 査読有り

Y. Ishitobi; T. Ishihara; H. Yasuura

Journal of Signal Processing Systems 60 巻 ( 2 ) 頁： 211 - 224 2010年8月

An RTOS in hardware for energy efficient software-based TCP/IP processing 査読有り

Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura

Proc. IEEE 8th Symposium on Application Specific Processors (SASP) 頁： 58 - 63 2010年6月

An implementation of energy efficient multi-performance processor for real-time applications 査読有り

Chengjie Zang, Tohru Ishihara

Proc. the 2010 International Conference on Green Circuits and Systems 頁： 211 - 216 2010年6月

Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories 査読有り

Lovic Gauthier, Tohru Ishihara

Proc. the 7th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) 頁： 116 - 125 2009年10月

Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion 査読有り

Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

IPSJ Transactions on System LSI Design Methodology 2 巻頁： 189-199 2009年2月

An Optimization Technique for Low-Energy Embedded Memory Systems 査読有り

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

IPSJ Transactions on System LSI Design Methodology 2 巻頁： 239-249 2009年2月

Way-Scaling to Reduce Power of Cache with Delay Variation 査読有り

Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 91-A 巻 ( 12 ) 頁： 3576-3584 2008年12月

A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V_th variation 査読有り

M. Goudarzi; T. Ishihara; H. Yasuura

Microelectronics Journal 39 巻 ( 12 ) 頁： 1797 - 1808 2008年12月

Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption 査読有り

Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura

Proc. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 頁： 62 - 71 2008年9月

Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation 査読有り

Maziar Goudarzi, Tohru Ishihara

Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 93 - 98 2008年8月

AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications 査読有り

Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato

Proc. IEEE Symposium on Application Specific Processors (SASP) 頁： 83 - 88 2008年6月

Simultaneous optimization of memory configuration and code allocation for low power embedded systems 査読有り

Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

Proc. the 18th ACM Great Lakes Symposium on VLSI 頁： 403 - 406 2008年5月

Instruction cache leakage reduction by changing register operands and using asymmetric sram cells 査読有り

Maziar Goudarzi, Tohru Ishihara

Proc. the 18th ACM Great Lakes Symposium on VLSI 頁： 383 - 386 2008年5月

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems 査読有り

Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami

IEICE Transactions on Electronics 91-C 巻 ( 4 ) 頁： 410-417 2008年4月

Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways 査読有り

Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara

Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 頁： 447 - 450 2008年4月

Value-dependence of SRAM leakage in deca-nanometer technologies 査読有り

Maziar Goudarzi, Tohru Ishihara

IEICE Electronic Express 5 巻頁： 23-28 2008年1月

Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation 査読有り

Maziar Goudarzi, Tohru Ishihara, Mamid Noori

Proc. High Performance Embedded Architectures and Compilers (HiPEAC) 頁： 224 - 239 2008年1月

Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems 査読有り

Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami

IEICE Transactions on Electronics 90-C 巻 ( 10 ) 頁： 1983-1991 2007年10月

A Hybrid Memory Architecture for Low Power Embedded System Design 査読有り

Tadayuki Matsumura, Yuriko Ishitobi, Tohru Ishihara, Maziar Goudarzi, Hiroto Yasuura

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 56 - 62 2007年10月

Code placement for reducing the energy consumption of embedded processors with scratchpad and cache memories 査読有り

Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

Proc. IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia) 頁： 13 - 18 2007年10月

Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems 査読有り

Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami

Proc. Design, Automation and Test in Europe (DATE) 頁： 1490 - 1495 2007年4月

A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation 査読有り

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura

Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 878 - 883 2007年1月

An Energy Characterization Framework for Software-Based Embedded Systems 査読有り

Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah

Proc. IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia) 頁： 59 - 64 2006年10月

Exploiting Narrow Bitwidth Operations for Low Power Embedded Software Design 査読有り

Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 51 - 56 2006年4月

A simulation-based soft error estimation methodology for computer systems 査読有り

Makoto Sugihara, Tohru Ishihara, Koji Hashimoto, Masanori Muroyama

Proc. IEEE International Symposium on Quality Electronics Design (ISQED) 頁： 196 - 203 2006年3月

A cache-defect-aware code placement algorithm for improving the performance of processors 査読有り国際共著

Tohru Ishihara, Farzan Fallah

Proc. International Conference on Computer Aided Design (ICCAD) 頁： 995 - 1001 2005年11月

A non-uniform cache architecture for low power system design 査読有り国際共著

Tohru Ishihara, Farzan Fallah

Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 363 - 368 2005年8月

A Code Placement Technique for Improving the Performance of Processors with Defective Caches 査読有り

Tohru Ishihara, Farzan Fallah

Proc. International Workshop on Logic and Synthesis (IWLS) 頁： 210 - 214 2005年6月

A way memoization technique for reducing power consumption of caches in application specific integrated processors 査読有り

Tohru Ishihara, Farzan Fallah

Proc. Design, Automation and Test in Europe (DATE) 頁： 358 - 363 2005年3月

Comparative Study On Verilog-Based And C-Based Hardware Design Education 査読有り

Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada

Proc. International Conference on Microelectronics Systems Education (MSE) 頁： 41 - 42 2003年6月

オンチップメモリの高速化と低スタンバイリークを実現する閾値電圧の静的スケジューリング手法査読有り

石原亨, 浅田邦博

情報処理学会論文誌 44 巻 ( 5 ) 頁： 1284-1291 2003年5月

A Voltage Scheduling Technique for Fault-Tolerant Real-Time Microprocessor Systems 査読有り

Tohru Ishihara

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 137 - 143 2003年4月

An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories 査読有り

Tohru Ishihara, Kunihiro Asada

Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 282 - 287 2002年1月

A power minimization technique for arithmetic circuits by cell selection 査読有り

Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura

Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 268 - 273 2002年1月

A System Level Optimization Technique for Application Specific Low Power Memories 査読有り

Tohru ISHIHARA, Kunihiro ASADA

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences E84-A 巻 ( 11 ) 頁： 2755-2761 2001年11月

入力信号パターンを考慮した低電力算術演算回路の設計手法査読有り

室山真徳，石原亨，兵頭章彦，安浦寛人

情報処理学会論文誌 42 巻 ( 4 ) 頁： 1007-1015 2001年4月

DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ査読有り

井上弘士, 石原亨，甲斐康司，村上和彰

情報処理学会論文誌 42 巻 ( 3 ) 頁： 419-431 2001年3月

Software energy reduction techniques for variable-voltage processors 査読有り

T. Okuma; H. Yasuura; T. Ishihara

IEEE Design and Test of Computers 18 巻 ( 2 ) 頁： 31 - 41 2001年3月

A system level memory power optimization technique using multiple supply and threshold voltages 査読有り

Tohru Ishihara, Kunihiro Asada

Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 456 - 461 2001年1月

可変電源電圧プロセッサに対するリアルタイムタスクスケジューリング手法査読有り

大隈孝憲, 石原亨, 安浦寛人

電子情報通信学会論文誌 J83-C 巻 ( 6 ) 頁： 454-462 2000年6月

Flexible system LSI for embedded systems and its optimization techniques 査読有り

A. Inoue; T. Ishihara; H. Yasuura

Design Automation for Embedded Systems 5 巻 ( 2 ) 頁： 179 - 205 2000年6月

A power reduction technique with object code merging for application specific embedded processors 査読有り

Tohru Ishihara, Hiroto Yasuura

Proc. Design, Automation and Test in Europe (DATE) 頁： 617 - 623 2000年3月

System LSI design methods for low power LSIs 招待有り査読有り

H. Yasuura; T. Ishihara

IEICE Transactions on Electronics E83-C 巻 ( 2 ) 頁： 143 - 152 2000年2月

A high-performance and low-power cache architecture with speculative way-selection 査読有り

K. Indue; T. Ishihara; K. Kai; K. Murakami

IEICE Transactions on Electronics E83-C 巻 ( 2 ) 頁： 186 - 193 2000年2月

A memory power optimization technique for application specific embedded systems 査読有り

T. Ishihara; H. Yasuura

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E82-A 巻 ( 11 ) 頁： 2366 - 2374 1999年11月

Real-time task scheduling for a variable voltage processor 査読有り

Takanori Okuma, Tohru Ishihara, Hiroto Yasuura

Proc. the 12th International Symposium on System Synthesis (ISSS) 頁： 24 - 29 1999年11月

Way-predicting set-associative cache for high performance and low energy consumption 査読有り

Koji Inoue, Tohru Ishihara, Kazuaki Murakami

Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 273 - 275 1999年8月

Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches 査読有り

H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E81-A 巻 ( 12 ) 頁： 2621 - 2629 1998年12月

Programmable power management architecture for power reduction 査読有り

T. Ishihara; H. Yasuura

IEICE Transactions on Electronics E81-C 巻 ( 9 ) 頁： 1473 - 1479 1998年9月

Voltage scheduling problem for dynamically variable voltage processors 査読有り

Tohru Ishihara, Hiroto Yasuura

Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 197 - 202 1998年8月

Instruction Scheduling for Power Reduction in Processor-Based System Design 査読有り

Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura

Proc. Design, Automation and Test in Europe (DATE) 頁： 855 - 860 1998年2月

Power-Pro: Programmable Power Management Architecture 査読有り

Tohru Ishihara, Hiroto Yasuura

Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 321 - 322 1998年2月

Optimization of Supply Voltage Assignment for Power Reduction on Processor Based Systems 査読有り

Tohru Ishihara, Hiroto Yasuura

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 頁： 170 - 177 1997年12月

Experimental analysis of power estimation models of CMOS VLSI circuits 査読有り

Tohru Ishihara, Hiroto Yasuura

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E80-A 巻 ( 3 ) 頁： 480 - 486 1997年3月

Basic experimentation on accuracy of power estimation for CMOS VLSI circuits 査読有り

Tohru Ishihara, Hiroto Yasuura

Proc. International Symposium on Low Power Electronics and Design (ISLPED) 頁： 117 - 120 1996年8月

　前のページ - 次のページ　

<石原 亨>

論文 - 石原 亨

<石原　亨>

論文 - 石原　亨