論文 - 石原 亨
-
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing 査読有り
L. Hou, Y. Masuda, and T. Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E106-A 巻 ( 3 ) 頁： 532 - 541 2023年3月
-
DVFS virtualization for energy minimization of mixed-criticality dual-OS platforms 査読有り
T. Komori, Y. Masuda, and T. Ishihara
Proc. 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) 頁： 128 - 137 2022年8月
-
Power-Aware Pruning for Ultrafast, Energy-Efficient, and Accurate Optical Neural Network Design 査読有り
N. Hattori, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi
Proc. Design Automation Conference (DAC) 2022年7月
-
Optoelectronic Implementation of Compact and Power-Efficient Recurrent Neural Networks 査読有り
N. Ichikawa, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 頁： 390 - 393 2022年6月
-
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing 査読有り
T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E105-A 巻 ( 3 ) 頁： 497 - 508 2022年3月
-
Identification of redundant flip-flops using fault injection for low-power approximate computing circuits 査読有り
Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol.E107-A 巻 ( No.3 ) 2024年3月
-
Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform 査読有り
Takumi Komori, Yutaka Masuda, Tohru Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol.E107-A 巻 ( No.1 ) 頁： 3 - 15 2024年1月
-
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design 査読有り
T. -F. Chen, Y. Masuda, T. Ishihara
Proc. 36th IEEE International System-On-Chip Conference (SOCC) 頁： 34 - 39 2023年9月
-
Feedback-tuned fuzzing for accelerating quality verification of approximate computing design 査読有り
Yusei Honda, Yutaka Masuda, Tohru Ishihara
Proc. 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 頁： 1 - 3 2023年7月
-
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits 査読有り
Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
Proc. IEEE Design, Automation and Test in Europe Conference (DATE) 頁： 1 - 2 2023年4月
-
Dynamic Verification Framework of Approximate Computing Circuits using Quality-aware Coverage-based Grey-box Fuzzing 査読有り
Y. Masuda, Y. Honda, and T. Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E106-A 巻 ( 3 ) 頁： 514 - 522 2023年3月
-
Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits 査読有り
J. Lu, Y. Masuda, T. Ishihara
Proc. 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 頁： 20 - 25 2022年10月
-
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits 査読有り
Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera
IEEE 35th International System-on-Chip Conference (SOCC) 頁： 1 - 6 2022年9月
-
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling 査読有り
Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E105-A 巻 ( 3 ) 頁： 509 - 517 2022年3月
-
Energy efficient OEO conversion and its applications to photonic integrated systems 査読有り 国際誌
Shinya A., Nozaki K., Kita S., Ishihara T., Matsuo S., Notomi M.
Proc. Optical Fiber Communications Conference and Exhibition (OFC) 2022年3月
-
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers 査読有り
L. Hou, Y. Masuda, and T. Ishihara
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 568 - 573 2022年1月
-
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation 査読有り
N. Hattori, J. Shiomi, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E104-A 巻 ( 11 ) 頁： 1477 - 1487 2021年11月
-
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits 査読有り
R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E104-A 巻 ( 11 ) 頁： 1546 - 1554 2021年11月
-
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing 査読有り
K. Yoshisue, Y. Masuda, and T. Ishihara
Proc. IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) 2021年6月
-
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing 査読有り
T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara
IEEE International Symposium on Quality Electronic Design (ISQED) 頁： 300 - 306 2021年4月