論文 - 石原 亨
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An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier 査読有り
Lingxiao Hou,Yutaka Masuda,Tohru Ishihara
Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2021年3月
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Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing 査読有り
Naoki Hattori,Yutaka Masuda,Tohru Ishihara,Jun Shiomi,Akihiko Shinya,Masaya Notomi
Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics 11703 巻 頁： 1E1 - 1E17 2021年3月
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Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design 査読有り
Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto
Proc. IEEE Design, Automation and Test in Europe Conference (DATE) 2021年2月
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An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. 査読有り
Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi
Proc. International Conference on Rebooting Computing (ICRC) 頁： 95 - 101 2020年12月
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Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling 査読有り
Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto
Proc. International Workshop on Logic and Synthesis (IWLS) 頁： 136 - 142 2020年7月
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A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. 査読有り
Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 頁： 488 - 493 2020年7月
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Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. 査読有り 国際共著
Khyati Kiyawat,Yutaka Masuda,Jun Shiomi,Tohru Ishihara
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 頁： 415 - 421 2020年7月
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On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing 査読有り
Hongjie Xu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102-A 巻 ( 12 ) 頁： 1741 - 1750 2019年12月
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Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits 査読有り
Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102-A 巻 ( 12 ) 頁： 1751 - 1759 2019年12月
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An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator 査読有り 国際誌
Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi
Photonics-Optics Technology Oriented Networking, Information, and Computing Systems (PHOTONICS) at The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC19) 2019年11月
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A Design Method of a Cell-Based Amplifier for Body Bias Generation 査読有り
Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
IEICE Transactions on IEICE Transactions on Electronics E102-C 巻 ( 7 ) 頁： 565 - 572 2019年7月
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BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing 査読有り 国際誌
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
Proc. the 24th Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 203 - 209 2019年1月
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Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
Proc. IEEE International Conference on Rebooting Computing (ICRC) 頁： 62 - 67 2018年11月
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Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics 査読有り 国際誌
Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
Proc. IEEE International Conference on Rebooting Computing (ICRC) 頁： 43 - 50 2018年11月
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Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization 査読有り
Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera
Proc.the 31st IEEE International System-on-Chip Conference (SOCC) 2018年9月
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Independent N-well and P-well Biasing for Minimum Leakage Energy Operation 査読有り
Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera
Proc. the International Symposium on On-Line Testing and Robust System Design (IOLTS) 頁： 177 - 182 2018年7月
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Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure 査読有り 国際誌
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. the 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) 頁： 237 - 242 2018年7月
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Minimum Energy Point Tracking with All-Digital On-Chip Sensors
塩見準, 保木本修, 石原 亨, 小野寺秀俊
ASP Journal of Low Power Electronics 14 巻 ( 2 ) 2018年6月
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An Integrated Nanophotonic Parallel Adder 査読有り
石原 亨, 新家昭彦, 井上弘士, 野崎謙悟, 納富雅也
ACM Journal on Emerging Technologies in Computing (JETC) 2018年6月
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An optical parallel multiplier using nanophotonic analog adders and optoelectronic analog-to-digital converters 査読有り
Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
Proceedings of Conference on Lasers and Electro-Optics (CLEO) 2018 巻 2018年5月