研究者詳細 - 石原　亨

論文 - 石原　亨

分割表示 154 件中 61 - 80 件目／全件表示 >>

Variability- and correlation-aware logical effort for near-threshold circuit design 招待有り査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the17th International Symposium on Quality Electronic Design (ISQED) 頁： 18 - 23 2016年3月

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. 査読有り

Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

21st Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 691 - 696 2016年1月

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring 査読有り

イスラムマーフズ, 塩見準, 石原亨, 小野寺秀俊

IEEE Journal of Solid-State Circuits 50 巻 ( 11 ) 頁： 2475 - 2490 2015年11月

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization 査読有り

Shiomi Jun, Ishihara Tohru, Onodera Hidetoshi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A 巻 ( 7 ) 頁： 1455 - 1466 2015年7月

An impact of process variation on supply voltage dependence of logic path delay variation. 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. VLSI Design, Automation and Test (VLSI-DAT) 頁： 1 - 4 2015年4月

A Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation using Cell-Based Structure 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 2015年3月

An energy-efficient on-chip memory structure for variability-aware near-threshold operation. 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the 16th International Symposium on Quality Electronic Design (ISQED) 頁： 23 - 28 2015年3月

Energy reduction by built-in body biasing with single supply voltage operation. 査読有り

Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

Proc. the 16th International Symposium on Quality Electronic Design (ISQED) 頁： 181 - 185 2015年3月

Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell 査読有り

西澤真一, 石原亨, 小野寺秀俊

IPSJ Transactions on System LSI Design Methodology 8 巻頁： 131 - 135 2015年2月

Microarchitectural-level statistical timing models for near-threshold circuit design. 査読有り

Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. the 20th Asia and South Pacific Design Automation Conference (ASP-DAC) 頁： 87 - 93 2015年1月

An Integrated Framework for Energy Optimization of Embedded Real-Time Applications 査読有り国際誌

Takase Hideki, Zeng Gang, Gauthier Lovic, Kawashima Hirotaka, Atsumi Noritoshi, Tatematsu Tomohiro, Kobayashi Yoshitake, Koshiro Takenori, Ishihara Tohru, Tomiyama Hiroyuki, Takada Hiroaki

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A 巻 ( 12 ) 頁： 2477 - 2487 2014年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：一般社団法人電子情報通信学会

This paper presents a framework for reducing the energy consumption of embedded real-time systems. We implemented the presented framework as both an optimization toolchain and an energy-aware real-time operating system. The framework consists of the integration of multiple techniques to optimize the energy consumption. The main idea behind our approach is to utilize trade-offs between the energy consumption and the performance of different processor configurations during task checkpoints, and to maintain memory allocation during task context switches. In our framework, a target application is statically analyzed at both intra-task and inter-task levels. Based on these analyzed results, runtime optimization is performed in response to the behavior of the application. A case study shows that our toolchain and real-time operating systems have achieved energy reduction while satisfying the real-time performance. The toolchain has also been successfully applied to a practical application.

DOI： 10.1587/transfun.E97.A.2477

その他リンク： https://dblp.uni-trier.de/db/journals/ieicet/ieicet97a.html#TakaseZGKATKKIT14

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-chip Process and Temperature Monitoring 査読有り国際誌

A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Proc. IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) 頁： 45 - 48 2014年11月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. An estimation method of threshold voltage variation is then developed. Cell-base design approach is taken so that design cost is minimized. Measurement results from a 65-nm test chip show the validity of the proposed circuit. Total area is 4500 mu m(2) and active power consumption is 50 nW at 1.0 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as testing and post-silicon tuning.

DOI： 10.1109/ASSCC.2014.7008856

Web of Science

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その他リンク： https://dblp.uni-trier.de/db/conf/asscc/asscc2014.html#MahfuzulSIO14

Variation-aware Flip-Flop energy optimization for ultra low voltage operation. 査読有り

Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. the 27th IEEE International System-on-Chip Conference (SOCC) 頁： 17 - 22 2014年10月

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. the 27th IEEE International System-on-Chip Conference (SOCC) 頁： 42 - 47 2014年9月

Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) 頁： 28 - 32 2014年3月

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation 査読有り

Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 96-A 巻 ( 12 ) 頁： 2499-2507 2013年12月

DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems 査読有り

K. Lee, T. Ishihara

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences 96-A 巻 ( 12 ) 頁： 2660-2667 2013年12月

Energy-efficient Dynamic Voltage and Frequency Scaling by P/N-performance Self-adjustment using Adaptive Body Bias, 査読有り

A.K.M. Mahfuzul Islam, Norihiro Kamae, Tohru Ishihara, Hidetoshi Onodera

Proc. the Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2013年10月

A standard cell optimization method for near-threshold voltage operations 査読有り

Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7606 巻頁： 32 - 41 2013年9月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Springer

Near-threshold voltage operation is a well-known solution for drastically improving the energy efficiency of microprocessors fabricated with the latest process technologies. However, it is not well studied how the optimal gate size of standard cells changes when the supply voltage of the microprocessors gets closer to the threshold voltage. This paper first shows an experimental observation that the optimal gate size for nearthreshold voltage which is 0.6V in this work is far from the optimal gate size for the nominal supply voltage which is 1.2V in our target process technology. Based on this fact, the paper next presents our cell optimization flow which finds the optimal gate sizes of individual standard cells operating at the near-threshold voltage. The experimental results show that, when operating at the 0.6V condition, the energy consumptions of several benchmark circuits synthesized with our standard cells optimized for the 0.6V condition can be reduced by 31% at the best case and by 23% on average compared with those of the same circuits synthesized with the cells optimized for the nominal supply voltage. © Springer-Verlag Berlin Heidelberg 2013.

DOI： 10.1007/978-3-642-36157-9_4

Scopus

J-GLOBAL

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その他リンク： https://dblp.uni-trier.de/db/conf/patmos/patmos2012.html#KondoNIO12

DLIC: Decoded Loop Instructions Caching for Energy-Aware Embedded Processors 査読有り国際共著国際誌

Gu Ji, Guo Hui, Ishihara Tohru

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 13 巻 ( 1 ) 頁： 6 - 26 2013年8月

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