Faculty Profiles - EDAHIRO Masato

Papers - EDAHIRO Masato

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GPU-accelerated Index Nested Loop Join on VoltDB Reviewed

N. Anh, S. Kato, M. Edahiro

Proceedings of the 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'16) Vol. WIP page： 6 2016.10

A Scalability Analysis of Many Cores and On-chip Mesh Networks on the TILE-Gx Platform Reviewed

Y. Liu, H. Sasaki, S. Kato, and M. Edahiro

Proceedings of IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) page： 46-52 2016.9

Monocular Vision-Based Localization Using ORB-SLAM with LIDAR-Aided Mapping in Real-World Robot Challenge Reviewed

A. Sujiwo, T. Ando, E. Takeuchi, Y. Ninomiya and M. Edahiro

Journal of Robotics and Mechatronics Vol. 28 ( 4 ) page： 479-490 2016.8

Monocular Vision-Based Localization Using ORB-SLAM with LIDAR-Aided Mapping in Real-World Robot Challenge Reviewed

A. Sujiwo, T. Ando, E. Takeuchi, Y. Ninomiya, M. Edahiro

Journal of Robotics and Mechatronics Vol. 28 ( 4 ) page： 479-490 2016.8

Accelerated Deformable Part Models on GPUs Reviewed

M. Hirabayashi, S. Kato, M. Edahiro, K. Takeda, and S. Mita

IEEE Transactions on Parallel & Distributed Systems Vol. 27 ( 6 ) page： 1589-1602 2016.6

Accelerated Deformable Part Models on GPUs Reviewed

Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Kazuya Takeda, Seiichi Mita

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Vol. 27 ( 6 ) page： 1589 - 1602 2016.6

Language：English Publishing type：Research paper (scientific journal) Publisher：IEEE COMPUTER SOC

Object detection is a fundamental challenge facing intelligent applications. Image processing is a promising approach to this end, but its computational cost is often a significant problem. This paper presents schemes for accelerating the deformable part models (DPM) on graphics processing units (GPUs). DPM is a well-known algorithm for image-based object detection, and it achieves high detection rates at the expense of computational cost. GPUs are massively parallel compute devices designed to accelerate dataparallel compute-intensive workload. According to an analysis of execution times, approximately 98 percent of DPM code exhibits loop processing, which means that DPM could be highly parallelized by GPUs. In this paper, we implement DPM on the GPU by exploiting multiple parallelization schemes. Results of an experimental evaluation of this GPU-accelerated DPM implementation demonstrate that the best scheme of GPU implementations using an NVIDIA GPU achieves a speed up of 8.6x over a naive CPU-based implementation.

DOI： 10.1109/TPDS.2015.2453962

Web of Science

A scalability analysis of many cores and on-chip mesh networks on the TILE-Gx platform Reviewed

Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro

2016 IEEE 10TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC) page： 46 - 52 2016

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing manycore processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor.
We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the twodimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.

DOI： 10.1109/MCSoC.2016.40

Web of Science

Parallel Design of Feedback Control Systems Utilizing Dead Time for Embedded Multicore Processors

SUZUKI Yuta, SATA Kota, KAKO Jun'ichi, YAMAGUCHI Kohei, ARAKAWA Fumio, EDAHIRO Masato

IEICE Transactions on Electronics Vol. E99.C ( 4 ) page： 491 - 502 2016

Language：English Publishing type：Research paper (scientific journal) Publisher：The Institute of Electronics, Information and Communication Engineers

This paper presents a parallelization method utilizing dead time to implement higher precision feedback control systems in multicore processors. The feedback control system is known to be difficult to parallelize, and it is difficult to deal with the dead time in control systems. In our method, the dead time is explicitly represented as delay elements. Then, these delay elements are distributed to the overall systems with equivalent transformation so that the system can be simulated or executed in parallel pipeline operation. In addition, we introduce a method of delay-element addition for parallelization. For a spring-mass-damper model with a dead time, parallel execution of the model using our technique achieves 3.4 times performance acceleration compared with its sequential execution on an ideal four-core simulation and 1.8 times on a cycle-accurate simulator of a four-core embedded processor as a threaded application on a real-time operating system.

DOI： 10.1587/transele.e99.c.491

Web of Science

CiNii Research

Pure Pursuit Revisited: Field Testing of Autonomous Vehicles in Urban Areas Reviewed

Hiroki Ohta, Naoki Akai, Eijiro Takeuchi, Shinpei Kato, Masato Edahiro

PROCEEDINGS OF 2016 IEEE 4TH INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS (CPSNA) page： 7 - 12 2016

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

In this paper, we aim to explore path following. We implement a path following component by referring to the existing Pure Pursuit algorithm. Using the simulation and field operational test, we identified the problem in the path following component. The main problems identified were with respect to vehicles meandering off the path, turning a corner, and the instability of steering control. Therefore, we apply some modifications to the Pure Pursuit[1] algorithm. We have also conducted the simulation and field operational tests again to evaluate these modifications.

DOI： 10.1109/CPSNA.2016.10

Web of Science

Simulinkモデルからのブロックレベル並列化 Reviewed

山口滉平，竹松慎弥，池田良裕，李瑞徳，鍾兆前，近藤真己（NEC情報システムズ），枝廣正人

組込みシステムシンポジウム (ESS2015) page：ポスター(21) 2015.10

Simulinkモデルからのブロックレベル並列化 Reviewed

山口滉平, 竹松慎弥, 池田良裕, 李瑞徳, 鍾兆前, 近藤真己, C情報システムズ, 枝廣正人

組込みシステムシンポジウム (ESS2015) page：ポスター(21) 2015.10

System-level design method for control systems with hardware-implemented interrupt handler Reviewed

Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro

Journal of Information Processing Vol. 23 ( 5 ) page： 532 - 541 2015.9

Language：English Publishing type：Research paper (scientific journal) Publisher：Information Processing Society of Japan

In this paper, we propose a system-level design method for control systems that enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to a deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates the target implementation from the model. Case studies on a motor control system show that the proposed method reduces the processor load, improves the latency of the interrupt processing, and enables the design space exploration for the control system.

DOI： 10.2197/ipsjjip.23.532

Scopus

System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler Reviewed

Y. Ando, S. Honda, H. Takada and M. Edahiro

Journal of Information Processing Vol. 23 ( 5 ) page： 532-541 2015.9

HexaCam: An FPGA-based Multi-view Camera System Reviewed

A. Monrroy, M. Hirabayashi, S. Kato, M. Edahiro, T. Miyoshi and S. Funada

Proceedings of the 3rd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'15) page： 48-53 2015.8

Real-Time Visualization of Moving Objects Reviewed

P. Ortal, S. Kato, and M. Edahiro

Proceedings of the 3rd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'15) page： 60-65 2015.8

Automatic synthesis of inter-heterogeneous-processor communication for programmable system-on-chip Reviewed

Y. Ando, Y. Ishida, S. Honda, H. Takada and M. Edahiro

IPSJ Transactions on System LSI Design Methodology Vol. 8 page： 95-99 2015.8

Automatic synthesis of inter-heterogeneous-processor communication for programmable system-on-chip Reviewed

Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro

IPSJ Transactions on System LSI Design Methodology Vol. 8 page： 95-99 2015.8

階層構造を持つメニーコアアーキテクチャへのタスクマッピング Reviewed

油谷創, 枝廣正人

情報処理学会論文誌 Vol. ５６ ( ８ ) page： 1568-1581 2015.8

階層構造を持つメニーコアアーキテクチャへのタスクマッピング Reviewed

油谷創, 枝廣正人

情報処理学会論文誌 Vol. 56 ( 8 ) page： 1568-1581 2015.8

Design Space Exploration of Control System with Hardware-implemented Interrupt Handler Reviewed

Y. Ando, S. Honda, H. Takada, M. Edahiro

Proceedings of International Conference on Information and Communication Technology for Embedded Systems (IC-ICTES) page： 1-6 2015.3

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Papers - EDAHIRO Masato