Faculty Profiles - EDAHIRO Masato

Papers - EDAHIRO Masato

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FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals Reviewed

Hiroaki, I, A Ikeno, M Kondo, J Sakai, M Edahiro

2005 INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS page： 178 - 183 2005

Language：English Publishing type：Research paper (international conference proceedings) Publisher：ASSOC COMPUTING MACHINERY

We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multi-grained separation mechanisms: coarse-grained processor-level separation of the basic-function domain from other domains for such downloaded applications, medium-grained OS-level separation, and fine-grained process-level separation within SELinux. Four new technologies, which include three enhancements to SELinux, support the FIDES platform: 1) bus filter logic for processor-level separation can be implemented as a small logic, 2) XIP kernels for memory-efficient OS-level separation can reduce memory requirements by 182%, 3) policy separation for enhanced process-level separation can apply policies 2.1 times faster at system boot-up, and 4) dynamic access control can provide secure Inter-Domain Communications (IDCs) with an overhead of only 4% for IDC system calls. We implemented SELinuxes on an ARM-based multiprocessor. Therefore, the best-suited platform to secure next generation mobile terminals is the FIDES platform, which can provide higher security as well as higher performance and lower power consumption on chip multiprocessors leading the current technology trend of microprocessors.

Web of Science

A new LSI Performance Prediction Model for interconnection analysis of future LSIs Reviewed

S Takahashi, M Edahiro, Y Hayashi

PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 page： 51 - 56 1998

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

As the interconnection delays control the LSI performance, the LSI performance estimation at higher design level becomes more difficult. In this paper a new LSI performance model for the estimation is described, which is made up by adopting a new clack-skew model to the SUSPENS (Stanford University System Performance Simulator) model. Using the model, it is cleared that a specific block size, where the line delay overcomes the block cycle time, becomes shorter as the LSI generation proceeds.

Web of Science

AN EFFICIENT ZERO-SKEW ROUTING ALGORITHM Reviewed

M EDAHIRO

31ST DESIGN AUTOMATION CONFERENCE - PROCEEDINGS 1994 page： 375 - 380 1994

DCT/IDCT PROCESSOR FOR HDTV DEVELOPED WITH DSP SILICON COMPILER Reviewed

T MIYAZAKI, T NISHITANI, M EDAHIRO, ONO, I, K MITSUHASHI

JOURNAL OF VLSI SIGNAL PROCESSING Vol. 5 ( 2-3 ) page： 151 - 158 1993.4

Language：English Publishing type：Research paper (scientific journal) Publisher：KLUWER ACADEMIC PUBL

This article presents a discrete cosine transform (DCI) processor for high definition television (HDTV) by using an extended version of DSP Silicon Compiler. The extension is mainly concerned with module generation functions.A matrix-vector product module composed of multiply-accumulators (MACs) is newly added to the silicon compiler. The compiler accomplishes placement of leaf-cells and routing between the cells, referring to a prototype layout for the MAC. The prototype, which consists of a Booth multiplier and a carry look ahead adder, is carefully designed to attain high operation speed. The processor developed by the silicon compiler carries out 8 x 8 DCT and its inverse transform (IDCT). In order to evaluate the newly extended functions in the compiler, the architecture employed for the processor is based on the matrix-vector product method. By using DSP Silicon Compiler and 0.8 mum triple metal CMOS technology, the DCT processor is easily implemented with error-free environment and achieves a 50MHz data rate, which meets Japanese HDTV base line signal processing. The chip is implemented on a 12.80 x 12.57 mm2 area.

Web of Science

A CLUSTERING-BASED OPTIMIZATION ALGORITHM IN ZERO-SKEW ROUTINGS Reviewed

M EDAHIRO

30TH DESIGN AUTOMATION CONFERENCE : PROCEEDINGS 1993 page： 612 - 616 1993

DELAY MINIMIZATION FOR ZERO-SKEW ROUTING Reviewed

M EDAHIRO

1993 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS page： 563 - 566 1993

A BUCKETING ALGORITHM FOR THE ORTHOGONAL SEGMENT INTERSECTION SEARCH PROBLEM AND ITS PRACTICAL EFFICIENCY Reviewed

M EDAHIRO, K TANAKA, T HOSHINO, T ASANO

ALGORITHMICA Vol. 4 ( 1 ) page： 61 - 76 1989

Practical use of Bucketing Techniques in Computational Geometry Reviewed

Takao Asano, Masato Edahiro, Hiroshi Imai, Masao Iri, Kazuo Murota

Machine Intelligence and Pattern Recognition Vol. 2 ( C ) page： 153 - 195 1985.1

Language：English Publishing type：Research paper (scientific journal)

Techniques for using “buckets” to improve the efficiency of several computational-geometrical algorithms are described, together with examples illustrating the practical importance of the bucketing techniques. Specifically, they are applied to the problems of minimum-weight perfect matchings in the plane, two-dimensional Voronoi diagrams, point location and range search in the plane, and shortest paths in networks. © 1985, Elsevier Inc. All rights reserved.

DOI： 10.1016/B978-0-444-87806-9.50011-6

Scopus

A new pointlocation algorithm and its practical efficiency-comparison with existing algorithms

EDAHIRO M.

ACM Trans. Graphics Vol. 3 page： 86 - 109 1984

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