Faculty Profiles - EDAHIRO Masato

Papers - EDAHIRO Masato

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Optimal Elliptic Curve Scalar Multiplication Using Double-Base Chains Reviewed

V. Suppakitpaisarn, M. Edahiro and H. Imai

International Journal of Digital Information and Wireless Communications (IJDIWC) Vol. 2 ( 1 ) page： 923-942 2012

Toward GPU-accelerated Traffic Simulation and Its Real-Time Challenge Reviewed

Manato Hirabayashi, Shinpei Kato, Masato Edahiro and Yuki Sugiyama

International Workshop on Real-Time and Distributed Computing in Emerging Applications (REACTION2012) page： 1-6 2012

Calculating average joint hamming weight for minimal weight conversion of d integers Reviewed

Vorapong Suppakitpaisarn, Masato Edahiro, Hiroshi Imai

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) Vol. 7157 page： 229 - 240 2012

Language：English Publishing type：Research paper (international conference proceedings)

In this paper, we propose an algorithm to calculate the efficiency of number representations in elliptic curve cryptography, average joint Hamming weight. The method uses Markov chains generated from a minimal weight conversion algorithm of d integers using the minimal weight conversion. With redundant representations using digit sets like {0, ±1}, it is possible to reduce computation time of the cryptosystem. Although larger digit sets make the computation time shorter, it requires longer preprocessing time. Therefore, the average joint Hamming weight is useful to evaluate digit sets. The Markov chains to find the average joint Hamming weight are derived automatically from the conversions. However, the number of states in these Markov chains is generally infinite. In [8], we propose an algorithm to reduce the number of states, but it is still unclear which representations the method can be applied for. In this paper, the finiteness of Markov chain with the existence of a stationary distribution is proven in a class of representation whose digit set D S be a finite set such that there exists a natural number Λ where D S ⊆ {0, ±1, ..., ±Λ} and {0,±1, ±Λ} ⊆ D S. The class covers most of the representation practically used in elliptic curve cryptography such as the representation which digit set are {0, ±1} and {0, ±1, ±3}. © 2012 Springer-Verlag.

DOI： 10.1007/978-3-642-28076-4_23

Scopus

Fastest Multi-Scalar Multiplication Based on Double-Base Chain Reviewed

V. Suppakitpaisarn, M. Edahiro, H. Imai

World Congress on Internet Security (WorldCIS-2012) page： 93-98 2012

Fast Elliptic Curve Cryptography Using Optimal Double-Base Chains Reviewed

V. Suppakitpaisarn, M. Edahiro, H. Imai

Proceedings of the International Conference on Informatics & Applications (ICIA2012) page： 190-204 2012

Efficient algorithms for extracting pareto-optimal hardware configurations in DEPS framework Reviewed

Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada

IPSJ Transactions on System LSI Design Methodology Vol. 5 page： 133 - 142 2012

Language：English Publishing type：Research paper (scientific journal)

A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice. © 2012 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.5.133

Scopus

Comparison of preemption schemes for partially reconfigurable FPGAs Reviewed

Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada

IEEE Embedded Systems Letters Vol. 4 ( 2 ) page： 45 - 48 2012

Language：English Publishing type：Research paper (scientific journal)

Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization. © 2012 IEEE.

DOI： 10.1109/LES.2012.2193660

Scopus

Optimal Elliptic Curve Cryptography Using Fibonacci Sequence Reviewed

V. Suppakitpaisarn, M. Edahiro, H. Imai

Proceedings of the 5th Thailand-Japan International Academic Conference (TJIA2012) page：未登録 2012

Toward GPU-accelerated Traffic Simulation and Its Real-Time Challenge Reviewed

Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Yuki Sugiyama

International Workshop on Real-Time and Distributed Computing in Emerging Applications (REACTION2012) page： 1-6 2012

Optimal Elliptic Curve Scalar Multiplication Using Double-Base Chains Reviewed

V. Suppakitpaisarn, M. Edahiro, H. Imai

International Journal of Digital Information and Wireless Communications (IJDIWC) Vol. 2 ( 1 ) page： 923-942 2012

Rainbow - An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs Reviewed

Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda and Hiroaki Takada

IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig) page： 416-421 2011.11

Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-power Multicore Reviewed

Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, and Hironori Kasahara

The 24th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2011) page： Session 1 2011.9

Rainbow: An OS extension for hardware multitasking on dynamically partially reconfigurable FPGAs Reviewed

Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada

Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 page： 416 - 421 2011

Language：English Publishing type：Research paper (international conference proceedings)

DPR (Dynamic Partial Reconfiguration) capability found in some of modern FPGAs allows implementation of a concept of a HW (Hardware) task, which similarly to its software counterpart has its state and shares time-multiplexed resources with the other tasks. While the new technology presents many advantages for embedded systems where run-time adaptability is an additional requirement, their efficient and easily portable implementations require a control software or an OS which would manage all the complexities of the underlying technology, providing an abstracted interface for the application programmer. This paper presents a novel and robust hardware multitasking extension for a conventional OS, managing task scheduling and configurations, and providing easy-to-use API (Application Programming Interface) for the application programmer. Scheduling is priority-based and takes advantage of task caching. Moreover, the extension is based on a developed design flow and embedded hardware platform allowing efficient task preemption, which can be utilized whenever it presents any benefits to the application. © 2011 IEEE.

DOI： 10.1109/ReConFig.2011.73

Scopus

A Robust Seamless Communication Architecture for Next-Generation Mobile Terminals on Multi-CPU SoCs Reviewed

Hiroaki Inoue, Junji Sakai, Masato Edahiro

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS Vol. 9 ( 3 ) 2010.2

Language：English Publishing type：Research paper (scientific journal) Publisher：ASSOC COMPUTING MACHINERY

We propose a robust seamless communication architecture that enables legacy mobile terminal software designed for single-CPU processors to be run on multi-CPU processors without any software modifications. This architecture features two new technologies: proxy processes, which help achieve the design of its user-level system-call hooking and a robust design method, which reduces bandwidth variation by systematic parameter optimization. Our evaluations confirmed that this architecture achieves fundamental features with satisfactory performance, that we have succeeded in getting actual mobile terminal software to run on three CPUs without modifying the software, and that the robust design method reduces bandwidth variation by 21%.

DOI： 10.1145/1698772.1698777

Web of Science

Parallelizing Fundamental Algorithms such as Sorting on Multi-core Processors for EDA Acceleration Reviewed

Masato Edahiro

PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 page： 230 - 233 2009

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

Fundamental algorithms should be parallelized to accelerate EDA software on multi-core architecture. In this paper, we introduce scalable algorithms that have scalability on multi-cores. As an example, a sorting algorithm, called Map Sort, is presented. This algorithm uses a map from subsets of input data to intervals on data range. Experimental results show that, in comparison with quick sort on a single CPU, processing time of Map Sort is comparable on a CPU and three times faster on four CPUs.

Web of Science

FIDES: An Advanced Chip Multiprocessor Platform for Secure Next Generation Mobile Terminals Reviewed

Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS Vol. 8 ( 1 ) 2008.12

Language：English Publishing type：Research paper (scientific journal) Publisher：ASSOC COMPUTING MACHINERY

We propose a secure platform on a chip multiprocessor, FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multigrained separation mechanisms. Four new technologies support the FIDES platform: bus filter logic, XIP kernels, policy separation, and dynamic access control. With these technologies, the FIDES platform can tolerate both application-level and kernel-level bugs on an actual download subsystem. Thus, the best-suited platform to secure next generation mobile terminals is FIDES.

DOI： 10.1145/1457246.1457247

Web of Science

MULTITASKING PARALLEL METHOD FOR HIGH-END EMBEDDED APPLIANCES Reviewed

Junji Sakai, Inoue Hiroaki, Sunao Torii, Masato Edahiro

IEEE MICRO Vol. 28 ( 5 ) page： 54 - 62 2008.9

Language：English Publishing type：Research paper (scientific journal) Publisher：IEEE COMPUTER SOC

EMBEDDED APPLIANCES SUCH AS HIGH-END CELL PHONES REQUIRE NOT ONLY HIGH PERFORMANCE BUT ALSO A PERFORMANCE GUARANTEE. THE AUTHORS DEMONSTRATE A PERFORMANCE GUARANTEE FRAMEWORK USING AN ASYMMETRIC MULTIPROCESSING APPROACH. THEY IMPLEMENTED THE PROPOSED METHOD ON A MULTICORE PROCESSOR USING LINUX. EVALUATION RESULTS SHOW THAT THE METHOD IMPROVES THE PERFORMANCE GUARANTEE WHILE MAINTAINING SOFTWARE COMPATIBILITY.

Web of Science

Processor virtualization for secure mobile terminals Reviewed

Hiroaki Inoue, Junji Sakai, Masato Edahiro

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS Vol. 13 ( 3 ) 2008.7

Language：English Publishing type：Research paper (scientific journal) Publisher：ASSOC COMPUTING MACHINERY

We propose a processor virtualization architecture, VIRTUS, to provide a dedicated domain for preinstalled applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies, namely, VMM asymmetrization, dynamic interdomain communication (IDC), and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor. Evaluations have shown that VMM asymmetrization results in significantly less performance degradation and LOC increase than do other VMMs. Further, dynamic IDC overhead is low enough, and virtualization-assist logic can be implemented in a sufficiently small area.

DOI： 10.1145/1367045.1367057

Web of Science

Towards scalable and secure execution platform for embedded systems Reviewed

Junji Sakai, Hiroaki Inoue, Masato Edahiro

PROCEEDINGS OF THE ASP-DAC 2007 page： 350 - + 2007

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

Reliability of embedded systems can be enhanced by multicore and partitioning approaches. Physical partitioning based on ANW multicore achieves runtime stability of multiple applications in a system and prevents the whole system shutdown as well even when a malicious code creeps in. Combined with logical partitioning by processor virtualization and SMP technologies, the multicore architecture could realize more flexible and more scalable platform for future embedded systems.

Web of Science

VIRTUS: A new processor virtualization architecture for security-oriented next-generation mobile terminals Reviewed

Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 page： 484 - + 2006

Language：English Publishing type：Research paper (international conference proceedings) Publisher：ASSOC COMPUTING MACHINERY

We propose a new processor virtualization architecture, VIRTUS, to provide a dedicated domain for pre-installed applications and virtualized domains for downloaded native applications. With it security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies: VMM asymmetrization, dynamic inter-domain communication and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor.

Web of Science

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Papers - EDAHIRO Masato