Faculty Profiles - SUDA Jun

Papers - SUDA Jun

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Improved on-current of 4H-SiC MOSFETs with a three-dimensional gate structure

Nanen Y., Yoshioka H., Noborio M., Suda J., Kimoto T.

Materials Science Forum Vol. 615 617 page： 753 - 756 2009

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Materials Science Forum

4H-SiC (0001) MOSFETs with a three-dimensional gate structure, which has a top channel on the (0001) face and side-wall channels on the {11-20} face have been fabricated. The three-dimensional gate structures with a 1-5 μm width and 0.8 μm height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300°C. The fabricated MOSFETs have exhibited superior characteristics: ION / IOFF, the subthreshold swing and VTH are 1010, 250 mV/decade and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1 μm-wide MOSFET is ten times higher than that of a conventional planar MOSFET. © (2009) Trans Tech Publications.

DOI： 10.4028/www.scientific.net/MSF.615-617.753

Improved current gain in GaN/SiC Heterojunction Bipolar Transistors by insertion of ultra-thin AlN layer at emitter-junction

Miyake H., Kimoto T., Suda J.

Materials Science Forum Vol. 615 617 page： 979 - 982 2009

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Materials Science Forum

GaN/SiC Heterojunction Bipolar Transistors (HBTs) with ultra-thin AlN insertion layers at the n-GaN/p-SiC emitter junction are proposed to improve carrier injection efficiency. The current-voltage characteristics of n-GaN/AlN/p-SiC heterojunctions have exhibited very small reverse leakage and good rectification. The capacitance-voltage measurement have revealed that the conduction band offset between n-GaN and p-SiC has been reduced from -0.74 eV to -0.54 eV by insertion of AlN, indicating that the GaN/AlN/SiC heterojunction may show better electron-injection efficiency. A significantly improved common-base current gain (α∼0.2) is obtained for GaN/AlN/SiC HBTs with initial N* pre-irradiation, while it was very low (α∼0.001) for GaN/SiC HBTs without AlN layers. © (2009) Trans Tech Publications.

DOI： 10.4028/www.scientific.net/MSF.615-617.979

High channel mobility in P-channel MOSFETs fabricated on 4H-SiC (0001) and non-basal faces

Noborio M., Suda J., Kimoto T.

Materials Science Forum Vol. 615 617 page： 789 - 792 2009

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Materials Science Forum

P-channel MOSFETs have been fabricated on 4H-SiC (0001) face as well as on 4H-SiC (03-38) and (11-20) faces. The gate oxides were formed by thermal oxidation in dry N2O ambient, which is widely accepted to improve the performance of n-channel SiC MOSFETs. The p-channel SiC MOSFETs with N 2O-grown oxides on 4H-SiC (0001), (03-38), and (11-20) faces show a channel mobility of 7 cm2/Vs, 11 cm2/Vs, and 17 cm 2/Vs, respectively. From the quasi-static C-V curves measured by using gate-controlled diodes, the interface state density was calculated by an original method. The interface state density was the lowest at the SiO 2/4H-SiC (03-38) interface (about 1×1012 cm -2eV-1 at EV + 0.2 eV). The authors have applied deposited oxides to the 4H-SiC p-channel MOSFETs. The (0001), (03-38), and (11-20) MOSFETs with deposited oxides exhibit a channel mobility of 10 cm 2/Vs, 13 cm2/Vs, and 17 cm2/Vs, respectively. The deposited oxides are one of effective approaches to improve both n-channel and p-channel 4H-SiC MOS devices. © (2009) Trans Tech Publications.

DOI： 10.4028/www.scientific.net/MSF.615-617.789

Spatial profiling of planar defects in 4H-SiC epilayers using micro-photoluminescence mapping

Feng G., Suda J., Kimoto T.

Materials Science Forum Vol. 615 617 page： 245 - 250 2009

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Materials Science Forum

The micro-photoluminescence (micro-PL) spectroscopy and its intensity mapping have been utilized to investigate the planar defects, stacking faults (SFs), in 4H-SiC epilayers. Strong PL emissions from the SFs are observed even at room temperature. It is found that each kind of SF shows the distinct PL emission behaviours. Three kinds of SFs: intrinsic Frank SFs, double Shockley SFs, and in-grown SFs, have been identified in the samples based on the micro-PL spectra. At the same time, the micro-PL intensity mapping at the emission band of each SF has been performed to spatially profile the SFs. The shapes, distributions, and densities of SFs in the epilayers are then presented. The PL emission behaviours of each SF at low temperature are also studied. © (2009) Trans Tech Publications, Switzerland.

DOI： 10.4028/www.scientific.net/MSF.615-617.245

The temperature dependence of the refractive indices of GaN and AlN from room temperature up to 515 degrees C

Watanabe Naoki, Kimoto Tsunenobu, Suda Jun

JOURNAL OF APPLIED PHYSICS Vol. 104 ( 10 ) 2008.11

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Journal of Applied Physics

The temperature dependence of the refractive indices of GaN and AlN was investigated in the wavelength range from the near band edge (367 nm for GaN and 217 nm for AlN) to 1000 nm and the temperature range from room temperature to 515 °C. Optical interference measurements with vertical incident configuration were employed to precisely evaluate the ordinary refractive indices. © 2008 American Institute of Physics.

DOI： 10.1063/1.3021148

N2O-grown oxides/4H-SiC (0001), (0338), and (1120) interface properties characterized by using p-type gate-controlled diodes

Noborio Masato, Suda Jun, Kimoto Tsunenobu

APPLIED PHYSICS LETTERS Vol. 93 ( 19 ) 2008.11

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Applied Physics Letters

The N2 O -grown SiO2 /4H-SiC (0001), (033̄8), and (112̄0) interface properties in p -channel metal-oxide-semiconductor field-effect transistors (MOSFETs) have been characterized by using gate-controlled diodes. Although the inversion layer is not formed in simple SiC MOS capacitors at room temperature due to its large bandgap, a standard low frequency capacitance-voltage (C-V) curve can be obtained for the gate-controlled diodes, owing to the supply of minority carriers from the source region. From the quasistatic C-V curves measured by using gate-controlled diodes, the interface state density has been evaluated by an original method proposed in this study. The interface state density near the valence band edge evaluated by the method is the lowest at the oxides/ 4H-SiC (033̄8) interface. Comparison with the channel mobility is also discussed. © 2008 American Institute of Physics.

DOI： 10.1063/1.3028016

Surface Morphologies of 4H-SiC(11(2)over-bar0) and (1(1)over-bar00) Treated by High-Temperature Gas Etching

Horita Masahiro, Kimoto Tsunenobu, Suda Jun

JAPANESE JOURNAL OF APPLIED PHYSICS Vol. 47 ( 11 ) page： 8388 - 8390 2008.11

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Japanese Journal of Applied Physics

The impact of HCl/H2 high-temperature gas-etching on the surface morphologies of 4H-SiC(1120) and (1100) faces is investigated by atomic force microscopy (AFM). Very flat surfaces are obtained on both (1120) and (11̄00) faces after gas-etching when the substrate surfaces are initially treated by chemical mechanical polishing to remove polishing scratches. The root-mean square roughness values of gas-etched (112̄0) and (11̄00) substrates are 0.07 and 0.11nm, respectively. Within AFM resolution limits no atomic steps are observed on the very flat surfaces of (1120) substrates. On the other hand, clear step-and-terrace structures are observed on (1100) substrates after gas-etching and the height of the steps (2.7Å) corresponding to the lattice spacing between 4H-SiC(1100) planes (= √3a/2). © 2008 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.47.8388

Comprehensive analysis of multiple-reflection effects on rotational Maker-fringe experiments

Abe M., Shoji I., Suda J., Kondo T.

Journal of the Optical Society of America B: Optical Physics Vol. 25 ( 10 ) page： 1616 - 1624 2008.10

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Journal of the Optical Society of America B: Optical Physics

What we believe to be a new mathematical procedure has been proposed for analyzing the rotational Maker-fringe data taking account of the effects of multiple reflections and interferences of the fundamental and second-harmonic beams in anisotropic plane-parallel plates. In the present formalisms partial overlaps of the fundamental and second-harmonic beams are fully included. A comparison between numerical simulations based on the proposed formalisms and experimental data obtained for a high-quality (0001) plane-parallel plate of 6H-SiC revealed the validity of our theory. We have determined the magnitudes of the nonlinear optical coefficients of 6H-SiC as d31=d32 = 6.7±0.8 pm/V, d15=d24 = 6.4±1.1 pm/V, and d33 = -9.7±8.0 pm/V. © 2008 Optical Society of America.

DOI： 10.1364/JOSAB.25.001616

Improved Performance of 4H-SiC Double Reduced Surface Field Metal-Oxide-Semiconductor Field-Effect Transistors by Increasing RESURF Doses

Noborio Masato, Suda Jun, Kimoto Tsunenobu

APPLIED PHYSICS EXPRESS Vol. 1 ( 10 ) page： 1014031 - 1014033 2008.10

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Applied Physics Express

For further improvement of lateral power devices, 4H-SiC double reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) with high doses in RESURF region have been fabricated and characterized. The drift resistance was decreased and the breakdown voltage was increased with increasing RESURF doses, although breakdown occurs in the oxide when the RESURF doses are too high. The increase of drift resistance in double RESURF MOSFETs at elevated temperature was smaller than that in single RESURF MOSFETs, due to the higher doping concentration in the RESURF region. The fabricated 4H-SiC(0001) double RESURF MOSFETs exhibited a breakdown voltage (VB) of 1540V and an on-resistance (RON) of 55mΩcm2. The figure-of-merit (VB2/R ON) of the fabricated device is 43MW/cm2, which is the highest value compared with those reported in lateral MOSFETs. © 2008 The Japan Society of Applied Physics.

DOI： 10.1143/APEX.1.101403

Improvement of Channel Mobility in Inversion-Type n-Channel GaN Metal-Oxide-Semiconductor Field-Effect Transistor by High-Temperature Annealing

Yamaji Kazuki, Noborio Masato, Suda Jun, Kimoto Tsunenobu

JAPANESE JOURNAL OF APPLIED PHYSICS Vol. 47 ( 10 ) page： 7784 - 7787 2008.10

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Japanese Journal of Applied Physics

Inversion- and depletion-type GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated on p- and n--type GaN epitaxial layers, respectively, grown on n+-type on-axis 4H-SiC(0001) substrates. After gate SiO2 was deposited by plasma-enhanced chemical vapor deposition at 350 °C, high-temperature annealing in N2 was carried out to modify the interface. The channel mobility was enhanced with increasing annealing temperature. The device annealed in N2 at 1100 °C after SiO2 deposition showed an inversion channel mobility of 108cm2.V-1.s-1 at a gate voltage of 15 V. The authors also fabricated MOS capacitors on n--type GaN and characterized the interface state density at the SiO2/GaN interface from capacitance-voltage measurements using the Terman method, of which density was estimated to be in the range of (6-10) × 1011 cm -2.eV-1 at an energy level of 0.2eV below the conduction band edge. The interface state density tended to decrease with increasing annealing temperature, resulting in the improvement of the channel mobility. © 2008 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.47.7784

Comprehensive analysis of multiple-reflection effects on rotational Maker-fringe experiments

Abe Makoto, Shoji Ichiro, Suda Jun, Kondol Takashi

JOURNAL OF THE OPTICAL SOCIETY OF AMERICA B-OPTICAL PHYSICS Vol. 25 ( 10 ) page： 1616 - 1624 2008.10

Impact of surface step heights of 6H-SiC (0001) vicinal substrates in heteroepitaxial growth of 2H-AlN

Okumura H., Horita M., Kimoto T., Suda J.

APPLIED SURFACE SCIENCE Vol. 254 ( 23 ) page： 7858 - 7860 2008.9

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Applied Surface Science

Impact of step height of silicon carbide (SiC) substrates on heteroepitaxial growth of aluminum nitride (AlN) was investigated. Step-and-terrace structures with various step heights, 6 monolayer (ML), 3ML and 1ML, were formed on 6H-SiC (0 0 0 1) vicinal substrates by high-temperature gas etching. 2H-AlN layers were grown on the substrate by plasma-assisted molecular-beam epitaxy (MBE) and then these layers were characterized by atomic-force microscopy (AFM) and X-ray diffraction (XRD). High-quality AlN can be grown on SiC substrates with 6ML- and 3ML-height step, while AlN grown on SiC substrates with 1ML-height step exhibited inferior crystalline quality. A model for high-quality AlN growth on SiC substrates with 3ML-height step is proposed. © 2008 Elsevier B.V. All rights reserved.

DOI： 10.1016/j.apsusc.2008.02.165

4H-SiC double RESURF MOSFETs with a record performance by increasing RESURF dose

Noborio M., Suda J., Kimoto T.

Proceedings of the International Symposium on Power Semiconductor Devices and ICs page： 263 - 266 2008.9

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Proceedings of the International Symposium on Power Semiconductor Devices and ICs

For further improvement of lateral power devices, 4H-SiC double RESURF MOSFETs with high RESURF doses have been fabricated and characterized. The drift resistance was decreased and the breakdown voltage was increased with increasing RESURF doses, although oxide brekaodown occurs when the RESURF doses are too high. The increase in drift resistance at elevated temperature was smaller for double RESURF MOSFETs than single RESURF MOSFETs, due to the higher doping concentration in the RESURF region. The fabricated 4H-SiC (0001) double RESURF MOSFETs exhibited a breakdown voltage (VB) of 1430 V and an on-resistance (RON) of 57 mΩcm2, and the MOSFETs on 4H-SiC (0001) face demonstrated a higher breakdown voltage of 1550 V and a lower on-resistance of 54 mΩcm2. The figure-of-merit (V B2/RON) of the fabricated device on Si face and C face is 36 MW/cm2 and 44 MW/cm2, respectively, which is the highest value among any lateral MOSFETs ever reported. ©2008 IEEE.

DOI： 10.1109/ISPSD.2008.4538949

Nonpolar 4H-AlN grown on 4H-SiC (1(1)over-bar00) with reduced stacking fault density realized by persistent layer-by-layer growth

Horita Masahiro, Kimoto Tsunenobu, Suda Jun

APPLIED PHYSICS LETTERS Vol. 93 ( 8 ) 2008.8

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Applied Physics Letters

Nonpolar AlN layers were grown on 4H-SiC (1 1- 00) substrates by plasma-assisted molecular-beam epitaxy. By using SiC substrates with well-formed step-and-terrace structures, stable layer-by-layer growth of 4H-AlN (1 1- 00) can be realized. The layer-by-layer growth is confirmed by observations of anisotropic two-dimensional AlN islands on the grown surface as well as persistent reflection high-energy electron diffraction intensity oscillations. Cross-sectional transmission electron microscopy observations reveal that stacking fault generation during growth is suppressed and the stacking fault density is reduced to 1× 106 cm-1. © 2008 American Institute of Physics.

DOI： 10.1063/1.2976559

4H-SiC MIS capacitors and MISFETs with deposited SiNx/SiO2 stack-gate structures

Noborio Masato, Suda Jun, Kimoto Tsunenobu

IEEE TRANSACTIONS ON ELECTRON DEVICES Vol. 55 ( 8 ) page： 2054 - 2060 2008.8

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：IEEE Transactions on Electron Devices

SiNx/SiO2 stack-gate structures, followed by N2O annealing, have been investigated to improve the 4H-SiC metal - insulator - semiconductor (MIS) interface quality. Capacitance - voltage measurements on fabricated stack-gate MIS capacitors have indicated that the interface trap density is reduced by postdeposition annealing in N2O at 1300 °C. When the MIS capacitor with a SiNx/SiO2 thickness of 10 nm/50 nm was annealed in N2O for 2 h, the interface trap density at EC - 0.2 eV is below 1 × 1011 cm-2eV-1. Oxidation of SiNx during N2O annealing has resulted in the improvement of SiCMIS interface characteristics, as well as dielectric properties. The fabricated MISFETs with SiNx/SiO2 stack-gate structure annealed in N2O demonstrate a reasonably high channel mobility of 32 cm2/V · s on the (0001)Si face and 40 cm2/V · s on the (0001)C face. © 2008 IEEE.

DOI： 10.1109/TED.2008.926644

Simulation and experimental study on the junction termination structure for high-voltage 4H-SiC PiN diodes

Hiyoshi Toru, Hori Tsutomu, Suda Jun, Kimoto Tsunenobu

IEEE TRANSACTIONS ON ELECTRON DEVICES Vol. 55 ( 8 ) page： 1841 - 1846 2008.8

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：IEEE Transactions on Electron Devices

Designing and fabrication of 10-kV 4H-SiC PiN diodes with an improved junction termination structure have been investigated. An improved bevel mesa structure and a single-zonejunction termination extension (JTE) have been employed to achieve a high breakdown voltage (≥10 kV)). The improved bevel mesa structure, nearly a vertical sidewall at the edge of the p-n junction and a gradual slope at the mesa bottom, has been fabricated by reactive ion etching. The effectiveness of the improved bevel mesa structure has been experimentally demonstrated. The JTE region has been optimized by device simulation, and the JTE dose dependence of the breakdown voltage has been compared with experimental results. A 4H-SiC PiN diode with a JTE dose of 1.1 × 1013 cm-2 has exhibited a high blocking voltage of 10.2 kV. The locations of electric field crowding and breakdown are also discussed. © 2008 IEEE.

DOI： 10.1109/TED.2008.926643

Hydrogen implantation and annealing-induced exfoliation process in SiC wafers with various crystal orientations

Senga Kei, Kimoto Tsunenobu, Suda Jun

JAPANESE JOURNAL OF APPLIED PHYSICS Vol. 47 ( 7 ) page： 5352 - 5354 2008.7

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Japanese Journal of Applied Physics

The influence of time and temperature were investigated in wafer exfoliation process by hydrogen implantation for 4H-SiC wafers with various orientations, on-axis and 8° off-axis (0001), (11̄00), and (112̄0). Void formation occurs isotropically for all the orientations investigated. The blistering rate (R) of 4H-SiC was found to be dependent on the crystal orientation of the wafer; RSiC(0001) on-axis ≲ R SiC(0001) 8° off-axis ≲ RSiC(11̄00) < RSiC(11̄20). The blistering rate of (112̄0) is faster than those of the other three orientations. This result suggests that different annealing conditions are needed when fabricating SiC-on-insulator wafers of different crystal orientations. © 2008 The Japan Society of Applied Physics.

DOI： 10.1143/JJAP.47.5352

Lifetime-killing defects in 4H-SiC epilayers and lifetime control by low-energy electron irradiation

Kimoto Tsunenobu, Danno Katsunori, Suda Jun

PHYSICA STATUS SOLIDI B-BASIC SOLID STATE PHYSICS Vol. 245 ( 7 ) page： 1327 - 1336 2008.7

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Physica Status Solidi (B) Basic Research

Carrier lifetimes in n-type 4H-SiC epilayers have been investigated by differential microwave photoconductance decay measurements. Through a correlation study between lifetime and various deep levels, the Z1/2 and/or EH6/7 centers have been identified as effective recombination centers. When the Z1/2 (and EH6/7) concentration is higher than 1013 cm-3, the inverse carrier lifetime is in proportion to the trap concentration, and the lifetime increases with increasing excitation intensity (density of irradiated photons). Alternartively, other recombination processes limit the lifetime when the Z1/2 concentration is less than 1013 cm-3. In this case, the carrier lifetime is decreased by increasing the excitation intensity. Surface recombination and recombination in the substrate have been suggested based on numerical analyses as the other recombination paths. By controlling the Z 1/2 (and EH6/7) concentration by low-energy electron irradiation, lifetime control has been achieved. © 2008 Wiley-VCH Verlag GmbH & Co. KGaA.

DOI： 10.1002/pssb.200844076

Characterization of stacking faults in 4H-SiC epilayers by room-temperature microphotoluminescence mapping

Feng Gan, Suda Jun, Kimoto Tsunenobu

APPLIED PHYSICS LETTERS Vol. 92 ( 22 ) 2008.6

Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Applied Physics Letters

The stacking faults (SFs) in 4H-SiC epilayers have been characterized by microphotoluminescence spectroscopy and photoluminescence (PL) intensity mapping at room temperature. Three kinds of SFs, intrinsic Frank SFs, double Shockley SFs, and in-grown SFs, have been identified in the samples. Each kind of SF shows the distinct PL emission located at 420, 500, and 455 nm, respectively. The shapes and distributions of SFs have been profiled by micro-PL intensity mapping. The formation mechanisms of each SF are also discussed. © 2008 American Institute of Physics.

DOI： 10.1063/1.2937097

4H-SiC double RESURF MOSFETs with a record performance by increasing RESURF dose

Noborio Masato, Suda Jun, Kimoto Tsunenobu

ISPSD 08: PROCEEDINGS OF THE 20TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS page： 263 - 266 2008

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