研究者詳細 - 枝廣　正人

論文 - 枝廣　正人

分割表示 217 件中 161 - 180 件目／全件表示 >>

Simple One-to-one Architecture for Parallel Execution of Embedded Control Systems 査読有り

R. Nakamura, F. Arakawa, and M. Edahiro

Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) 頁： 25-30 2014年8月

GPU-accelerated Point Cloud Mapping for Autonomous Driving 査読有り

Y. Kitsukawa, S. Kato, and M. Edahiro

Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) 頁： WiP Session 2014年8月

Evaluation of GNSS for Autonomous Driving 査読有り

H. Ohta, S. Kato, and M. Edahiro

Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) 頁： WiP Session 2014年8月

Evaluation of GNSS for Autonomous Driving 査読有り

H. Ohta, S. Kato, M. Edahiro

Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) 頁： WiP Session 2014年8月

GPU-accelerated Point Cloud Mapping for Autonomous Driving 査読有り

Y. Kitsukawa, S. Kato, M. Edahiro

Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) 頁： WiP Session 2014年8月

Simple One-to-one Architecture for Parallel Execution of Embedded Control Systems 査読有り

R. Nakamura, F. Arakawa, M. Edahiro

Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) 頁： 25-30 2014年8月

Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors 査読有り

Y. Suzuki, K. Sata (Toyota), J. Kako (Toyota), K. Yamaguchi, F. Arakawa, and M. Edahiro

Proceedings of COOL Chips XVII 頁： VI-2 2014年4月

Power and Performance Characterization and Modeling of GPU-accelerated Systems 査読有り

Y. Abe, H. Sasaki, S. Kato, K. Inoue, M. Edahiro, and M. Peres

Proceedings of the 28th IEEE International Parallel and Distributed Processing Symposium (IPDPS'14) 頁： 113-122 2014年3月

Establishing a standard interface between multi-manycore and software tools - SHIM 査読有り

Masaki Gondo, Fumio Arakawa, Masato Edahiro

2014 IEEE COOL CHIPS XVII 頁： VI-1 2014年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

The multi core processors are becoming norm and a processor with even more than a hundred of cores are emerging. These inherently require wide range of software tools to help software developers. However, supporting these complex hardware by the tools require significant effort by the tool vendors, and each invest in adapting the new hardware by modifying their tools or creating proprietary configuration files, while often the similar set of hardware architectural information are needed. The SHIM, Software-Hardware Interface for Multi-many-core, is a joint industrial and academic effort to standardize the interface between the multicore hardware and the software tools. This extended abstract introduces SHIM, the overall architecture, the schema used, the use-cases, and a prototype tool to foster the adaption of the interface.

Web of Science

Power and Performance Characterization and Modeling of GPU-Accelerated Systems 査読有り

Yuki Abe, Koji Inoue, Hiroshi Sasaki, Masato Edahiro, Shinpei Kato, Martin Peres

2014 IEEE 28TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM 頁： 113-122 2014年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Graphics processing units (GPUs) provide an order-of-magnitude improvement on peak performance and performance-per-watt as compared to traditional multicore CPUs. However, GPU-accelerated systems currently lack a generalized method of power and performance prediction, which prevents system designers from an ultimate goal of dynamic power and performance optimization. This is due to the fact that their power and performance characteristics are not well captured across architectures, and as a result, existing power and performance modeling approaches are only available for a limited range of particular GPUs. In this paper, we present power and performance characterization and modeling of GPU-accelerated systems across multiple generations of architectures. Characterization and modeling both play a vital role in optimization and prediction of GPU-accelerated systems. We quantify the impact of voltage and frequency scaling on each architecture with a particularly intriguing result that a cutting-edge Kepler-based GPU achieves energy saving of 75% by lowering GPU clocks in the best scenario, while Fermi-and Tesla-based GPUs achieve no greater than 40% and 13%, respectively. Considering these characteristics, we provide statistical power and performance modeling of GPU-accelerated systems simplified enough to be applicable for multiple generations of architectures. One of our findings is that even simplified statistical models are able to predict power and performance of cutting-edge GPUs within errors of 20% to 30% for any set of voltage and frequency pair.

DOI： 10.1109/IPDPS.2014.23

Web of Science

Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors 査読有り

Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro

2014 IEEE COOL CHIPS XVII 頁： VI-2 2014年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.

Web of Science

Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors 査読有り

Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro

2014 IEEE COOL CHIPS XVII E99-C 巻 ( 4 ) 頁： 491-502 2014年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Web of Science

Data Transfer Matters for GPU Computing 査読有り

Y. Fujii, T. Azumi, N. Nishio, and S. Kato, and M. Edahiro

Proceedings of the 19th IEEE International Conference on Parallel and Distributed Systems (ICPADS'13) 頁： 275 - 282 2013年12月

Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs 査読有り

Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, and Hiroaki Takada

International Journal of Reconfigurable Computing 2013 巻頁： ID: 789134 2013年10月

Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs 査読有り

Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada

International Journal of Reconfigurable Computing 2013 巻頁： ID: 789134 2013年10月

GPU Implementations of Object Detection using HOG Features and Deformable Models 査読有り

M. Hirabayashi, S. Kato, M. Edahiro, K. Takeda, T. Kawano, and S. Mita

Proceedings of the 1st IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'13) 頁： 106-111 2013年8月

Data Transfer Matters for GPU Computing 査読有り

Yusuke Fujii, Takuya Azumi, Nobuhiko Nishio, Shinpei Kato, Masato Edahiro

2013 19TH IEEE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS 2013) 頁： 275 - 282 2013年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Graphics processing units (GPUs) embrace many-core compute devices where massively parallel compute threads are offloaded from CPUs. This heterogeneous nature of GPU computing raises non-trivial data transfer problems especially against latency-critical real-time systems. However even the basic characteristics of data transfers associated with GPU computing are not well studied in the literature. In this paper, we investigate and characterize currently-achievable data transfer methods of cutting-edge GPU technology. We implement these methods using open-source software to compare their performance and latency for real-world systems. Our experimental results show that the hardware-assisted direct memory access (DMA) and the I/O read-and-write access methods are usually the most effective, while on-chip microcontrollers inside the GPU are useful in terms of reducing the data transfer latency for concurrent multiple data streams. We also disclose that CPU priorities can protect the performance of GPU data transfers.

DOI： 10.1109/ICPADS.2013.47

Web of Science

GPU implementations of object detection using HOG features and deformable models 査読有り

Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Kazuya Takeda, Taiki Kawano, Seiichi Mita

2013 IEEE 1st International Conference on Cyber-Physical Systems, Networks, and Applications, CPSNA 2013 頁： 106 - 111 2013年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE Computer Society

Vision-based object detection using camera sensors is an essential piece of perception for autonomous vehicles. Various combinations of features and models can be applied to increase the quality and the speed of object detection. A well-known approach uses histograms of oriented gradients (HOG) with deformable models to detect a car in an image [15]. A major challenge of this approach can be found in computational cost introducing a real-time constraint relevant to the real world. In this paper, we present an implementation technique using graphics processing units (GPUs) to accelerate computations of scoring similarity of the input image and the pre-defined models. Our implementation considers the entire program structure as well as the specific algorithm for practical use. We apply the presented technique to the real-world vehicle detection program and demonstrate that our implementation using commodity GPUs can achieve speedups of 3x to 5x in frame-rate over sequential and multithreaded implementations using traditional CPUs. © 2013 IEEE.

DOI： 10.1109/CPSNA.2013.6614255

Scopus

Evaluation of power consumption at execution of multiple automatically parallelized and power controlled media applications on the RP2 low-power multicore 査読有り

Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, Hironori Kasahara

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7146 巻頁： 31 - 45 2013年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper evaluates an automatic power reduction scheme of OSCAR automatic parallelizing compiler having power reduction control capability when multiple media applications parallelized by the OSCAR compiler are executed simultaneously on RP2, a 8-core multicore processor developed by Renesas Electronics, Hitachi, and Waseda University. OSCAR compiler enables the hierarchical multigrain parallel processing and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating and power gating for each processor core using the OSCAR multi-platform API. The RP2 has eight SH4A processor cores, each of which has power control mechanisms such as DVFS, clock gating and power gating. First, multiple applications with relatively light computational load are executed simultaneously on the RP2. The average power consumption of power controlled eight AAC encoder programs, each of which was executed on one processor, was reduced by 47%, (to 1.01W), against one AAC encoder execution on one processor (from 1.89W) without power control. Second, when multiple intermediate computational load applications are executed, the power consumptions of an AAC encoder executed on four processors with the power reduction control was reduced by 57% (to 0.84W) against an AAC encoder execution on one processor (from 1.95W). Power consumptions of one MPEG2 decoder on four processors with power reduction control was reduced by 49% (to 1.01W) against one MPEG2 decoder execution on one processor (from 1.99W). Finally, when a combination of a high computational load application program and an intermediate computational load application program are executed simultaneously, the consumed power reduced by 21% by using twice number of cores for each application. This paper confirmed parallel processing and power reduction by OSCAR compiler are efficient for multiple application executions. In execution of multiple light computational load applications, power consumption increases only 12% for one application. Parallel processing being applied to intermediate computational load applications, power consumption of executing one application on one processor core (1.49W) is almost same power consumption of two applications on eight processor cores (1.46W). © 2013 Springer-Verlag.

DOI： 10.1007/978-3-642-36036-7_3

Scopus

Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework 査読有り

Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro and Hiroaki Takada

IPSJ Transactions on System LSI Design Methodology. 5 巻頁： 133-142 2012年8月

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