研究者詳細 - 枝廣　正人

論文 - 枝廣　正人

分割表示 217 件中 181 - 200 件目／全件表示 >>

Comparison of Preemption Schemes for Partially Reconfigurable FPGAs 査読有り

Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada

IEEE Embedded Systems Letters 4 巻 ( 2 ) 頁： 45-48 2012年6月

Calculating Average Joint Hamming Weight for Minimal Weight Conversion of d Integers 査読有り

V. Suppakitpaisarn, M. Edahiro and H. Imai

WALCOM: Algorithms and Computation, Springer, 2012, Lecture Notes in Computer Science 7157 巻頁： 229-240 2012年2月

Fast Elliptic Curve Cryptography Using Minimal Weight Conversion of d Integers 査読有り

V. Suppakitpaisarn, M. Edahiro and H. Imai

Proceedings of the Tenth Australasian Information Security Conference (AISC 2012), ACS, 2012, Conferences in Research and Practice in Information Technology 125 巻頁： 15-26 2012年1月

Fast Elliptic Curve Cryptography Using Minimal Weight Conversion of d Integers 査読有り

V. Suppakitpaisarn, M. Edahiro, H. Imai

Proceedings of the Tenth Australasian Information Security Conference (AISC 2012), ACS, 2012, Conferences in Research and Practice in Information Technology 125 巻頁： 15-26 2012年1月

Optimal Elliptic Curve Scalar Multiplication Using Double-Base Chains 査読有り

V. Suppakitpaisarn, M. Edahiro and H. Imai

International Journal of Digital Information and Wireless Communications (IJDIWC) 2 巻 ( 1 ) 頁： 923-942 2012年

Toward GPU-accelerated Traffic Simulation and Its Real-Time Challenge 査読有り

Manato Hirabayashi, Shinpei Kato, Masato Edahiro and Yuki Sugiyama

International Workshop on Real-Time and Distributed Computing in Emerging Applications (REACTION2012) 頁： 1-6 2012年

Optimal Elliptic Curve Cryptography Using Fibonacci Sequence 査読有り

V. Suppakitpaisarn, M. Edahiro and H. Imai

Proceedings of the 5th Thailand-Japan International Academic Conference (TJIA2012) 頁：未登録 2012年

Fast Elliptic Curve Cryptography Using Optimal Double-Base Chains 査読有り

V. Suppakitpaisarn, M. Edahiro and H. Imai

Proceedings of the International Conference on Informatics & Applications (ICIA2012) 頁： 190-204 2012年

Fastest Multi-Scalar Multiplication Based on Double-Base Chain 査読有り

V. Suppakitpaisarn, M. Edahiro and H. Imai

World Congress on Internet Security (WorldCIS-2012) 頁： 93-98 2012年

Calculating average joint hamming weight for minimal weight conversion of d integers 査読有り

Vorapong Suppakitpaisarn, Masato Edahiro, Hiroshi Imai

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 7157 巻頁： 229 - 240 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

In this paper, we propose an algorithm to calculate the efficiency of number representations in elliptic curve cryptography, average joint Hamming weight. The method uses Markov chains generated from a minimal weight conversion algorithm of d integers using the minimal weight conversion. With redundant representations using digit sets like {0, ±1}, it is possible to reduce computation time of the cryptosystem. Although larger digit sets make the computation time shorter, it requires longer preprocessing time. Therefore, the average joint Hamming weight is useful to evaluate digit sets. The Markov chains to find the average joint Hamming weight are derived automatically from the conversions. However, the number of states in these Markov chains is generally infinite. In [8], we propose an algorithm to reduce the number of states, but it is still unclear which representations the method can be applied for. In this paper, the finiteness of Markov chain with the existence of a stationary distribution is proven in a class of representation whose digit set D S be a finite set such that there exists a natural number Λ where D S ⊆ {0, ±1, ..., ±Λ} and {0,±1, ±Λ} ⊆ D S. The class covers most of the representation practically used in elliptic curve cryptography such as the representation which digit set are {0, ±1} and {0, ±1, ±3}. © 2012 Springer-Verlag.

DOI： 10.1007/978-3-642-28076-4_23

Optimal Elliptic Curve Scalar Multiplication Using Double-Base Chains 査読有り

V. Suppakitpaisarn, M. Edahiro, H. Imai

International Journal of Digital Information and Wireless Communications (IJDIWC) 2 巻 ( 1 ) 頁： 923-942 2012年

Optimal Elliptic Curve Cryptography Using Fibonacci Sequence 査読有り

V. Suppakitpaisarn, M. Edahiro, H. Imai

Proceedings of the 5th Thailand-Japan International Academic Conference (TJIA2012) 頁：未登録 2012年

Fastest Multi-Scalar Multiplication Based on Double-Base Chain 査読有り

V. Suppakitpaisarn, M. Edahiro, H. Imai

World Congress on Internet Security (WorldCIS-2012) 頁： 93-98 2012年

Fast Elliptic Curve Cryptography Using Optimal Double-Base Chains 査読有り

V. Suppakitpaisarn, M. Edahiro, H. Imai

Proceedings of the International Conference on Informatics & Applications (ICIA2012) 頁： 190-204 2012年

Efficient algorithms for extracting pareto-optimal hardware configurations in DEPS framework 査読有り

Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada

IPSJ Transactions on System LSI Design Methodology 5 巻頁： 133 - 142 2012年

記述言語：英語掲載種別：研究論文（学術雑誌）

A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice. © 2012 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.5.133

Comparison of preemption schemes for partially reconfigurable FPGAs 査読有り

Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada

IEEE Embedded Systems Letters 4 巻 ( 2 ) 頁： 45 - 48 2012年

記述言語：英語掲載種別：研究論文（学術雑誌）

Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization. © 2012 IEEE.

DOI： 10.1109/LES.2012.2193660

Toward GPU-accelerated Traffic Simulation and Its Real-Time Challenge 査読有り

Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Yuki Sugiyama

International Workshop on Real-Time and Distributed Computing in Emerging Applications (REACTION2012) 頁： 1-6 2012年

Rainbow - An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs 査読有り

Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda and Hiroaki Takada

IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig) 頁： 416-421 2011年11月

Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-power Multicore 査読有り

Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, and Hironori Kasahara

The 24th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2011) 頁： Session 1 2011年9月

Rainbow: An OS extension for hardware multitasking on dynamically partially reconfigurable FPGAs 査読有り

Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada

Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 頁： 416 - 421 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

DPR (Dynamic Partial Reconfiguration) capability found in some of modern FPGAs allows implementation of a concept of a HW (Hardware) task, which similarly to its software counterpart has its state and shares time-multiplexed resources with the other tasks. While the new technology presents many advantages for embedded systems where run-time adaptability is an additional requirement, their efficient and easily portable implementations require a control software or an OS which would manage all the complexities of the underlying technology, providing an abstracted interface for the application programmer. This paper presents a novel and robust hardware multitasking extension for a conventional OS, managing task scheduling and configurations, and providing easy-to-use API (Application Programming Interface) for the application programmer. Scheduling is priority-based and takes advantage of task caching. Moreover, the extension is based on a developed design flow and embedded hardware platform allowing efficient task preemption, which can be utilized whenever it presents any benefits to the application. © 2011 IEEE.

DOI： 10.1109/ReConFig.2011.73

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