研究者詳細 - 枝廣　正人

論文 - 枝廣　正人

分割表示 217 件中 201 - 217 件目／全件表示 >>

A Robust Seamless Communication Architecture for Next-Generation Mobile Terminals on Multi-CPU SoCs 査読有り

Hiroaki Inoue, Junji Sakai, Masato Edahiro

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 9 巻 ( 3 ) 2010年2月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：ASSOC COMPUTING MACHINERY

We propose a robust seamless communication architecture that enables legacy mobile terminal software designed for single-CPU processors to be run on multi-CPU processors without any software modifications. This architecture features two new technologies: proxy processes, which help achieve the design of its user-level system-call hooking and a robust design method, which reduces bandwidth variation by systematic parameter optimization. Our evaluations confirmed that this architecture achieves fundamental features with satisfactory performance, that we have succeeded in getting actual mobile terminal software to run on three CPUs without modifying the software, and that the robust design method reduces bandwidth variation by 21%.

DOI： 10.1145/1698772.1698777

Web of Science

Optimal Average Joint Hamming Weight and Minimal Weight Conversion of d Integers.

Vorapong Suppakitpaisarn, Masato Edahiro, Hiroshi Imai

IACR Cryptology ePrint Archive 2010 巻頁： 300 - 300 2010年

Parallelizing Fundamental Algorithms such as Sorting on Multi-core Processors for EDA Acceleration 査読有り

Masato Edahiro

PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 頁： 230 - 233 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Fundamental algorithms should be parallelized to accelerate EDA software on multi-core architecture. In this paper, we introduce scalable algorithms that have scalability on multi-cores. As an example, a sorting algorithm, called Map Sort, is presented. This algorithm uses a map from subsets of input data to intervals on data range. Experimental results show that, in comparison with quick sort on a single CPU, processing time of Map Sort is comparable on a CPU and three times faster on four CPUs.

Web of Science

FIDES: An Advanced Chip Multiprocessor Platform for Secure Next Generation Mobile Terminals 査読有り

Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 8 巻 ( 1 ) 2008年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：ASSOC COMPUTING MACHINERY

We propose a secure platform on a chip multiprocessor, FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multigrained separation mechanisms. Four new technologies support the FIDES platform: bus filter logic, XIP kernels, policy separation, and dynamic access control. With these technologies, the FIDES platform can tolerate both application-level and kernel-level bugs on an actual download subsystem. Thus, the best-suited platform to secure next generation mobile terminals is FIDES.

DOI： 10.1145/1457246.1457247

Web of Science

MULTITASKING PARALLEL METHOD FOR HIGH-END EMBEDDED APPLIANCES 査読有り

Junji Sakai, Inoue Hiroaki, Sunao Torii, Masato Edahiro

IEEE MICRO 28 巻 ( 5 ) 頁： 54 - 62 2008年9月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE COMPUTER SOC

EMBEDDED APPLIANCES SUCH AS HIGH-END CELL PHONES REQUIRE NOT ONLY HIGH PERFORMANCE BUT ALSO A PERFORMANCE GUARANTEE. THE AUTHORS DEMONSTRATE A PERFORMANCE GUARANTEE FRAMEWORK USING AN ASYMMETRIC MULTIPROCESSING APPROACH. THEY IMPLEMENTED THE PROPOSED METHOD ON A MULTICORE PROCESSOR USING LINUX. EVALUATION RESULTS SHOW THAT THE METHOD IMPROVES THE PERFORMANCE GUARANTEE WHILE MAINTAINING SOFTWARE COMPATIBILITY.

Web of Science

Processor virtualization for secure mobile terminals 査読有り

Hiroaki Inoue, Junji Sakai, Masato Edahiro

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 13 巻 ( 3 ) 2008年7月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：ASSOC COMPUTING MACHINERY

We propose a processor virtualization architecture, VIRTUS, to provide a dedicated domain for preinstalled applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies, namely, VMM asymmetrization, dynamic interdomain communication (IDC), and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor. Evaluations have shown that VMM asymmetrization results in significantly less performance degradation and LOC increase than do other VMMs. Further, dynamic IDC overhead is low enough, and virtualization-assist logic can be implemented in a sufficiently small area.

DOI： 10.1145/1367045.1367057

Web of Science

Towards scalable and secure execution platform for embedded systems 査読有り

Junji Sakai, Hiroaki Inoue, Masato Edahiro

PROCEEDINGS OF THE ASP-DAC 2007 頁： 350 - + 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Reliability of embedded systems can be enhanced by multicore and partitioning approaches. Physical partitioning based on ANW multicore achieves runtime stability of multiple applications in a system and prevents the whole system shutdown as well even when a malicious code creeps in. Combined with logical partitioning by processor virtualization and SMP technologies, the multicore architecture could realize more flexible and more scalable platform for future embedded systems.

Web of Science

VIRTUS: A new processor virtualization architecture for security-oriented next-generation mobile terminals 査読有り

Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 頁： 484 - + 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ASSOC COMPUTING MACHINERY

We propose a new processor virtualization architecture, VIRTUS, to provide a dedicated domain for pre-installed applications and virtualized domains for downloaded native applications. With it security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies: VMM asymmetrization, dynamic inter-domain communication and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor.

Web of Science

FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals 査読有り

Hiroaki, I, A Ikeno, M Kondo, J Sakai, M Edahiro

2005 INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS 頁： 178 - 183 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ASSOC COMPUTING MACHINERY

We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multi-grained separation mechanisms: coarse-grained processor-level separation of the basic-function domain from other domains for such downloaded applications, medium-grained OS-level separation, and fine-grained process-level separation within SELinux. Four new technologies, which include three enhancements to SELinux, support the FIDES platform: 1) bus filter logic for processor-level separation can be implemented as a small logic, 2) XIP kernels for memory-efficient OS-level separation can reduce memory requirements by 182%, 3) policy separation for enhanced process-level separation can apply policies 2.1 times faster at system boot-up, and 4) dynamic access control can provide secure Inter-Domain Communications (IDCs) with an overhead of only 4% for IDC system calls. We implemented SELinuxes on an ARM-based multiprocessor. Therefore, the best-suited platform to secure next generation mobile terminals is the FIDES platform, which can provide higher security as well as higher performance and lower power consumption on chip multiprocessors leading the current technology trend of microprocessors.

Web of Science

A new LSI Performance Prediction Model for interconnection analysis of future LSIs 査読有り

S Takahashi, M Edahiro, Y Hayashi

PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 頁： 51 - 56 1998年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

As the interconnection delays control the LSI performance, the LSI performance estimation at higher design level becomes more difficult. In this paper a new LSI performance model for the estimation is described, which is made up by adopting a new clack-skew model to the SUSPENS (Stanford University System Performance Simulator) model. Using the model, it is cleared that a specific block size, where the line delay overcomes the block cycle time, becomes shorter as the LSI generation proceeds.

Web of Science

AN EFFICIENT ZERO-SKEW ROUTING ALGORITHM 査読有り

M EDAHIRO

31ST DESIGN AUTOMATION CONFERENCE - PROCEEDINGS 1994 頁： 375 - 380 1994年

DCT/IDCT PROCESSOR FOR HDTV DEVELOPED WITH DSP SILICON COMPILER 査読有り

T MIYAZAKI, T NISHITANI, M EDAHIRO, ONO, I, K MITSUHASHI

JOURNAL OF VLSI SIGNAL PROCESSING 5 巻 ( 2-3 ) 頁： 151 - 158 1993年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：KLUWER ACADEMIC PUBL

This article presents a discrete cosine transform (DCI) processor for high definition television (HDTV) by using an extended version of DSP Silicon Compiler. The extension is mainly concerned with module generation functions.A matrix-vector product module composed of multiply-accumulators (MACs) is newly added to the silicon compiler. The compiler accomplishes placement of leaf-cells and routing between the cells, referring to a prototype layout for the MAC. The prototype, which consists of a Booth multiplier and a carry look ahead adder, is carefully designed to attain high operation speed. The processor developed by the silicon compiler carries out 8 x 8 DCT and its inverse transform (IDCT). In order to evaluate the newly extended functions in the compiler, the architecture employed for the processor is based on the matrix-vector product method. By using DSP Silicon Compiler and 0.8 mum triple metal CMOS technology, the DCT processor is easily implemented with error-free environment and achieves a 50MHz data rate, which meets Japanese HDTV base line signal processing. The chip is implemented on a 12.80 x 12.57 mm2 area.

Web of Science

A CLUSTERING-BASED OPTIMIZATION ALGORITHM IN ZERO-SKEW ROUTINGS 査読有り

M EDAHIRO

30TH DESIGN AUTOMATION CONFERENCE : PROCEEDINGS 1993 頁： 612 - 616 1993年

DELAY MINIMIZATION FOR ZERO-SKEW ROUTING 査読有り

M EDAHIRO

1993 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS 頁： 563 - 566 1993年

A BUCKETING ALGORITHM FOR THE ORTHOGONAL SEGMENT INTERSECTION SEARCH PROBLEM AND ITS PRACTICAL EFFICIENCY 査読有り

M EDAHIRO, K TANAKA, T HOSHINO, T ASANO

ALGORITHMICA 4 巻 ( 1 ) 頁： 61 - 76 1989年

Practical use of Bucketing Techniques in Computational Geometry 査読有り

Takao Asano, Masato Edahiro, Hiroshi Imai, Masao Iri, Kazuo Murota

Machine Intelligence and Pattern Recognition 2 巻 ( C ) 頁： 153 - 195 1985年1月

記述言語：英語掲載種別：研究論文（学術雑誌）

Techniques for using “buckets” to improve the efficiency of several computational-geometrical algorithms are described, together with examples illustrating the practical importance of the bucketing techniques. Specifically, they are applied to the problems of minimum-weight perfect matchings in the plane, two-dimensional Voronoi diagrams, point location and range search in the plane, and shortest paths in networks. © 1985, Elsevier Inc. All rights reserved.

DOI： 10.1016/B978-0-444-87806-9.50011-6

Scopus

A new pointlocation algorithm and its practical efficiency-comparison with existing algorithms

EDAHIRO M.

ACM Trans. Graphics 3 巻頁： 86 - 109 1984年

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