2026/08/04 更新

写真a

サワダ タカシ
澤田 高志
SAWADA Takashi
所属
未来社会創造機構 先進パワーエレクトロニクス研究部門 特任助教
職名
特任助教
 

論文 5

  1. Topology Optimization for Reducing Current Imbalance in Circuit with Multichip Devices Open Access

    Okubo, Y; Nomura, K; Sawada, T; Shiozaki, K

    IEICE ELECTRONICS EXPRESS   23 巻 ( 7 ) 頁: 20250743 - 20250743   2026年4月

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    記述言語:英語   出版者・発行元:一般社団法人 電子情報通信学会  

    DOI: 10.1587/elex.23.20250743

    Open Access

    Web of Science

    CiNii Research

  2. Theoretical Estimation of Current Imbalance in Multichip Power Module Using Resistance Matrix Open Access

    Nomura, K; Sawada, T; Tadano, H; Takagi, K; Shiozaki, K

    IEICE ELECTRONICS EXPRESS   22 巻 ( 22 ) 頁: 20250509 - 20250509   2025年11月

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    記述言語:英語   出版者・発行元:一般社団法人 電子情報通信学会  

    This paper describes a theoretical method to estimate the current imbalance based on the resistance matrix in a multichip power module. It is derived that the current through each device can be calculated based on the terminal voltage, the resistance matrix of the module, and the on-resistance of each device. The resistance matrix of the module can be easily obtained using parasitic extraction simulation tools. By using circuit simulations for 4-, 6-, and 12-parallel module structures, it is confirmed that the proposed method can accurately estimate the current imbalance.

    DOI: 10.1587/elex.22.20250509

    Open Access

    Web of Science

    Scopus

    CiNii Research

  3. Design of High-Power Inverter with 12 Parallel GaN Devices

    Sawada T., Takuma S., Onuma Y., Takagi K., Tadano H., Shiozaki K.

    Pcim Europe Conference Proceedings   2024-June 巻   頁: 161 - 166   2024年

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    出版者・発行元:Pcim Europe Conference Proceedings  

    Parallel placement and current imbalance are widely discussed in the application of GaN devices to high-power inverters. This paper describes a circuit layout that reduces the parasitic component of the printed circuit board by mounting GaN devices in 12 parallel in a three-phase inverter circuit. The current imbalance in the multi-pulse test is less than 20% at 600 A current output.

    DOI: 10.30420/566262019

    Scopus

  4. Continuous Operation of a Half-Bridge with Multi-Parallel GaN Power Devices for Increased Current Capability Open Access

    Sawada T., Tadano H., Shiozaki K., Isobe T.

    IEEJ Journal of Industry Applications   12 巻 ( 4 ) 頁: 695 - 700   2023年7月

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    記述言語:英語   出版者・発行元:一般社団法人 電気学会  

    GaN power devices improve the performance in power conversion circuits. Since the current rating of the GaN devices is still small, many devices must be connected in parallel to create a large-current power module. Device cooling and low stray inductance are the major challenges in designing a high-power half-bridge circuit with multi-parallel GaN devices. In order to overcome these challenges, we propose an inverter circuit structure with 12 parallel GaN devices capable of double-sided cooling and a well-balanced stray inductance. Such a system is applicable to electric vehicle design.

    DOI: 10.1541/ieejjia.22007958

    Open Access

    Scopus

    CiNii Research

  5. Continuous Operation of High-Power Half-Bridge with 12 Paralleled GaN Power Devices

    Sawada T., Tadano H., Shiozaki K., Isobe T.

    2022 International Power Electronics Conference IPEC Himeji 2022 Ecce Asia     頁: 157 - 160   2022年

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    出版者・発行元:2022 International Power Electronics Conference IPEC Himeji 2022 Ecce Asia  

    GaN power devices improve the performance in power conversion circuits. Since the current rating of the GaN devices is still small, many devices must be connected in parallel to create a high-current power module. In designing the layout of the half-bridge circuit with multi-paralleled GaN devices, the device cooling and low stray inductance are the major challenge for the high-power half-bridge circuit. We propose an inverter circuit structure with 12 parallel GaN devices focusing on the double-sided cooling and the well-balanced stray inductance for the application to electric vehicles.

    DOI: 10.23919/IPEC-Himeji2022-ECCE53331.2022.9806956

    Scopus

MISC 6

  1. Circuit Layout Design of the Parasitic Component of the Printed Circuit Board for Multi-Parallel GaN Devices

    Takashi Sawada, Shunsuke Takuma, Yoshitaka Onuma, Hiroshi Tadano, and Koji Shiozaki  

    International Symposium on Advanced Power Packaging (ISAPP)   2025年11月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究発表ペーパー・要旨(国際会議)  

  2. パッシブコモンノイズキャンセラのGaNインバータへの適用

    澤田高志, 只野博, 小笠原悟司, 井出一正, 髙木健一, 塩﨑宏司  

    電気学会産業応用部門大会   2025年8月

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    担当区分:筆頭著者   記述言語:日本語   掲載種別:研究発表ペーパー・要旨(全国大会,その他学術会議)  

  3. Common-mode Noise Canceller for GaN Traction Inverter

    Takashi Sawada, Satoshi Ogasawara, Hiroshi Tadano, and Koji Shiozaki  

    EMC Joint Workshop 2024   2024年11月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究発表ペーパー・要旨(国際会議)  

  4. The Study of Cooling Design of Power Conversion Circuit including GaN-HEMTs

    Takashi Sawada, Hiroshi Tadano and Koji Shiozaki  

    International Conference on Materials and Systems for Sustainability (ICMaSS) 2021   2021年11月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究発表ペーパー・要旨(国際会議)  

  5. GaNパワーデバイス搭載インバータ基板のバスバー冷却構造による高放熱性とゲートインダクタンス低減

    澤田高志, 只野博, 塩崎宏司, 磯部高範  

    電気学会産業応用部門大会   2021年8月

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    担当区分:筆頭著者  

  6. A Design of High-Power Inverter Circuit Including GaN Power Devices 査読有り

    Takashi Sawada, Hiroshi Tadano, Koji Shiozaki  

    2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)   2020年9月

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究発表ペーパー・要旨(国際会議)  

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