Updated on 2026/08/04

写真a

 
SAWADA Takashi
 
Organization
Institutes of Innovation for Future Society Designated Assistant Professor
Title
Designated Assistant Professor
 

Papers 5

  1. Topology optimization for reducing current imbalance in circuit with multichip devices Open Access

    Okubo Yoshinori, Nomura Katsuya, Sawada Takashi, Shiozaki Koji

    IEICE Electronics Express   Vol. 23 ( 7 ) page: 20250743 - 20250743   2026.4

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    Language:English   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>This study proposes a topology optimization approach to reduce current imbalance in a power module with multi parallel-connected devices. In this study, the conductor layout is derived by a density-based topology optimization that minimizes the coefficient of variation (CV) of the device currents under constraints for grayscale suppression, open/short-circuit prevention, and preservation of the total current. In the optimized results with 12 parallel devices, several disconnections occurred when open/short circuit prevention and the binarization term were not applied. By incorporating both methods, the optimized layout maintained proper connection and reduced current imbalance.</p>

    DOI: 10.1587/elex.23.20250743

    Open Access

    Web of Science

    CiNii Research

  2. Theoretical estimation of current imbalance in multichip power module using resistance matrix Open Access

    Nomura Katsuya, Sawada Takashi, Tadano Hiroshi, Takagi Kenichi, Shiozaki Koji

    IEICE Electronics Express   Vol. 22 ( 22 ) page: 20250509 - 20250509   2025.11

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    Language:English   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>This paper describes a theoretical method to estimate the current imbalance based on the resistance matrix in a multichip power module. It is derived that the current through each device can be calculated based on the terminal voltage, the resistance matrix of the module, and the on-resistance of each device. The resistance matrix of the module can be easily obtained using parasitic extraction simulation tools. By using circuit simulations for 4-, 6-, and 12-parallel module structures, it is confirmed that the proposed method can accurately estimate the current imbalance.</p>

    DOI: 10.1587/elex.22.20250509

    Open Access

    Web of Science

    Scopus

    CiNii Research

  3. Design of High-Power Inverter with 12 Parallel GaN Devices

    Sawada T., Takuma S., Onuma Y., Takagi K., Tadano H., Shiozaki K.

    Pcim Europe Conference Proceedings   Vol. 2024-June   page: 161 - 166   2024

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    Publisher:Pcim Europe Conference Proceedings  

    Parallel placement and current imbalance are widely discussed in the application of GaN devices to high-power inverters. This paper describes a circuit layout that reduces the parasitic component of the printed circuit board by mounting GaN devices in 12 parallel in a three-phase inverter circuit. The current imbalance in the multi-pulse test is less than 20% at 600 A current output.

    DOI: 10.30420/566262019

    Scopus

  4. Continuous Operation of a Half-Bridge with Multi-Parallel GaN Power Devices for Increased Current Capability Open Access

    Sawada Takashi, Tadano Hiroshi, Shiozaki Koji, Isobe Takanori

    IEEJ Journal of Industry Applications   Vol. 12 ( 4 ) page: 695 - 700   2023.7

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    Language:English   Publisher:The Institute of Electrical Engineers of Japan  

    <p>GaN power devices improve the performance in power conversion circuits. Since the current rating of the GaN devices is still small, many devices must be connected in parallel to create a large-current power module. Device cooling and low stray inductance are the major challenges in designing a high-power half-bridge circuit with multi-parallel GaN devices. In order to overcome these challenges, we propose an inverter circuit structure with 12 parallel GaN devices capable of double-sided cooling and a well-balanced stray inductance. Such a system is applicable to electric vehicle design.</p>

    DOI: 10.1541/ieejjia.22007958

    Open Access

    Scopus

    CiNii Research

  5. Continuous Operation of High-Power Half-Bridge with 12 Paralleled GaN Power Devices

    Sawada T., Tadano H., Shiozaki K., Isobe T.

    2022 International Power Electronics Conference IPEC Himeji 2022 Ecce Asia     page: 157 - 160   2022

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    Publisher:2022 International Power Electronics Conference IPEC Himeji 2022 Ecce Asia  

    GaN power devices improve the performance in power conversion circuits. Since the current rating of the GaN devices is still small, many devices must be connected in parallel to create a high-current power module. In designing the layout of the half-bridge circuit with multi-paralleled GaN devices, the device cooling and low stray inductance are the major challenge for the high-power half-bridge circuit. We propose an inverter circuit structure with 12 parallel GaN devices focusing on the double-sided cooling and the well-balanced stray inductance for the application to electric vehicles.

    DOI: 10.23919/IPEC-Himeji2022-ECCE53331.2022.9806956

    Scopus

MISC 6

  1. Circuit Layout Design of the Parasitic Component of the Printed Circuit Board for Multi-Parallel GaN Devices

    Takashi Sawada, Shunsuke Takuma, Yoshitaka Onuma, Hiroshi Tadano, and Koji Shiozaki

    International Symposium on Advanced Power Packaging (ISAPP)     2025.11

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    Authorship:Lead author   Language:English   Publishing type:Research paper, summary (international conference)  

  2. パッシブコモンノイズキャンセラのGaNインバータへの適用

    澤田高志, 只野博, 小笠原悟司, 井出一正, 髙木健一, 塩﨑宏司

    電気学会産業応用部門大会     2025.8

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    Authorship:Lead author   Language:Japanese   Publishing type:Research paper, summary (national, other academic conference)  

  3. Common-mode Noise Canceller for GaN Traction Inverter

    Takashi Sawada, Satoshi Ogasawara, Hiroshi Tadano, and Koji Shiozaki

    EMC Joint Workshop 2024     2024.11

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    Authorship:Lead author   Language:English   Publishing type:Research paper, summary (international conference)  

  4. The Study of Cooling Design of Power Conversion Circuit including GaN-HEMTs

    Takashi Sawada, Hiroshi Tadano and Koji Shiozaki

    International Conference on Materials and Systems for Sustainability (ICMaSS) 2021     2021.11

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    Authorship:Lead author   Language:English   Publishing type:Research paper, summary (international conference)  

  5. GaNパワーデバイス搭載インバータ基板のバスバー冷却構造による高放熱性とゲートインダクタンス低減

    澤田高志, 只野博, 塩崎宏司, 磯部高範

    電気学会産業応用部門大会     2021.8

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    Authorship:Lead author  

  6. A Design of High-Power Inverter Circuit Including GaN Power Devices Reviewed

    Takashi Sawada, Hiroshi Tadano, Koji Shiozaki

    2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe)     2020.9

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    Authorship:Lead author   Language:English   Publishing type:Research paper, summary (international conference)  

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