Updated on 2023/09/27
Doctor of engineering （ 2000.3 Kyushu University ）
Energy efficient computing, Low power design, Optical computing
Informatics / Computer system / Energy efficient computing
Informatics / Computer system / Energy Efficient Computing
Nagoya University Graduate School of Informatics Department of Computing and Software Systems 2 Professor
2018.10
Kyoto University Graduate School of Informatics Department of Communications and Computer Engineering Associate professor
2011.4 - 2018.9
Kyushu University System LSI Research Center Associate professor
2007.4 - 2011.3
Kyushu University System LSI Research Center Associate Professor
2005.8 - 2007.3
Fujitsu Laboratories of America Researcher
2003.4 - 2005.7
The University of Tokyo Assistant
2000.4 - 2003.4
Japan Society for Promotion of Science
1997.4 - 2000.3
Nagoya University Graduate School of Informatics Professor
2018.10
Country：Japan
Kyoto University Graduate School of Informatics Associate professor
2011.4 - 2018.9
Country：Japan
Kyushu University
1995.4 - 2000.3
Country： Japan
Kyushu University Faculty of Engineering Department of Computer Science and Communication Engineering
1991.4 - 1995.3
Country： Japan
電子情報通信学会
2008.5
情報処理学会
1994
IEEE Computer Society
ACM
科学技術分野の文部科学大臣表彰 若手科学者賞
2009.4 文部科学省 マイクロプロセッサの省電力化に関する研究
石原 亨
丸文研究奨励賞
2007.3 丸文財団 ソフトウェア制御によるシステムLSIの低消費エネルギー化と微細化への対応
石原 亨
長尾真記念特別賞
2010.5 情報処理学会 コンピュータシステムの省エネルギー化に関する研究
石原 亨
論文賞
2013.5 電子情報通信学会 Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications
Lovic Eric Gauthier, 石原 亨
Best Paper Award
2021.6 IEICE Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, and Masaya Notomi
論文賞
2018.6 電子情報通信学会 Analytical Stability Modeling for CMOS Latches in Low Voltage Operation
鎌苅竜也, 塩見準,石原亨,小野寺秀俊
情報処理学会創立40周年記念論文賞
2000.3 情報処理学会 DRAM／ロジック混載LSI向け高性能／低消費電力キャッシュ・アーキテクチャ
井上弘士，石原亨，甲斐康司，村上和彰
ISLPED 1st Most Cited Paper Award
2015.9 IEEE/ACM International Symposium on Low Power Electronics and Design Voltage scheduling problem for dynamically variable voltage processors
Tohru Ishihara, Hiroto Yasuura
IEEE SOCC Best Paper Award
2016.9 IEEE International System-on-Chip Conference Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
Outstanding Paper Award
2010.10 Workshop on Synthesis And System Integration of Mixed Information technologies Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications
Lovic Gauthier, Tohru Ishihara, Hideki, Hiroyuki,Hiroaki Takada
Outstanding Paper Award
2021.3 Workshop on Synthesis And System Integration of Mixed Information technologies An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier
L. Hou, Y. Masuda, T. Ishihara
情報処理学会システムLSI設計技術研究会優秀論文賞
2016.9 情報処置学会システムLSI設計技術研究会
情報処理学会システムLSI設計技術研究会優秀論文賞
2013.8 情報処置学会システムLSI設計技術研究会
情報処理学会システムLSI設計技術研究会優秀論文賞
2002.7 情報処置学会システムLSI設計技術研究会
LSI IPデザイン・アワード MeP賞
2008.4 LSI IPデザイン・アワード運営委員会
LSI IPデザイン・アワード IP優秀賞
1999.5 LSI IPデザイン・アワード運営委員会
情報処理学会九州支部奨励賞
1998.5 情報処理学会九州支部
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing Reviewed
L. Hou, Y. Masuda, and T. Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E106-A ( 3 ) page： 532 - 541 2023.3
DVFS virtualization for energy minimization of mixed-criticality dual-OS platforms Reviewed
T. Komori, Y. Masuda, and T. Ishihara
Proc. 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) page： 128 - 137 2022.8
Power-Aware Pruning for Ultrafast, Energy-Efficient, and Accurate Optical Neural Network Design Reviewed
N. Hattori, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi
Proc. Design Automation Conference (DAC) 2022.7
Optoelectronic Implementation of Compact and Power-Efficient Recurrent Neural Networks Reviewed
N. Ichikawa, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) page： 390 - 393 2022.6
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing Reviewed
T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E105-A ( 3 ) page： 497 - 508 2022.3
Identification of redundant flip-flops using fault injection for low-power approximate computing circuits Reviewed
Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. Vol.E107-A ( No.3 ) 2024.3
Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform Reviewed
Takumi Komori, Yutaka Masuda, Tohru Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. Vol.E107-A ( No.1 ) 2024.1
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design Reviewed
T. -F. Chen, Y. Masuda, T. Ishihara
Proc. 36th IEEE International System-On-Chip Conference (SOCC) page： 34 - 39 2023.9
Feedback-tuned fuzzing for accelerating quality verification of approximate computing design Reviewed
Yusei Honda, Yutaka Masuda, Tohru Ishihara
Proc. 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), page： 1 - 3 2023.7
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits Reviewed
Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
Proc. IEEE Design, Automation and Test in Europe Conference (DATE) page： 1 - 2 2023.4
Dynamic Verification Framework of Approximate Computing Circuits using Quality-aware Coverage-based Grey-box Fuzzing Reviewed
Y. Masuda, Y. Honda, and T. Ishihara
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E106-A ( 3 ) page： 514 - 522 2023.3
Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits Reviewed
J. Lu, Y. Masuda, T. Ishihara
Proc. 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) page： 20 - 25 2022.10
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits Reviewed
Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera
IEEE 35th International System-on-Chip Conference (SOCC) page： 1 - 6 2022.9
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling Reviewed
Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E105-A ( 3 ) page： 509 - 517 2022.3
Energy efficient OEO conversion and its applications to photonic integrated systems Reviewed International journal
Shinya A., Nozaki K., Kita S., Ishihara T., Matsuo S., Notomi M.
Proc. Optical Fiber Communications Conference and Exhibition (OFC) 2022.3
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers Reviewed
L. Hou, Y. Masuda, and T. Ishihara
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) page： 568 - 573 2022.1
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits Reviewed
R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E104-A ( 11 ) page： 1546 - 1554 2021.11
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation Reviewed
N. Hattori, J. Shiomi, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E104-A ( 11 ) page： 1477 - 1487 2021.11
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing Reviewed
K. Yoshisue, Y. Masuda, and T. Ishihara
Proc. IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) 2021.6
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing Reviewed
T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara
IEEE International Symposium on Quality Electronic Design (ISQED) page： 300 - 306 2021.4
An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier Reviewed
Lingxiao Hou,Yutaka Masuda,Tohru Ishihara
Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2021.3
Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing Reviewed
Naoki Hattori,Yutaka Masuda,Tohru Ishihara,Jun Shiomi,Akihiko Shinya,Masaya Notomi
Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics Vol. 11703 page： 1E1 - 1E17 2021.3
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design Reviewed
Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto
Proc. IEEE Design, Automation and Test in Europe Conference (DATE) 2021.2
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. Reviewed
Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi
Proc. International Conference on Rebooting Computing (ICRC) page： 95 - 101 2020.12
Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling Reviewed
Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto
Proc. International Workshop on Logic and Synthesis (IWLS) page： 136 - 142 2020.7
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. Reviewed
Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) page： 488 - 493 2020.7
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. Reviewed International coauthorship
Khyati Kiyawat,Yutaka Masuda,Jun Shiomi,Tohru Ishihara
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) page： 415 - 421 2020.7
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing Reviewed
Hongjie Xu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E102-A ( 12 ) page： 1741 - 1750 2019.12
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits Reviewed
Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E102-A ( 12 ) page： 1751 - 1759 2019.12
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator Reviewed International journal
Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi
Photonics-Optics Technology Oriented Networking, Information, and Computing Systems (PHOTONICS) at The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC19) 2019.11
A Design Method of a Cell-Based Amplifier for Body Bias Generation Reviewed
Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
IEICE Transactions on IEICE Transactions on Electronics Vol. E102-C ( 7 ) page： 565 - 572 2019.7
BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing Reviewed International journal
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
Proc. the 24th Asia and South Pacific Design Automation Conference (ASP-DAC) page： 203 - 209 2019.1
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
Proc. IEEE International Conference on Rebooting Computing (ICRC) page： 62 - 67 2018.11
Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics Reviewed International journal
Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
Proc. IEEE International Conference on Rebooting Computing (ICRC) page： 43 - 50 2018.11
Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization Reviewed
Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera
Proc.the 31st IEEE International System-on-Chip Conference (SOCC) 2018.9
Independent N-well and P-well Biasing for Minimum Leakage Energy Operation Reviewed
Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera
Proc. the International Symposium on On-Line Testing and Robust System Design (IOLTS) page： 177 - 182 2018.7
Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure Reviewed International journal
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. the 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) page： 237 - 242 2018.7
Minimum Energy Point Tracking with All-Digital On-Chip Sensors
Jun Shiomi, Shu Hokimoto, Tohru Ishihara, and Hidetoshi Onodera
ASP Journal of Low Power Electronics Vol. 14 ( 2 ) 2018.6
An Integrated Nanophotonic Parallel Adder Reviewed
Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi
ACM Journal on Emerging Technologies in Computing (JETC) 2018.6
An optical parallel multiplier using nanophotonic analog adders and optoelectronic analog-to-digital converters Reviewed
Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
Proceedings of Conference on Lasers and Electro-Optics (CLEO) Vol. 2018 2018.5
A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator Reviewed
Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera
Japanese Journal of Applied Physics Vol. 57 ( 4S ) page： 04FF09-1 - 04FF09-6 2018.3
A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits Reviewed
Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 56 - 61 2018.3
Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) page： 45 - 50 2018.3
Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation Reviewed
Yuta Nagaoka, Tohru Ishihara, Hidetoshi Onodera
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 290 - 295 2018.3
An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters Reviewed
Yuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 100 - 105 2018.3
All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors Reviewed
Shu Hokimoto, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. Annual IEEE International Conference on Microelectronic Test Structures (ICMTS) page： 128 - 133 2018.3
A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies Reviewed
Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 320 - 325 2018.3
On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation Reviewed
Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera
Proc. Annual IEEE International Conference on Microelectronic Test Structures (ICMTS) page： 111 - 116 2018.3
A minimum energy point tracking algorithm based on dynamic voltage scaling and adaptive body biasing Reviewed
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E100A ( 12 ) page： 2776 - 2784 2017.12
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E100A ( 12 ) page： 2764 - 2775 2017.12
Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Elsevier: Integration, the VLSI Journal ( 有り ) 2017.7
On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator Reviewed
Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera
2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) page： 1 - 4 2017.4
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Reviewed
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES Vol. E99A ( 12 ) page： 2463 - 2472 2016.12
A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) page： 36 - 41 2016.10
Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications Reviewed
Kei Yoshizawa, Tohru Ishihara, Hidetoshi Onodera
Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) page： 329 - 334 2016.10
An Integrated Optical Parallel Adder as a First Step Towards Light Speed Data Processing Reviewed International journal
Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi
2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) page： 123 - 124 2016.10
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
PROCEEDINGS OF 2016 26TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) page： 44 - 49 2016.9
Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing Reviewed
Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
Proc. IEEE International System-on-Chip Conference (SOCC) page： 1 - 6 2016.9
Guidelines for effective and simplified dynamic supply and threshold voltage scaling Reviewed
Toshinori Takeshita, Tohru Ishihara, Hidetoshi Onodera
Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 2016.4
Variability- and correlation-aware logical effort for near-threshold circuit design Invited Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. the17th International Symposium on Quality Electronic Design (ISQED) page： 18 - 23 2016.3
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. Reviewed
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
21st Asia and South Pacific Design Automation Conference (ASP-DAC) page： 691 - 696 2016.1
A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol. 50 ( 11 ) page： 2475 - 2490 2015.11
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES Vol. E98A ( 7 ) page： 1455 - 1466 2015.7
An impact of process variation on supply voltage dependence of logic path delay variation. Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Proc. VLSI Design, Automation and Test (VLSI-DAT) page： 1 - 4 2015.4
A Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation using Cell-Based Structure Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) 2015.3
An energy-efficient on-chip memory structure for variability-aware near-threshold operation. Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. the 16th International Symposium on Quality Electronic Design (ISQED) page： 23 - 28 2015.3
Energy reduction by built-in body biasing with single supply voltage operation. Reviewed
Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
Proc. the 16th International Symposium on Quality Electronic Design (ISQED) page： 181 - 185 2015.3
Layout generator with flexible grid assignment for area efficient standard cell Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
IPSJ Transactions on System LSI Design Methodology Vol. 8 page： 131 - 135 2015.2
Microarchitectural-level statistical timing models for near-threshold circuit design. Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. the 20th Asia and South Pacific Design Automation Conference (ASP-DAC) page： 87 - 93 2015.1
An Integrated Framework for Energy Optimization of Embedded Real-Time Applications Reviewed International journal
Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES Vol. E97A ( 12 ) page： 2477 - 2487 2014.12
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-chip Process and Temperature Monitoring Reviewed International journal
A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
Proc. IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) page： 45 - 48 2014.11
Variation-aware Flip-Flop energy optimization for ultra low voltage operation. Reviewed
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Proc. the 27th IEEE International System-on-Chip Conference (SOCC) page： 17 - 22 2014.10
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Proc. the 27th IEEE International System-on-Chip Conference (SOCC) page： 42 - 47 2014.9
Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) page： 28 - 32 2014.3
DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems Reviewed
K. Lee, T. Ishihara
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences Vol. 96-A ( 12 ) page： 2660-2667 2013.12
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences Vol. 96-A ( 12 ) page： 2499-2507 2013.12
Energy-efficient Dynamic Voltage and Frequency Scaling by P/N-performance Self-adjustment using Adaptive Body Bias, Reviewed
A.K.M. Mahfuzul Islam, Norihiro Kamae, Tohru Ishihara, Hidetoshi Onodera
Proc. the Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2013.10
A standard cell optimization method for near-threshold voltage operations Reviewed
Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) Vol. 7606 page： 32 - 41 2013.9
DLIC: Decoded loop instructions caching for energy-aware embedded processors Reviewed International coauthorship International journal
Ji Gu, Hui Guo, Tohru Ishihara
Transactions on Embedded Computing Systems Vol. 13 ( 1 ) page： 6 - 26 2013.8
An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) 2013.3
Analysis and comparison of XOR cell structures for low voltage circuit design. Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Proc. International Symposium on Quality Electronic Design (ISQED) page： 703 - 708 2013.3
A flexible structure of standard cell and its optimization method for near-threshold voltage operation Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
Proc. the 30th International IEEE Conference on Computer Design (ICCD) page： 235 - 240 2012.10
I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays Reviewed
Kyungsoo Lee, Tohru Ishihara
Proc. IEEE 10th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia) page： 48 - 55 2012.10
Loop instruction caching for energy-efficient embedded multitasking processors Reviewed
Ji Gu, Tohru Ishihara, Kyungsoo Lee
Proc. IEEE 10th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia) page： 97 - 106 2012.10
A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems Reviewed
Ji Gu, Tohru Ishihara
Proc. the 1st International Conference on Smart Grids and Green IT Systems (SMARTGREENS) page： 197 - 202 2012.4
A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems Reviewed
Kyungsoo Lee, Tohru Ishihara
Proc. the 1st International Conference on Smart Grids and Green IT Systems (SMARTGREENS) page： 175 - 182 2012.4
Processor energy characterization for compiler-assisted software energy reduction Reviewed
L. Gauthier; T. Ishihara
Journal of Electrical and Computer Engineering - 英語 2012.1
Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications Reviewed
Lovic Gauthier, Tohru Ishihara
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences Vol. 94-A ( 12 ) page： 2597-2608 2011.12
ＲＴＯＳのハードウェア化によるソフトウェアベースＴＣＰ／ＩＰ処理の高速化と低消費電力化 Reviewed
丸山修孝;石原亨;安浦寛人
電子情報通信学会論文誌 A Vol. J94-A ( 9 ) page： 692 - 701 2011.9
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits Reviewed
Takumi Okuhira, Tohru Ishihara
Proc. the 21st International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) page： 237 - 246 2011.9
An integrated optimization framework for reducing the energy consumption of embedded real-time applications Reviewed
Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada
Proc. International Symposium on Low Power Electronics and Design (ISLPED) page： 271 - 276 2011.8
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies Reviewed
Maziar Goudarzi, Tohru Ishihara, Hamid Noori
Transactions on High-Performance Embedded Architectures and Compilers Vol. 3 page： 275-299 2011.3
Developing an integrated verification and debug methodology Reviewed
Akitoshi Matsuda, Tohru Ishihara
Proc. Design, Automation and Test in Europe (DATE) page： 503 - 504 2011.3
A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems Reviewed
Tohru ISHIHARA
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences Vol. 93-A ( 12 ) page： 2533-2541 2010.12
SRAM leakage reduction by row/column redundancy under random within-die delay variation Reviewed
M. Goudarzi; T. Ishihara
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 18 ( 12 ) page： 1660 - 1671 2010.12
Compiler assisted energy reduction techniques for embedded multimedia processors Invited Reviewed
Lovic Gauthier, Tohru Ishihara
Proc. the 2nd APSIPA Annual Summit and Conference page： 27 - 36 2010.12
Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications Reviewed
Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 7 - 12 2010.10
Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems Reviewed
Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada
Proc. the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) page： 157 - 166 2010.10
Code and data placement for embedded processors with scratchpad and cache memories Reviewed
Y. Ishitobi; T. Ishihara; H. Yasuura
Journal of Signal Processing Systems Vol. 60 ( 2 ) page： 211 - 224 2010.8
An RTOS in hardware for energy efficient software-based TCP/IP processing Reviewed
Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura
Proc. IEEE 8th Symposium on Application Specific Processors (SASP) page： 58 - 63 2010.6
An implementation of energy efficient multi-performance processor for real-time applications Reviewed
Chengjie Zang, Tohru Ishihara
Proc. the 2010 International Conference on Green Circuits and Systems page： 211 - 216 2010.6
Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories Reviewed
Lovic Gauthier, Tohru Ishihara
Proc. the 7th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) page： 116 - 125 2009.10
Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion Reviewed
Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
IPSJ Transactions on System LSI Design Methodology Vol. 2 page： 189-199 2009.2
An Optimization Technique for Low-Energy Embedded Memory Systems Reviewed
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
IPSJ Transactions on System LSI Design Methodology Vol. 2 page： 239-249 2009.2
Way-Scaling to Reduce Power of Cache with Delay Variation Reviewed
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences Vol. 91-A ( 12 ) page： 3576-3584 2008.12
A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation Reviewed
M. Goudarzi; T. Ishihara; H. Yasuura
Microelectronics Journal Vol. 39 ( 12 ) page： 1797 - 1808 2008.12
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption Reviewed
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
Proc. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) page： 62 - 71 2008.9
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation Reviewed
Maziar Goudarzi, Tohru Ishihara
Proc. International Symposium on Low Power Electronics and Design (ISLPED) page： 93 - 98 2008.8
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications Reviewed
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato
Proc. IEEE Symposium on Application Specific Processors (SASP) page： 83 - 88 2008.6
Simultaneous optimization of memory configuration and code allocation for low power embedded systems Reviewed
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
Proc. the 18th ACM Great Lakes Symposium on VLSI page： 403 - 406 2008.5
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells Reviewed
Maziar Goudarzi, Tohru Ishihara
Proc. the 18th ACM Great Lakes Symposium on VLSI page： 383 - 386 2008.5
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems Reviewed
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
IEICE Transactions on Electronics Vol. 91-C ( 4 ) page： 410-417 2008.4
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways Reviewed
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) page： 447 - 450 2008.4
Value-dependence of SRAM leakage in deca-nanometer technologies Reviewed
Maziar Goudarzi, Tohru Ishihara
IEICE Electronic Express Vol. 5 page： 23-28 2008.1
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation Reviewed
Maziar Goudarzi, Tohru Ishihara, Mamid Noori
Proc. High Performance Embedded Architectures and Compilers (HiPEAC) page： 224 - 239 2008.1
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems Reviewed
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
IEICE Transactions on Electronics Vol. 90-C ( 10 ) page： 1983-1991 2007.10
A Hybrid Memory Architecture for Low Power Embedded System Design Reviewed
Tadayuki Matsumura, Yuriko Ishitobi, Tohru Ishihara, Maziar Goudarzi, Hiroto Yasuura
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 56 - 62 2007.10
Code placement for reducing the energy consumption of embedded processors with scratchpad and cache memories Reviewed
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
Proc. IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia) page： 13 - 18 2007.10
Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems Reviewed
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
Proc. Design, Automation and Test in Europe (DATE) page： 1490 - 1495 2007.4
A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation Reviewed
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) page： 878 - 883 2007.1
An Energy Characterization Framework for Software-Based Embedded Systems Reviewed
Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah
Proc. IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia) page： 59 - 64 2006.10
Exploiting Narrow Bitwidth Operations for Low Power Embedded Software Design Reviewed
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 51 - 56 2006.4
A simulation-based soft error estimation methodology for computer systems Reviewed
Makoto Sugihara, Tohru Ishihara, Koji Hashimoto, Masanori Muroyama
Proc. IEEE International Symposium on Quality Electronics Design (ISQED) page： 196 - 203 2006.3
A cache-defect-aware code placement algorithm for improving the performance of processors Reviewed International coauthorship
Tohru Ishihara, Farzan Fallah
Proc. International Conference on Computer Aided Design (ICCAD) page： 995 - 1001 2005.11
A non-uniform cache architecture for low power system design Reviewed International coauthorship
Tohru Ishihara, Farzan Fallah
Proc. International Symposium on Low Power Electronics and Design (ISLPED) page： 363 - 368 2005.8
A Code Placement Technique for Improving the Performance of Processors with Defective Caches Reviewed
Tohru Ishihara, Farzan Fallah
Proc. International Workshop on Logic and Synthesis (IWLS) page： 210 - 214 2005.6
A way memoization technique for reducing power consumption of caches in application specific integrated processors Reviewed
Tohru Ishihara, Farzan Fallah
Proc. Design, Automation and Test in Europe (DATE) page： 358 - 363 2005.3
Comparative Study On Verilog-Based And C-Based Hardware Design Education Reviewed
Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada
Proc. International Conference on Microelectronics Systems Education (MSE) page： 41 - 42 2003.6
オンチップメモリの高速化と低スタンバイリークを実現する閾値電圧の静的スケジューリング手法 Reviewed
石原亨, 浅田邦博
情報処理学会論文誌 Vol. 44 ( 5 ) page： 1284-1291 2003.5
A Voltage Scheduling Technique for Fault-Tolerant Real-Time Microprocessor Systems Reviewed
Tohru Ishihara
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 137 - 143 2003.4
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories Reviewed
Tohru Ishihara, Kunihiro Asada
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) page： 282 - 287 2002.1
A power minimization technique for arithmetic circuits by cell selection Reviewed
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) page： 268 - 273 2002.1
A System Level Optimization Technique for Application Specific Low Power Memories Reviewed
Tohru ISHIHARA, Kunihiro ASADA
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences Vol. E84-A ( 11 ) page： 2755-2761 2001.11
入力信号パターンを考慮した低電力算術演算回路の設計手法 Reviewed
室山真徳，石原亨，兵頭章彦，安浦寛人
情報処理学会論文誌 Vol. 42 ( 4 ) page： 1007-1015 2001.4
DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ Reviewed
井上弘士, 石原亨，甲斐康司，村上和彰
情報処理学会論文誌 Vol. 42 ( 3 ) page： 419-431 2001.3
Software energy reduction techniques for variable-voltage processors Reviewed
T. Okuma; H. Yasuura; T. Ishihara
IEEE Design and Test of Computers Vol. 18 ( 2 ) page： 31 - 41 2001.3
A system level memory power optimization technique using multiple supply and threshold voltages Reviewed
Tohru Ishihara, Kunihiro Asada
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) page： 456 - 461 2001.1
可変電源電圧プロセッサに対するリアルタイムタスクスケジューリング手法 Reviewed
大隈孝憲, 石原亨, 安浦寛人
電子情報通信学会論文誌 Vol. J83-C ( 6 ) page： 454-462 2000.6
Flexible system LSI for embedded systems and its optimization techniques Reviewed
A. Inoue; T. Ishihara; H. Yasuura
Design Automation for Embedded Systems Vol. 5 ( 2 ) page： 179 - 205 2000.6
A power reduction technique with object code merging for application specific embedded processors Reviewed
Tohru Ishihara, Hiroto Yasuura
Proc. Design, Automation and Test in Europe (DATE) page： 617 - 623 2000.3
System LSI design methods for low power LSIs Invited Reviewed
H. Yasuura; T. Ishihara
IEICE Transactions on Electronics Vol. E83-C ( 2 ) page： 143 - 152 2000.2
A high-performance and low-power cache architecture with speculative way-selection Reviewed
K. Indue; T. Ishihara; K. Kai; K. Murakami
IEICE Transactions on Electronics Vol. E83-C ( 2 ) page： 186 - 193 2000.2
A memory power optimization technique for application specific embedded systems Reviewed
T. Ishihara; H. Yasuura
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E82-A ( 11 ) page： 2366 - 2374 1999.11
Real-time task scheduling for a variable voltage processor Reviewed
Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
Proc. the 12th International Symposium on System Synthesis (ISSS) page： 24 - 29 1999.11
Way-predicting set-associative cache for high performance and low energy consumption Reviewed
Koji Inoue, Tohru Ishihara, Kazuaki Murakami
Proc. International Symposium on Low Power Electronics and Design (ISLPED) page： 273 - 275 1999.8
Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches Reviewed
H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E81-A ( 12 ) page： 2621 - 2629 1998.12
Programmable power management architecture for power reduction Reviewed
T. Ishihara; H. Yasuura
IEICE Transactions on Electronics Vol. E81-C ( 9 ) page： 1473 - 1479 1998.9
Voltage scheduling problem for dynamically variable voltage processors Reviewed
Tohru Ishihara, Hiroto Yasuura
Proc. International Symposium on Low Power Electronics and Design (ISLPED) page： 197 - 202 1998.8
Instruction Scheduling for Power Reduction in Processor-Based System Design Reviewed
Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
Proc. Design, Automation and Test in Europe (DATE) page： 855 - 860 1998.2
Power-Pro: Programmable Power Management Architecture Reviewed
Tohru Ishihara, Hiroto Yasuura
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC) page： 321 - 322 1998.2
Optimization of Supply Voltage Assignment for Power Reduction on Processor Based Systems Reviewed
Tohru Ishihara, Hiroto Yasuura
Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) page： 170 - 177 1997.12
Experimental analysis of power estimation models of CMOS VLSI circuits Reviewed
Tohru Ishihara, Hiroto Yasuura
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E80-A ( 3 ) page： 480 - 486 1997.3
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits Reviewed
Tohru Ishihara, Hiroto Yasuura
Proc. International Symposium on Low Power Electronics and Design (ISLPED) page： 117 - 120 1996.8
Multi-Processor System-on-Chip 1
Jun Shiomi, Tohru Ishihara（ Role： Joint author , Chapter 10: Minimum Energy Computing via Supply and Threshold Voltage Scaling (pp. 227-254)）
Wiley – ISTE 2021.3
CMOS VLSI Design - A Circuits and Systems Perspective 4th ed.
Tohru Ishihara（ Role： Joint translator , Chapter 5 Power）
2014.1
Essential Issues in SOC Design: Designing Complex Systems-on-Chip
H. Yasuura, T. Ishihara, M. Muroyama（ Role： Contributor , Chapter 6: Energy Management Techniques for SOC Design）
Springer 2006.10
近似コンピューティング回路の設計最適化に向けた計算重要度評価技術
陸佳萱, 増田豊, 石原亨
情報処理学会研究報告(Web) Vol. 2021 ( SLDM-195 ) 2021
近似コンピューティング回路の品質検証を高速化するファジングテスト法
本多佑成, 増田豊, 石原亨
情報処理学会研究報告(Web) Vol. 2021 ( SLDM-195 ) 2021
ファジングと高位合成を用いた近似コンピューティング回路のタイミング検証手法
熊谷僚太, 増田豊, 石原亨
情報処理学会研究報告(Web) Vol. 2021 ( SLDM-195 ) 2021
Approximate Minimum Energy Point Tracking Which Guarantees Real-Time Responses of Tasks
小森工, 増田豊, 塩見準, 石原亨
回路とシステムワークショップ論文集(CD-ROM) Vol. 34th 2021
服部 直樹, 増田 豊, 石原 亨, 塩見 準, 新家 昭彦, 納富 雅也
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 119 ( 443 ) page： 251 - 256 2020.3
富山 葉月, 増田 豊, 石原 亨
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 119 ( 443 ) page： 113 - 118 2020.3
Towards the realization of low-latency and high-efficiency photoelectronic accelerators
北翔太, 北翔太, 野崎謙悟, 野崎謙悟, 小野真証, 小野真証, 高田健太, 高田健太, 新家昭彦, 新家昭彦, CONG G., 山本宗継, 前神有里子, 大野守史, 山田浩治, 川上哲志, 井上弘士, 石原亨, 納富雅也, 納富雅也
応用物理学会春季学術講演会講演予稿集(CD-ROM) Vol. 67th page： 1200 - 1200 2020
集積ナノフォトニクスに基づく近似並列乗算器を用いた低レイテンシ光ニューラルネットワーク—VLSI設計技術 ; デザインガイア2019 : VLSI設計の新しい大地
塩見 準, 石原 亨, 小野寺 秀俊, 新家 昭彦, 納富 雅也
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 119 ( 282 ) page： 127 - 132 2019.11
A Process-Scheduler-Based Approach to Minimum Energy Point Tracking
Shengyu Liu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
DA Symposium 2019 (poster) 2019.8
福田 展和, 塩見 準, 石原 亨, 小野寺 秀俊
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 118 ( 29 ) page： 25 - 30 2018.5
光パスゲート論理に基づく超低遅延光回路—特集 集積ナノフォトニクス研究の最前線
新家 昭彦, 石原 亨, 井上 弘士, 野崎 謙悟, 納富 雅也
NTT技術ジャーナル / 日本電信電話株式会社 編 Vol. 30 ( 5 ) page： 28 - 31 2018.5
光パスゲート論理に基づく光波長多重並列加算器(2)~熱光学スイッチによる動作実証~
新家昭彦, 新家昭彦, 石原亨, 野崎謙悟, 野崎謙悟, 北翔太, 北翔太, 井上弘士, CONG Guangwei, 山田浩治, 納富雅也, 納富雅也
応用物理学会秋季学術講演会講演予稿集(CD-ROM) Vol. 79th 2018
<高校生のページ>人に寄り添う安全安心なコンピュータの実現を目指して
石原 亨, 小野寺 秀俊
Cue : 京都大学電気関係教室技術情報誌 Vol. 38 page： 58 - 62 2017.9
IoT向け超省エネルギープロセッサのための完全ディジタル型メモリ
塩見 準, 石原 亨, 小野寺 秀俊
LSIとシステムのワークショップ2017 (poster) 2017.5
ロジック部およびメモリ部の独立電圧制御によるプロセッサの消費エネルギー最小化 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2017)
塩見 準, 石原 亨, 小野寺 秀俊
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 116 ( 511 ) page： 87 - 92 2017.3
A Voltage-Scalable Fully Digital On-Chip Memory for Ultra-Low-Power IoT Processors
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
University Booth at Design, Automation and Test in Europe (DATE) 2017 (poster) 2017.3
Low-Power IoT Processor Integrating Voltage-Scalable Fully Digital Memories
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
IoT Ten-Cent System-on-Chip Challenge at Design, Automation and Test in Europe (DATE) 2017 (poster) 2017.3
低遅延な線形光学多ビット入力AND回路の検討
北翔太, 北翔太, 野崎謙悟, 野崎謙悟, 江川巧, 石原亨, 新家昭彦, 新家昭彦, 納富雅也, 納富雅也
応用物理学会秋季学術講演会講演予稿集(CD-ROM) Vol. 78th 2017
Optical WDM parallel adder based on optical pass gate logic (2) ~ Experimental study using thermo-optic switch ~
Shinya Akihiko, Ishihara Tohru, Nozaki Kengo, Kita Shota, Inoue Koji, Cong Guangwei, Yamada Koji, Notomi Masaya
JSAP Annual Meetings Extended Abstracts Vol. 64th page： 934 - 934 2017
Vol. 116 ( 93 ) page： 109 - 114 2016.6
竹下 俊宏, 塩見 準, 石原 亨, 小野寺 秀俊
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 115 ( 519 ) page： 187 - 192 2016.3
Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling Reviewed
Toshinori Takeshita, Tohru Ishihara, Hidetoshi Onodera
2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) page： 1 - 4 2016
A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Reviewed
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) page： 691 - 696 2016
光パスゲート論理に基づく光演算回路
新家昭彦, 新家昭彦, 石原亨, 井上弘士, 野崎謙悟, 野崎謙悟, 納富雅也, 納富雅也
応用物理学会春季学術講演会講演予稿集(CD-ROM) Vol. 63rd 2016
光パスゲート論理に基づく光演算回路(II)
新家昭彦, 新家昭彦, 石原亨, 井上弘士, 野崎謙悟, 野崎謙悟, 納富雅也, 納富雅也
応用物理学会秋季学術講演会講演予稿集(CD-ROM) Vol. 77th 2016
Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
International Workshop on Variability Modeling and Charactorization 2015.11
TAKESHITA Toshihiro, NISHIZAWA Shinichi, ISLAM A.K.M. Mahfuzul, ISHIHARA Tohru, ONODERA Hidetoshi
Technical report of IEICE. VLD Vol. 114 ( 426 ) page： 111 - 116 2015.1
Vol. 2015 ( 20 ) page： 1 - 6 2015.1
An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) page： 23 - 28 2015
Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation Reviewed
Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) page： 181 - 185 2015
An Impact of Process Variation on Supply Voltage Dependence of Logic Path Delay Variation Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2015 International symposium on VLSI Design, Automation and Test (VLSI-DAT) page： 1 - 4 2015
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
International System on Chip Conference page： 42 - 47 2014.11
Variation-aware Flip-Flop energy optimization for ultra low voltage operation Reviewed
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
International System on Chip Conference page： 17 - 22 2014.11
A Lognormal Timing Model and Design Guidelines for Near-Threshold Circuits Reviewed
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
International Workshop on Variability Modeling and Characterization (VMC) 2014.11
排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装 (ディペンダブルコンピューティング 組込み技術とネットワークに関するワークショップETNET2014)
高瀬 英希, 李 景洙, 石原 亨
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 113 ( 498 ) page： 85 - 90 2014.3
LEE KYUNGSOO, ISHIHARA TOHRU
IEICE technical report. Dependable computing Vol. 113 ( 498 ) page： 127 - 132 2014.3
排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装 (コンピュータシステム 組込み技術とネットワークに関するワークショップETNET2014)
高瀬 英希, 李 景洙, 石原 亨
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 113 ( 497 ) page： 85 - 90 2014.3
排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装
高瀬英希, 李景洙, 石原亨
研究報告システムLSI設計技術（SLDM） Vol. 2014 ( 15 ) page： 1 - 6 2014.3
Vol. 2014 ( 22 ) page： 1 - 6 2014.3
C-12-44 Maximizing Energy Efficiency of LSI Circuits by Simultaneous Tuning of Supply Voltage and Back Bias
Takeshita Toshihiro, Nishizawa Shinichi, Mahfuzul Islam A.K.M., Ishihara Tohru, Onodera Hidetoshi
Proceedings of the IEICE General Conference Vol. 2014 ( 2 ) page： 108 2014.3
Analysis and Comparison of XOR Cell Structures for Low Voltage Circuit Design Reviewed
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013) page： 703 - 708 2013
Maximizing Energy-Efficiency of Dual-OS Platforms through DVFS Virtualization Invited International conference
Tohru Ishihara
International Forum on MPSoC for Software-Defined Hardware (MPSoC) 2022.6.23
Near-Threshold Cache Architecture for Ultra-Low Energy Computing Invited
2019.7.11
Minimum Energy Point Tracking Exploiting All-Digital On-Chip Sensors Invited
Tohru Ishihara
International Forum on MPSoC for Software-Defined Hardware 2018.7.30
Minimum Energy Point Tracking for Self-Powered IoT Processors Invited
2017.7.3
An Integrated Optical Parallel Adder: A First Step towards Light-Speed Data Path Operation Invited
Tohru Ishihara
International Forum on MPSoC for Software-Defined Hardware 2016.7.14
Practical Supply and Threshold Voltage Scaling for Energy Efficient Operation of Microprocessors Invited
Tohru Ishihara
International Forum on MPSoC for Software-Defined Hardware 2015.7.13
Near-Threshold Computing on Heterogeneous Multicore Architectures Invited
Tohru Ishihara
International Forum on Embedded MPSoC and Multicore 2014.7.10
Power Management Techniques for Energy Harvesting Embedded Systems Invited
Tohru Ishihara
International Forum on Embedded MPSoC and Multicore 2013.7.18
Loop Instruction Caching for Energy-Efficient Embedded Multitasking Systems Invited
Tohru Ishihara
International Forum on Embedded MPSoC and Multicore 2012.7.11
Energy Characterization of Embedded Processors for Software Energy Optimization Invited
Tohru Ishihara
International Forum on Embedded MPSoC and Multicore 2011.7.5
Real-Time Dynamic Voltage Hopping on MPSoCs Invited International conference
Tohru Ishihara
International Forum on Embedded MPSoC and Multicore (MPSoC) 2009.8.5
Grant number：20H04155 2020.4 - 2023.3
日本学術振興会 科学研究費助成事業 基盤研究(B) 基盤研究(B)
石原 亨, 納富 雅也, 塩見 準, 増田 豊, 塩見 準, 納富 雅也, 増田 豊
Authorship：Principal investigator Grant type：Competitive
Grant amount：\17550000 （ Direct Cost: \13500000 、 Indirect Cost：\4050000 ）
2000年以降のナノフォトニクス技術の急速な発展を背景に、光デバイスは数ミクロンのサイズまで超小型化され、光回路と電子回路を混載して集積することが可能となった。本課題は、光と電子が密に融合する光集積回路のアーキテクチャと設計技術を構築することにより、光集積回路における遅延-電力-面積のトレードオフ限界を明確にし、光集積回路の最適な構成を明らかにするものである。上記目的のために、下記の３項目に取り組む。1）回路設計段階で光集積回路の遅延、電力、面積を予測するモデルを構築する。2）光集積回路に対する設計最適化技術を構築する。3）光集積回路を非ノイマン型演算器に適用し最適化の効果を評価する。
A Study on Optical Computer Design through Photonics and Electronics Co-Optimization
Grant number：17K19975 2017.6 - 2020.3
Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Research (Exploratory) Grant-in-Aid for Challenging Research (Exploratory)
Ishihara Tohru
Authorship：Principal investigator Grant type：Competitive
Grant amount：\6370000 （ Direct Cost: \4900000 、 Indirect Cost：\1470000 ）
This project is focused on an in-network optical computing. We have developed several optical functional units such as parallel adders, parallel multipliers and optical neural networks. With the optical devices as circuit building blocks, the computational speed of the arithmetic functions is on the order of picosecond since the delay of the single optical device is less than one picosecond. This ultra-low-latency is the basic motivation of using the optical devices for the optical circuit synthesis. Several key techniques for reducing the power consumption of optical circuits have been also developed. With optoelectronic circuit simulation, we have demonstrated the light speed operation of the circuits.
Research on computing infrastructure aimed at realizing an IoT society to come
Grant number：17H01712 2017.4 - 2020.3
Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
Ishihara Tohru
Authorship：Principal investigator Grant type：Competitive
Grant amount：\18850000 （ Direct Cost: \14500000 、 Indirect Cost：\4350000 ）
We have developed a microprocessor and a power management algorithm running on operating systems, which always minimize the energy consumption of the microprocessor. The algorithm dynamically controls the supply voltage, threshold voltage and clock frequency of the microprocessor so that the energy consumption of the microprocessor is always minimized for a given operation condition which include ambient temperature and workload of the applications running on the microprocessor. We have developed microprocessor chips based on RISC-V, an open source microprocessor design and have confirmed that the microprocessor and the power management algorithm we have developed work effectively. More specifically, we run the power management algorithm on the microprocessor under different ambient temperature conditions using a thermostatic chamber and confirmed that the processor chip we have developed always operates with the minimum energy even in the different operating environments.
LSI Design Method for Minimum Energy Operation
Grant number：16H01713 2016.4 - 2020.3
Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A) Grant-in-Aid for Scientific Research (A)
Onodera Hidetoshi
Authorship：Coinvestigator(s)
We have developed a method for deriving a set of supply voltage and threshold voltage that enables the circuit to operate at the minimum energy consumption under a wide range of operating conditions and a specified delay constraint. We experimentally confirmed using a fabricated 32-bit processor that the derived set of supply voltage and threshold voltage can operate the circuit with less than 5 % excess energy from the minimum energy consumption under a wide variety of delay constraints and operating conditions. We also developed a DLL-type body bias generator that generate P/N well-voltages independently so that the energy consumption becomes minimum, which was verified by fabricated test chips.
A Study on on-chip memories suitable for near-threshold voltage operation
Grant number：26540021 2014.4 - 2017.3
Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research Grant-in-Aid for Challenging Exploratory Research
Ishihara Tohru
Authorship：Principal investigator
Grant amount：\3640000 （ Direct Cost: \2800000 、 Indirect Cost：\840000 ）
We have developed on-chip memory subsystems running with very low supply voltages. It has a functionality to stably run with very low supply voltages down to 0.25V. We have designed memory circuits integrating our idea for saving the area and energy consumption, which demonstrated that the energy efficiency of our memory circuit is twice better than existing on-chip SRAMs. We also integrated the memory circuits on microprocessor chips. The processor chip well runs with less than 0.3V voltage supply. We have obtained several awards such as IPSJ Yamashita Memorial Award and IEEE SSCS Japan Chapter VDEC Design Award which are given for the achievements in this research project.
A Study on Energy Harvesting Embedded Computers as a Social Infrastructure
Grant number：26280013 2014.4 - 2017.3
Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B) Grant-in-Aid for Scientific Research (B)
Ishihara Tohru
Authorship：Principal investigator
Grant amount：\16770000 （ Direct Cost: \12900000 、 Indirect Cost：\3870000 ）
We have developed a microprocessor system running with unstable power sources such as a photovoltaic power supply system. The microprocessor has a functionality to stably run with very low supply voltages down to 0.3V. We have fabricated several microprocessor chips integrating our idea for saving the energy dissipation, which demonstrated the energy efficiency of our idea integrated on the chip. We also developed a technique of tuning supply voltage and threshold voltage simultaneously, which minimizes the energy consumption per performance of the microprocessor. The voltage tuning technique works effectively on the microprocessor chips fabricated. We have obtained several awards such as IPSJ Yamashita Memorial Award and IEEE SOCC Best Paper Award which are given for the achievements in this research project.
Grant number：25280014 2013.4 - 2017.3
Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B) Grant-in-Aid for Scientific Research (B)
ONODERA Hidetoshi, NISHIZAWA Sinichi, Mahfuzul Islam A. K. M., NISHIZAWA Sinichi, Mahfuzul Islam A. K. M.
Authorship：Coinvestigator(s)
Under low voltage operation, variability of circuit performance increases due to process variations, which may result in functional failure. In order to maintain robust operation under low supply voltage close to the threshold voltage of transistors, an on-chip monitor circuit for estimating process variations and a body-bias generator for compensating the estimated process variations have been developed. Analytical stability modeling for CMOS latches, which are known to be susceptible to process variations, has been developed and design guidelines for variation-tolerant latches have been derived. With those techniques, a circuit with stable operation under low supply voltage down to the threshold voltage of transistors can be realized.
光乗算器および光乗算方法
新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 北 翔太 , 高田 健太 , 石原 亨 , 小野寺秀俊 , 今井悠貴
光論理回路
新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 北 翔太 , 石原 亨
光論理回路
新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 石原 亨
光乗算器および光乗算方法
新家 昭彦, 納富 雅也, 野崎 謙悟, 北 翔太, 高田 健太, 石原 亨, 小野寺秀俊, 今井悠貴
光演算器
新家 昭彦, 納富 雅也, 野崎 謙悟, 北 翔太, 高田 健太, 石原 亨, 小野寺秀俊, 江川巧
光論理回路
新家 昭彦, 納富 雅也, 野崎 謙悟, 北 翔太, 石原 亨
Optical Logic Circuit
光演算器
新家昭彦, 納富雅也, 野崎謙悟, 倉持栄一, 石原亨
光論理回路および加算器
新家 昭彦, 納富 雅也, 野崎 謙悟, 石原 亨, 井上弘士
消費電力評価装置、電力係数作成システム、消費電力評価方法及び電力係数作成方法
神山 剛, 宮沢 祐光, 石原 亨, 久住 憲嗣, 金田 裕介, 奥平 拓見
消費電力分析システムおよびアプリケーション開発ツール
小西 哲平, 神山 剛, 大久保 信三, 稲村 浩, 石原 亨, 久住 憲嗣, 部谷 修平
プロセッサ設計を特徴付けるための方法、装置、論理プログラム及びシステム
石原 亨, ファルザン ファラー
SoC design methodology
2020.10 - 2021.2 （Kyoto University）
Level：Postgraduate Country：Japan
光ニューラルネットワークに関する解説と研究記事が日経エレクトロニクスに掲載 Newspaper, magazine
日経BP社 日経エレクトロニクス 日経エレクトロニクス2021年3月号 pp.35-38 2021.3
光の伝搬でAI処理を行う光ニューラルネットワークの解説と研究記事が日経クロステックに掲載 Internet
日経BP社 日経クロステック https://xtech.nikkei.com/atcl/nxt/column/18/01558/00007/ 2021.2
情報処理学会 論文誌 System LSI Design Methodology 編集委員会 委員長 International contribution
Role(s)：Review, evaluation, Peer review
情報処理学会 2023.4
国際科学技術協力基盤整備事業「世界のトップ研究者ネットワーク参画のための国際研究協力プログラム」国際科学技術協力推進委員
Role(s)：Review, evaluation
科学技術振興機構（JST） 2022.12 - 2023.3
科研費 学術変革領域研究（A）の審査意見書の作成
Role(s)：Review, evaluation, Peer review
文部科学省 2022.3
電子情報通信学会 『Special Section on VLSI Design and CAD Algorithms』編集委員会 編集委員
Role(s)：Planning, management, etc., Peer review
2020.4
IEEE Symposium on Low-Power and High-Speed Chips and Systems組織委員会 副委員長 International contribution
Role(s)：Planning, management, etc., Panel moderator, session chair, etc.
2020.4
Asia and South Pacific Design Automation Conference, Steering Committee Secretary International contribution
Role(s)：Planning, management, etc.
2020.4
電子情報通信学会 『Special Section on Circuit and Systems』編集委員会 編集委員
Role(s)：Planning, management, etc., Peer review
2019.7 - 2020.9
電子情報通信学会回路とシステム研究専門委員会委員
Role(s)：Planning, management, etc.
2018.4 - 2021.3
