Updated on 2022/11/01

写真a

 
ISHIHARA Tohru
 
Organization
Graduate School of Informatics Department of Computing and Software Systems 2 Professor
Graduate School
Graduate School of Informatics
Undergraduate School
School of Informatics Department of Computer Science
Title
Professor
Contact information
メールアドレス
External link

Degree 1

  1. Doctor of engineering ( 2000.3   Kyushu University ) 

Research Interests 1

  1. Energy efficient computing, Low power design, Optical computing

Research Areas 2

  1. Informatics / Computer system  / Energy efficient computing

  2. Informatics / Computer system  / Energy Efficient Computing

Research History 9

  1. Nagoya University   Graduate School of Informatics Department of Computing and Software Systems 2   Professor

    2018.10

  2. Kyoto University   Graduate School of Informatics Department of Communications and Computer Engineering   Associate professor

    2011.4 - 2018.9

  3. Kyushu University   System LSI Research Center   Associate professor

    2007.4 - 2011.3

  4. Kyushu University   System LSI Research Center   Assistant Professor

    2005.8 - 2007.3

  5. Fujitsu Laboratories of America   Researcher

    2003.4 - 2005.7

  6. The University of Tokyo   Assistant

    2000.4 - 2003.4

  7. Japan Society for Promotion of Science

    1997.4 - 2000.3

  8. Nagoya University   Graduate School of Informatics   Professor

    2018.10

      More details

    Country:Japan

    researchmap

  9. Kyoto University   Graduate School of Informatics   Associate professor

    2011.4 - 2018.9

      More details

    Country:Japan

    researchmap

▼display all

Education 2

  1. Kyushu University

    1995.4 - 2000.3

      More details

    Country: Japan

  2. Kyushu University   Faculty of Engineering   Department of Computer Science and Communication Engineering

    1991.4 - 1995.3

      More details

    Country: Japan

Professional Memberships 4

  1. 電子情報通信学会

    2008.5

  2. 情報処理学会

    1994

  3. IEEE Computer Society

  4. ACM

Awards 17

  1. 科学技術分野の文部科学大臣表彰 若手科学者賞

    2009.4   文部科学省   マイクロプロセッサの省電力化に関する研究

    石原 亨

     More details

    Country:Japan

  2. 丸文研究奨励賞

    2007.3   丸文財団   ソフトウェア制御によるシステムLSIの低消費エネルギー化と微細化への対応

    石原 亨

     More details

    Award type:Award from publisher, newspaper, foundation, etc. 

  3. 長尾真記念特別賞

    2010.5   情報処理学会   コンピュータシステムの省エネルギー化に関する研究

    石原 亨

     More details

    Award type:Award from Japanese society, conference, symposium, etc. 

  4. 論文賞

    2013.5   電子情報通信学会   Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications

    Lovic Eric Gauthier, 石原 亨

     More details

    Award type:Award from Japanese society, conference, symposium, etc. 

  5. Best Paper Award

    2021.6   IEICE   Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits

    Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, and Masaya Notomi

     More details

    Award type:Honored in official journal of a scientific society, scientific journal  Country:Japan

  6. 論文賞

    2018.6   電子情報通信学会   Analytical Stability Modeling for CMOS Latches in Low Voltage Operation

    鎌苅竜也, 塩見準,石原亨,小野寺秀俊

     More details

    Award type:Award from Japanese society, conference, symposium, etc. 

  7. 情報処理学会創立40周年記念論文賞

    2000.3   情報処理学会   DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ

    井上弘士,石原亨,甲斐康司,村上和彰

     More details

    Country:Japan

  8. ISLPED 1st Most Cited Paper Award

    2015.9   IEEE/ACM International Symposium on Low Power Electronics and Design   Voltage scheduling problem for dynamically variable voltage processors

    Tohru Ishihara, Hiroto Yasuura

     More details

    Award type:Award from international society, conference, symposium, etc. 

  9. IEEE SOCC Best Paper Award

    2016.9   IEEE International System-on-Chip Conference   Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing

    Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera

     More details

    Award type:Award from international society, conference, symposium, etc. 

  10. Outstanding Paper Award

    2010.10   Workshop on Synthesis And System Integration of Mixed Information technologies   Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications

    Lovic Gauthier, Tohru Ishihara, Hideki, Hiroyuki,Hiroaki Takada

     More details

    Award type:Award from international society, conference, symposium, etc. 

  11. Outstanding Paper Award

    2021.3   Workshop on Synthesis And System Integration of Mixed Information technologies   An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier

    L. Hou, Y. Masuda, T. Ishihara

     More details

    Award type:Award from international society, conference, symposium, etc. 

  12. 情報処理学会システムLSI設計技術研究会優秀論文賞

    2016.9   情報処置学会システムLSI設計技術研究会  

     More details

    Award type:Award from Japanese society, conference, symposium, etc. 

  13. 情報処理学会システムLSI設計技術研究会優秀論文賞

    2013.8   情報処置学会システムLSI設計技術研究会  

     More details

    Award type:Award from Japanese society, conference, symposium, etc. 

  14. 情報処理学会システムLSI設計技術研究会優秀論文賞

    2002.7   情報処置学会システムLSI設計技術研究会  

  15. LSI IPデザイン・アワード MeP賞

    2008.4   LSI IPデザイン・アワード運営委員会  

     More details

    Award type:Award from publisher, newspaper, foundation, etc. 

  16. LSI IPデザイン・アワード IP優秀賞

    1999.5   LSI IPデザイン・アワード運営委員会  

     More details

    Award type:Award from publisher, newspaper, foundation, etc. 

  17. 情報処理学会九州支部奨励賞

    1998.5   情報処理学会九州支部  

▼display all

 

Papers 146

  1. DVFS virtualization for energy minimization of mixed-criticality dual-OS platforms Reviewed

    T. Komori, Y. Masuda, and T. Ishihara

    Proc. 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)     page: 128 - 137   2022.8

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  2. Power-Aware Pruning for Ultrafast, Energy-Efficient, and Accurate Optical Neural Network Design Reviewed

    N. Hattori, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi

    Proc. Design Automation Conference (DAC)     2022.7

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1145/3489517.3530405

  3. Optoelectronic Implementation of Compact and Power-Efficient Recurrent Neural Networks Reviewed

    N. Ichikawa, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi

    Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)     page: 390 - 393   2022.6

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  4. Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing Reviewed

    T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E105-A ( 3 ) page: 497 - 508   2022.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  5. Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits Reviewed

    J. Lu, Y. Masuda, T. Ishihara

    Proc. 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)     page: 20 - 25   2022.10

     More details

    Authorship:Last author   Language:English   Publishing type:Research paper (international conference proceedings)  

  6. Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits Reviewed

    Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera

    IEEE 35th International System-on-Chip Conference (SOCC)     page: 1 - 6   2022.9

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  7. Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling Reviewed

    Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E105-A ( 3 ) page: 509 - 517   2022.3

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

  8. Energy efficient OEO conversion and its applications to photonic integrated systems Reviewed International journal

    Shinya A., Nozaki K., Kita S., Ishihara T., Matsuo S., Notomi M.

    Proc. Optical Fiber Communications Conference and Exhibition (OFC)     2022.3

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Optics InfoBase Conference Papers  

    We describe nanophotonics-based opto-electric devices and their femtofarad integration. The combination of these devices and optical interference units has a potential to provide energy-efficient and ultra-low latency optical information processing.

    Scopus

  9. An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers Reviewed

    L. Hou, Y. Masuda, and T. Ishihara

    Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 568 - 573   2022.1

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  10. A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits Reviewed

    R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi,

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E104-A ( 11 ) page: 1546 - 1554   2021.11

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  11. Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation Reviewed

    N. Hattori, J. Shiomi, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E104-A ( 11 ) page: 1477 - 1487   2021.11

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  12. Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing Reviewed

    K. Yoshisue, Y. Masuda, and T. Ishihara

    Proc. IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)     2021.6

     More details

    Authorship:Last author   Language:English   Publishing type:Research paper (international conference proceedings)  

  13. Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing Reviewed

    T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara

    IEEE International Symposium on Quality Electronic Design (ISQED)     page: 300 - 306   2021.4

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  14. An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier Reviewed

    Lingxiao Hou,Yutaka Masuda,Tohru Ishihara

    Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)     2021.3

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  15. Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing Reviewed

    Naoki Hattori,Yutaka Masuda,Tohru Ishihara,Jun Shiomi,Akihiko Shinya,Masaya Notomi

    Proc. AI and Optical Data Sciences II. International Society for Optics and Photonics   Vol. 11703   page: 1E1 - 1E17   2021.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    DOI: https://doi.org/10.1117/12.2577966

    DOI: https://doi.org/10.1117/12.2577966

  16. Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design Reviewed

    Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto

    Proc. IEEE Design, Automation and Test in Europe Conference (DATE)     2021.2

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  17. An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. Reviewed

    Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

    Proc. International Conference on Rebooting Computing (ICRC)     page: 95 - 101   2020.12

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  18. Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling Reviewed

    Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto

    Proc. International Workshop on Logic and Synthesis (IWLS)     page: 136 - 142   2020.7

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  19. A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. Reviewed

    Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

    Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)     page: 488 - 493   2020.7

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  20. Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. Reviewed International coauthorship

    Khyati Kiyawat,Yutaka Masuda,Jun Shiomi,Tohru Ishihara

    Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)     page: 415 - 421   2020.7

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  21. On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing Reviewed

    Hongjie Xu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E102-A ( 12 ) page: 1741 - 1750   2019.12

     More details

    Authorship:Corresponding author  

  22. Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits Reviewed

    Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E102-A ( 12 ) page: 1751 - 1759   2019.12

     More details

    Authorship:Corresponding author  

  23. An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator Reviewed International journal

    Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi

    Photonics-Optics Technology Oriented Networking, Information, and Computing Systems (PHOTONICS) at The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC19)     2019.11

     More details

    Authorship:Lead author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  24. A Design Method of a Cell-Based Amplifier for Body Bias Generation Reviewed

    Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE Transactions on IEICE Transactions on Electronics   Vol. E102-C ( 7 ) page: 565 - 572   2019.7

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1587/transele.2018CTP0014

    researchmap

    Other Link: https://dblp.uni-trier.de/db/journals/ieicet/ieicet102c.html#KoyanagiSIO19

  25. BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing Reviewed International journal

    Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

    Proc. the 24th Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 203 - 209   2019.1

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:ACM  

    DOI: 10.1145/3287624.3287703

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/aspdac/aspdac2019.html#MatsuoSIOSN19

  26. An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms towards Light Speed Data Processing Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

    Proc. IEEE International Conference on Rebooting Computing (ICRC)     page: 62 - 67   2018.11

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/ICRC.2018.8638614

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/icrc/icrc2018.html#ShiomiIOSN18

  27. Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics Reviewed International journal

    Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

    Proc. IEEE International Conference on Rebooting Computing (ICRC)     page: 43 - 50   2018.11

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/ICRC.2018.8638607

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/icrc/icrc2018.html#EgawaIOSKNTN18

  28. Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization Reviewed

    Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera

    Proc.the 31st IEEE International System-on-Chip Conference (SOCC)     2018.9

  29. Independent N-well and P-well Biasing for Minimum Leakage Energy Operation Reviewed

    Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera

    Proc. the International Symposium on On-Line Testing and Robust System Design (IOLTS)     page: 177 - 182   2018.7

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/IOLTS.2018.8474128

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/iolts/iolts2018.html#OkamuraIO18

  30. Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure Reviewed International journal

    Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)     page: 237 - 242   2018.7

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/PATMOS.2018.8464141

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/patmos/patmos2018.html#XuSIO18

  31. Minimum Energy Point Tracking with All-Digital On-Chip Sensors

    Jun Shiomi, Shu Hokimoto, Tohru Ishihara, and Hidetoshi Onodera

    ASP Journal of Low Power Electronics   Vol. 14 ( 2 )   2018.6

     More details

    Authorship:Corresponding author   Language:English  

  32. An Integrated Nanophotonic Parallel Adder Reviewed

    Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi

    ACM Journal on Emerging Technologies in Computing (JETC)     2018.6

     More details

    Authorship:Lead author, Corresponding author   Language:English  

  33. An optical parallel multiplier using nanophotonic analog adders and optoelectronic analog-to-digital converters Reviewed

    Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

    Proceedings of Conference on Lasers and Electro-Optics (CLEO)   Vol. 2018   2018.5

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:OSA - The Optical Society  

    We proposes an architecture of an optical parallel multiplier based on an optical analog addition. With optoelectronic circuit simulation, we show that the optical multiplier is more than three times faster than the CMOS multiplier.

    DOI: 10.1364/CLEO_AT.2018.JW2A.50

    Scopus

    researchmap

  34. A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator Reviewed

    Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

    Japanese Journal of Applied Physics   Vol. 57 ( 4S ) page: 04FF09-1 - 04FF09-6   2018.3

     More details

    Language:English  

  35. A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits Reviewed

    Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 56 - 61   2018.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  36. On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation Reviewed

    Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

    Proc. Annual IEEE International Conference on Microelectronic Test Structures (ICMTS)     page: 111 - 116   2018.3

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  37. Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)     page: 45 - 50   2018.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  38. Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation Reviewed

    Yuta Nagaoka, Tohru Ishihara, Hidetoshi Onodera

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 290 - 295   2018.3

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  39. An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters Reviewed

    Yuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 100 - 105   2018.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  40. All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors Reviewed

    Shu Hokimoto, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. Annual IEEE International Conference on Microelectronic Test Structures (ICMTS)     page: 128 - 133   2018.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  41. A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies Reviewed

    Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 320 - 325   2018.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  42. A minimum energy point tracking algorithm based on dynamic voltage scaling and adaptive body biasing Reviewed

    Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E100A ( 12 ) page: 2776 - 2784   2017.12

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Institute of Electronics, Information and Communication, Engineers, IEICE  

    Scaling the supply voltage (VDD) and threshold voltage (VTH) for minimizing the energy consumption of processors dynamically is highly desired for applications such as wireless sensor network and Internet of Things (IoT). In this paper, we refer to the pair of VDD and VTH, which minimizes the energy consumption of the processor under a given operating condition, as a minimum energy point (MEP in short). Since the MEP is heavily dependent on an operating condition determined by a chip temperature, an activity factor, a process variation, and a performance required for the processor, it is not very easy to closely track the MEP at runtime. This paper proposes a simple but effective algorithm for dynamically tracking the MEP of a processor under a wide range of operating conditions. Gate-level simulation of a 32-bit RISC processor in a 65nm process demonstrates that the proposed algorithm tracks the MEP under a situation that operating condition widely vary.

    DOI: 10.1587/transfun.E100.A.2776

    Scopus

    researchmap

    Other Link: https://dblp.uni-trier.de/db/journals/ieicet/ieicet100a.html#HokimotoIO17

  43. A necessary and sufficient condition of supply and threshold voltages in CMOS circuits for minimum energy point operation Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E100A ( 12 ) page: 2764 - 2775   2017.12

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Institute of Electronics, Information and Communication, Engineers, IEICE  

    Scaling supply voltage (VDD) and threshold voltage (Vth) dynamically has a strong impact on energy efficiency of CMOS LSI circuits. Techniques for optimizing VDD and Vth simultaneously under dynamic workloads are thus widely investigated over the past 15 years. In this paper, we refer to the optimum pair of VDD and Vth, which minimizes the energy consumption of a circuit under a specific performance constraint, as a minimum energy point (MEP). Based on the simple transregional models of a CMOS circuit, this paper derives a simple necessary and sufficient condition for the MEP operation. The simple condition helps find the MEP of CMOS circuits. Measurement results using standard-cell based memories (SCMs) fabricated in a 65-nm process technology also validate the condition derived in this paper.

    DOI: 10.1587/transfun.E100.A.2764

    Scopus

    researchmap

    Other Link: https://dblp.uni-trier.de/db/journals/ieicet/ieicet100a.html#ShiomiIO17

  44. Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Elsevier: Integration, the VLSI Journal   ( 有り )   2017.7

     More details

    Language:English  

  45. On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator Reviewed

    Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

    2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)     page: 1 - 4   2017.4

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    This paper proposes a temperature monitoring scheme using a reconfigurable ring oscillator that has been proposed to estimate process variation. New circuit configurations, whose delay characteristics are sensitive to leakage current, are proposed to exploit the exponential dependence of the leakage current to temperature. Based on transistorlevel simulation assuming a 65 nm process technology, the oscillation frequency of the proposed circuit topology shows the temperature sensitivity of 5.0 %/degrees C at 20 degrees C and 2.9 %/ degrees C at 80 degrees C with low voltage sensitivity of 0.28 degrees C/10 mV at 25 degrees C and a supply voltage of 0.9 V. Estimation error of a 65 nm test chip ranges from -0.6 degrees C to 0.4 degrees C after two-point calibration. We also proposed a method to estimate the process variation and the temperature at the same time.

    DOI: 10.1109/VLSI-DAT.2017.7939649

    Web of Science

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2017.html#KishimotoIO17

  46. Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Reviewed

    Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   Vol. E99A ( 12 ) page: 2463 - 2472   2016.12

     More details

    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.

    DOI: 10.1587/transfun.E99.A.2463

    Web of Science

    researchmap

    Other Link: https://dblp.uni-trier.de/db/journals/ieicet/ieicet99a.html#KamakariSIO16

  47. A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)     page: 36 - 41   2016.10

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  48. Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications Reviewed

    Kei Yoshizawa, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)     page: 329 - 334   2016.10

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  49. An Integrated Optical Parallel Adder as a First Step Towards Light Speed Data Processing Reviewed International journal

    Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi

    2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)     page: 123 - 124   2016.10

     More details

    Authorship:Lead author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    Integrated optical circuits with nanophotonic devices have attracted significant attention due to its low power dissipation and light-speed operation. With light interference and resonance phenomena, the nanophotonic device works as a voltage-controlled optical pass-gate like a pass-transistor. This paper first introduces a concept of the optical pass-gate logic, and then proposes a parallel adder circuit based on the optical pass gate logic. Experimental results obtained with an optoelectronic circuit simulator show advantages of our optical parallel adder circuit over a traditional CMOS-based parallel adder circuit.

    DOI: 10.1109/ISOCC.2016.7799721

    Web of Science

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/isocc/isocc2016.html#IshiharaSINN16

  50. Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    PROCEEDINGS OF 2016 26TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS)     page: 44 - 49   2016.9

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area-and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using 65-nm FDSOI technology shows that the proposed SCM achieves area efficiency of 5.9 mu m(2) per bit (592F(2) per bit), which is less than that of the state of the art SCMs. The results also show that the energy consumption is further improved when the supply voltage scaling and back-gate biasing techniques are applied to our SCM.

    DOI: 10.1109/PATMOS.2016.7833424

    Web of Science

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/patmos/patmos2016.html#ShiomiIO16

  51. Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing Reviewed

    Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera

    Proc. IEEE International System-on-Chip Conference (SOCC)     page: 1 - 6   2016.9

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/SOCC.2016.7905420

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/socc/socc2016.html#HokimotoIO16

  52. Guidelines for effective and simplified dynamic supply and threshold voltage scaling Reviewed

    Toshinori Takeshita, Tohru Ishihara, Hidetoshi Onodera

    Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT)     2016.4

     More details

    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/vlsi-dat.2016.7482546

    researchmap

  53. Variability- and correlation-aware logical effort for near-threshold circuit design Invited Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. the17th International Symposium on Quality Electronic Design (ISQED)     page: 18 - 23   2016.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/isqed.2016.7479150

    researchmap

  54. A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. Reviewed

    Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    21st Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 691 - 696   2016.1

     More details

    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/ASPDAC.2016.7428092

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/aspdac/aspdac2016.html#KamakariSIO16

  55. Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring Reviewed

    A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   Vol. 50 ( 11 ) page: 2475 - 2490   2015.11

     More details

    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

    Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 mu m(2) and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.

    DOI: 10.1109/JSSC.2015.2461598

    Web of Science

    researchmap

  56. Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   Vol. E98A ( 7 ) page: 1455 - 1466   2015.7

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28 nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

    DOI: 10.1587/transfun.E98.A.1455

    Web of Science

    J-GLOBAL

    researchmap

    Other Link: https://dblp.uni-trier.de/db/journals/ieicet/ieicet98a.html#ShiomiIO15

  57. An impact of process variation on supply voltage dependence of logic path delay variation. Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Proc. VLSI Design, Automation and Test (VLSI-DAT)     page: 1 - 4   2015.4

     More details

    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/VLSI-DAT.2015.7114534

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2015.html#NishizawaIO15

  58. A Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation using Cell-Based Structure Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     2015.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  59. An energy-efficient on-chip memory structure for variability-aware near-threshold operation. Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 16th International Symposium on Quality Electronic Design (ISQED)     page: 23 - 28   2015.3

     More details

    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/ISQED.2015.7085372

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/isqed/isqed2015.html#ShiomiIO15

  60. Energy reduction by built-in body biasing with single supply voltage operation. Reviewed

    Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 16th International Symposium on Quality Electronic Design (ISQED)     page: 181 - 185   2015.3

     More details

    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/ISQED.2015.7085421

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/isqed/isqed2015.html#KamaeMTIO15

  61. Layout generator with flexible grid assignment for area efficient standard cell Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    IPSJ Transactions on System LSI Design Methodology   Vol. 8   page: 131 - 135   2015.2

     More details

    Language:English   Publishing type:Research paper (scientific journal)   Publisher:Information Processing Society of Japan  

    This paper discusses a standard cell layout generator that can be used to generate a standard cell library optimized to a target application. It can generate an area efficient layout from a virtual-grid symbolic layout with the ability of flexible grid positioning that considers local design rules enforced in a scaled technology. The generator reduces the cost of library design and enables an optimization of each cell with detailed layout information that can be used to estimate the performance of the cell under design. A standard cell library has been generated for commercial 28-nm FDSOI CMOS process using the proposed layout generator, and used for circuit design. Correct operation of designed circuit is observed form fabricated chip test.

    DOI: 10.2197/ipsjtsldm.8.131

    Scopus

    J-GLOBAL

    researchmap

  62. Microarchitectural-level statistical timing models for near-threshold circuit design. Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 20th Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 87 - 93   2015.1

     More details

    Authorship:Corresponding author   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/ASPDAC.2015.7058986

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/aspdac/aspdac2015.html#ShiomiIO15

  63. An Integrated Framework for Energy Optimization of Embedded Real-Time Applications Reviewed International journal

    Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   Vol. E97A ( 12 ) page: 2477 - 2487   2014.12

     More details

    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    This paper presents a framework for reducing the energy consumption of embedded real-time systems. We implemented the presented framework as both an optimization tookchain and an energy-aware real-time operating system. The framework consists of the integration of multiple techniques to optimize the energy consumption. The main idea behind our approach is to utilize trade-offs between the energy consumption and the performance of different processor configurations during task checkpoints, and to maintain memory allocation during task context switches. In our framework, a target application is statically analyzed at both intra-task and inter-task levels. Based on these analyzed results, run-time optimization is performed in response to the behavior of the application. A case study shows that our toolchain and real-time operating systems have achieved energy reduction while satisfying the real-time performance. The toolchain has also been successfully applied to a practical application.

    DOI: 10.1587/transfun.E97.A.2477

    Web of Science

    Scopus

    CiNii Research

    researchmap

    Other Link: https://dblp.uni-trier.de/db/journals/ieicet/ieicet97a.html#TakaseZGKATKKIT14

  64. Wide-Supply-Range All-Digital Leakage Variation Sensor for On-chip Process and Temperature Monitoring Reviewed International journal

    A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)     page: 45 - 48   2014.11

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. An estimation method of threshold voltage variation is then developed. Cell-base design approach is taken so that design cost is minimized. Measurement results from a 65-nm test chip show the validity of the proposed circuit. Total area is 4500 mu m(2) and active power consumption is 50 nW at 1.0 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as testing and post-silicon tuning.

    DOI: 10.1109/ASSCC.2014.7008856

    Web of Science

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/asscc/asscc2014.html#MahfuzulSIO14

  65. Variation-aware Flip-Flop energy optimization for ultra low voltage operation. Reviewed

    Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 27th IEEE International System-on-Chip Conference (SOCC)     page: 17 - 22   2014.10

     More details

    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/SOCC.2014.6948893

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/socc/socc2014.html#KamakariNIO14

  66. Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 27th IEEE International System-on-Chip Conference (SOCC)     page: 42 - 47   2014.9

     More details

    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/SOCC.2014.6948897

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/socc/socc2014.html#NishizawaIO14

  67. Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)     page: 28 - 32   2014.3

     More details

    Language:English  

    researchmap

  68. Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences   Vol. 96-A ( 12 ) page: 2499-2507   2013.12

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

  69. DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems Reviewed

    K. Lee, T. Ishihara

    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences   Vol. 96-A ( 12 ) page: 2660-2667   2013.12

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  70. Energy-efficient Dynamic Voltage and Frequency Scaling by P/N-performance Self-adjustment using Adaptive Body Bias, Reviewed

    A.K.M. Mahfuzul Islam, Norihiro Kamae, Tohru Ishihara, Hidetoshi Onodera

    Proc. the Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)     2013.10

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

    researchmap

  71. A standard cell optimization method for near-threshold voltage operations Reviewed

    Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   Vol. 7606   page: 32 - 41   2013.9

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Springer  

    Near-threshold voltage operation is a well-known solution for drastically improving the energy efficiency of microprocessors fabricated with the latest process technologies. However, it is not well studied how the optimal gate size of standard cells changes when the supply voltage of the microprocessors gets closer to the threshold voltage. This paper first shows an experimental observation that the optimal gate size for nearthreshold voltage which is 0.6V in this work is far from the optimal gate size for the nominal supply voltage which is 1.2V in our target process technology. Based on this fact, the paper next presents our cell optimization flow which finds the optimal gate sizes of individual standard cells operating at the near-threshold voltage. The experimental results show that, when operating at the 0.6V condition, the energy consumptions of several benchmark circuits synthesized with our standard cells optimized for the 0.6V condition can be reduced by 31% at the best case and by 23% on average compared with those of the same circuits synthesized with the cells optimized for the nominal supply voltage. © Springer-Verlag Berlin Heidelberg 2013.

    DOI: 10.1007/978-3-642-36157-9_4

    Scopus

    J-GLOBAL

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/patmos/patmos2012.html#KondoNIO12

  72. DLIC: Decoded loop instructions caching for energy-aware embedded processors Reviewed International coauthorship International journal

    Ji Gu, Hui Guo, Tohru Ishihara

    Transactions on Embedded Computing Systems   Vol. 13 ( 1 ) page: 6 - 26   2013.8

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

    With the explosive proliferation of embedded systems, especially through countless portable devices and wireless equipment used, embedded systems have become indispensable to the modern society and people's life. Those devices are often battery driven. Therefore, low energy consumption in embedded processors is important and becomes critical in step with the system complexity. The on-chip instruction cache (I-cache) is usually the most energy-consuming component on the processor chip due to its large size and frequent access operations. To reduce such energy consumption, the existing loop cache approaches use a tiny decoded cache to filter the I-cache access and instruction decode activity for repeated loop iterations. However, such designs are effective for small and simple loops, and only suitable for DSP kernel-like applications. They are not effectual for many embedded applications where complex loops are common. In this article, we propose a decoded loop instruction cache (DLIC) that is small, hence energy efficient, yet can capture most loops, including large nested ones with branch executions, so that a significant amount of I-cache accesses and instruction decoding can be eradicated. The experiments on a set of embedded benchmarks show that our proposed DLIC scheme can reduce energy consumption by up to 87% as compared to normal cache-only design. On average, 66% energy can be saved on instruction fetching and decoding, while at a performance overhead of only 1.4%. © 2013 ACM.

    DOI: 10.1145/2512464

    Web of Science

    Scopus

    researchmap

    Other Link: https://dblp.uni-trier.de/db/journals/tecs/tecs13.html#GuGI13

  73. An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)     2013.3

     More details

    Language:English  

    researchmap

  74. Analysis and comparison of XOR cell structures for low voltage circuit design. Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Proc. International Symposium on Quality Electronic Design (ISQED)     page: 703 - 708   2013.3

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    DOI: 10.1109/ISQED.2013.6523687

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/isqed/isqed2013.html#NishizawaIO13

  75. A flexible structure of standard cell and its optimization method for near-threshold voltage operation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Proc. the 30th International IEEE Conference on Computer Design (ICCD)     page: 235 - 240   2012.10

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  76. I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays Reviewed

    Kyungsoo Lee, Tohru Ishihara

    Proc. IEEE 10th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia)     page: 48 - 55   2012.10

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  77. Loop instruction caching for energy-efficient embedded multitasking processors Reviewed

    Ji Gu, Tohru Ishihara, Kyungsoo Lee

    Proc. IEEE 10th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia)     page: 97 - 106   2012.10

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  78. A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems Reviewed

    Ji Gu, Tohru Ishihara

    Proc. the 1st International Conference on Smart Grids and Green IT Systems (SMARTGREENS)     page: 197 - 202   2012.4

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  79. A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems Reviewed

    Kyungsoo Lee, Tohru Ishihara

    Proc. the 1st International Conference on Smart Grids and Green IT Systems (SMARTGREENS)     page: 175 - 182   2012.4

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  80. Processor energy characterization for compiler-assisted software energy reduction Reviewed

    L. Gauthier; T. Ishihara

    Journal of Electrical and Computer Engineering   - 英語   2012.1

     More details

    Authorship:Last author, Corresponding author   Language:English  

    DOI: 10.1155/2012/786943

  81. Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications Reviewed

    Lovic Gauthier, Tohru Ishihara

    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences   Vol. 94-A ( 12 ) page: 2597-2608   2011.12

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  82. RTOSのハードウェア化によるソフトウェアベースTCP/IP処理の高速化と低消費電力化 Reviewed

    丸山修孝;石原亨;安浦寛人

    電子情報通信学会論文誌 A   Vol. J94-A ( 9 ) page: 692 - 701   2011.9

     More details

    Authorship:Corresponding author   Language:Japanese  

  83. Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits Reviewed

    Takumi Okuhira, Tohru Ishihara

    Proc. the 21st International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)     page: 237 - 246   2011.9

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  84. An integrated optimization framework for reducing the energy consumption of embedded real-time applications Reviewed

    Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada

    Proc. International Symposium on Low Power Electronics and Design (ISLPED)     page: 271 - 276   2011.8

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  85. Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies Reviewed

    Maziar Goudarzi, Tohru Ishihara, Hamid Noori

    Transactions on High-Performance Embedded Architectures and Compilers   Vol. 3   page: 275-299   2011.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

    DOI: https://doi.org/10.1007/978-3-642-19448-1_15

  86. Developing an integrated verification and debug methodology Reviewed

    Akitoshi Matsuda, Tohru Ishihara

    Proc. Design, Automation and Test in Europe (DATE)     page: 503 - 504   2011.3

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  87. A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems Reviewed

    Tohru ISHIHARA

    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences   Vol. 93-A ( 12 ) page: 2533-2541   2010.12

     More details

    Authorship:Lead author, Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  88. SRAM leakage reduction by row/column redundancy under random within-die delay variation Reviewed

    M. Goudarzi; T. Ishihara

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems   Vol. 18 ( 12 ) page: 1660 - 1671   2010.12

     More details

    Authorship:Last author, Corresponding author   Language:English  

    DOI: 10.1109/TVLSI.2009.2026048

  89. Compiler assisted energy reduction techniques for embedded multimedia processors Invited Reviewed

    Lovic Gauthier, Tohru Ishihara

    Proc. the 2nd APSIPA Annual Summit and Conference     page: 27 - 36   2010.12

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  90. Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications Reviewed

    Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 7 - 12   2010.10

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  91. Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems Reviewed

    Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada

    Proc. the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)     page: 157 - 166   2010.10

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  92. Code and data placement for embedded processors with scratchpad and cache memories Reviewed

    Y. Ishitobi; T. Ishihara; H. Yasuura

    Journal of Signal Processing Systems   Vol. 60 ( 2 ) page: 211 - 224   2010.8

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1007/s11265-008-0306-3

  93. An RTOS in hardware for energy efficient software-based TCP/IP processing Reviewed

    Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura

    Proc. IEEE 8th Symposium on Application Specific Processors (SASP)     page: 58 - 63   2010.6

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  94. An implementation of energy efficient multi-performance processor for real-time applications Reviewed

    Chengjie Zang, Tohru Ishihara

    Proc. the 2010 International Conference on Green Circuits and Systems     page: 211 - 216   2010.6

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  95. Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories Reviewed

    Lovic Gauthier, Tohru Ishihara

    Proc. the 7th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia)     page: 116 - 125   2009.10

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  96. Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion Reviewed

    Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

    IPSJ Transactions on System LSI Design Methodology   Vol. 2   page: 189-199   2009.2

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

  97. An Optimization Technique for Low-Energy Embedded Memory Systems Reviewed

    Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

    IPSJ Transactions on System LSI Design Methodology   Vol. 2   page: 239-249   2009.2

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

  98. Way-Scaling to Reduce Power of Cache with Delay Variation Reviewed

    Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara

    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences   Vol. 91-A ( 12 ) page: 3576-3584   2008.12

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  99. A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation Reviewed

    M. Goudarzi; T. Ishihara; H. Yasuura

    Microelectronics Journal   Vol. 39 ( 12 ) page: 1797 - 1808   2008.12

     More details

    Language:English  

    DOI: 10.1016/j.mejo.2008.02.002

  100. Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption Reviewed

    Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura

    Proc. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)     page: 62 - 71   2008.9

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  101. Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation Reviewed

    Maziar Goudarzi, Tohru Ishihara

    Proc. International Symposium on Low Power Electronics and Design (ISLPED)     page: 93 - 98   2008.8

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  102. AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications Reviewed

    Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato

    Proc. IEEE Symposium on Application Specific Processors (SASP)     page: 83 - 88   2008.6

     More details

    Authorship:Lead author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  103. Simultaneous optimization of memory configuration and code allocation for low power embedded systems Reviewed

    Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

    Proc. the 18th ACM Great Lakes Symposium on VLSI     page: 403 - 406   2008.5

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  104. Instruction cache leakage reduction by changing register operands and using asymmetric sram cells Reviewed

    Maziar Goudarzi, Tohru Ishihara

    Proc. the 18th ACM Great Lakes Symposium on VLSI     page: 383 - 386   2008.5

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  105. Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems Reviewed

    Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami

    IEICE Transactions on Electronics   Vol. 91-C ( 4 ) page: 410-417   2008.4

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

  106. Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways Reviewed

    Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara

    Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)     page: 447 - 450   2008.4

     More details

    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  107. Value-dependence of SRAM leakage in deca-nanometer technologies Reviewed

    Maziar Goudarzi, Tohru Ishihara

    IEICE Electronic Express   Vol. 5   page: 23-28   2008.1

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

  108. Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation Reviewed

    Maziar Goudarzi, Tohru Ishihara, Mamid Noori

    Proc. High Performance Embedded Architectures and Compilers (HiPEAC)     page: 224 - 239   2008.1

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  109. Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems Reviewed

    Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami

    IEICE Transactions on Electronics   Vol. 90-C ( 10 ) page: 1983-1991   2007.10

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

  110. A Hybrid Memory Architecture for Low Power Embedded System Design Reviewed

    Tadayuki Matsumura, Yuriko Ishitobi, Tohru Ishihara, Maziar Goudarzi, Hiroto Yasuura

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 56 - 62   2007.10

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  111. Code placement for reducing the energy consumption of embedded processors with scratchpad and cache memories Reviewed

    Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

    Proc. IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia)     page: 13 - 18   2007.10

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  112. Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems Reviewed

    Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami

    Proc. Design, Automation and Test in Europe (DATE)     page: 1490 - 1495   2007.4

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  113. A software technique to improve yield of processor chips in presence of ultra-leaky SRAM cells caused by process variation Reviewed

    Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura

    Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 878 - 883   2007.1

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  114. An Energy Characterization Framework for Software-Based Embedded Systems Reviewed

    Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah

    Proc. IEEE Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia)     page: 59 - 64   2006.10

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  115. Exploiting Narrow Bitwidth Operations for Low Power Embedded Software Design Reviewed

    Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 51 - 56   2006.4

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  116. A simulation-based soft error estimation methodology for computer systems Reviewed

    Makoto Sugihara, Tohru Ishihara, Koji Hashimoto, Masanori Muroyama

    Proc. IEEE International Symposium on Quality Electronics Design (ISQED)     page: 196 - 203   2006.3

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  117. A cache-defect-aware code placement algorithm for improving the performance of processors Reviewed International coauthorship

    Tohru Ishihara, Farzan Fallah

    Proc. International Conference on Computer Aided Design (ICCAD)     page: 995 - 1001   2005.11

     More details

    Authorship:Lead author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  118. A non-uniform cache architecture for low power system design Reviewed International coauthorship

    Tohru Ishihara, Farzan Fallah

    Proc. International Symposium on Low Power Electronics and Design (ISLPED)     page: 363 - 368   2005.8

     More details

    Authorship:Lead author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  119. A Code Placement Technique for Improving the Performance of Processors with Defective Caches Reviewed

    Tohru Ishihara, Farzan Fallah

    Proc. International Workshop on Logic and Synthesis (IWLS)     page: 210 - 214   2005.6

     More details

    Authorship:Lead author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  120. A way memoization technique for reducing power consumption of caches in application specific integrated processors Reviewed

    Tohru Ishihara, Farzan Fallah

    Proc. Design, Automation and Test in Europe (DATE)     page: 358 - 363   2005.3

     More details

    Authorship:Lead author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  121. Comparative Study On Verilog-Based And C-Based Hardware Design Education Reviewed

    Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada

    Proc. International Conference on Microelectronics Systems Education (MSE)     page: 41 - 42   2003.6

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  122. オンチップメモリの高速化と低スタンバイリークを実現する閾値電圧の静的スケジューリング手法 Reviewed

    石原亨, 浅田邦博

    情報処理学会論文誌   Vol. 44 ( 5 ) page: 1284-1291   2003.5

     More details

    Authorship:Lead author   Language:Japanese   Publishing type:Research paper (scientific journal)  

  123. A Voltage Scheduling Technique for Fault-Tolerant Real-Time Microprocessor Systems Reviewed

    Tohru Ishihara

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 137 - 143   2003.4

     More details

    Authorship:Lead author, Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  124. An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories Reviewed

    Tohru Ishihara, Kunihiro Asada

    Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 282 - 287   2002.1

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  125. A power minimization technique for arithmetic circuits by cell selection Reviewed

    Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura

    Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 268 - 273   2002.1

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  126. A System Level Optimization Technique for Application Specific Low Power Memories Reviewed

    Tohru ISHIHARA, Kunihiro ASADA

    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences   Vol. E84-A ( 11 ) page: 2755-2761   2001.11

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (scientific journal)  

  127. 入力信号パターンを考慮した低電力算術演算回路の設計手法 Reviewed

    室山真徳,石原亨,兵頭章彦,安浦寛人

    情報処理学会論文誌   Vol. 42 ( 4 ) page: 1007-1015   2001.4

     More details

    Language:Japanese   Publishing type:Research paper (scientific journal)  

  128. DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ Reviewed

    井上弘士, 石原亨,甲斐康司,村上和彰

    情報処理学会論文誌   Vol. 42 ( 3 ) page: 419-431   2001.3

     More details

    Language:Japanese   Publishing type:Research paper (scientific journal)  

  129. Software energy reduction techniques for variable-voltage processors Reviewed

    T. Okuma; H. Yasuura; T. Ishihara

    IEEE Design and Test of Computers   Vol. 18 ( 2 ) page: 31 - 41   2001.3

     More details

    Authorship:Last author   Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1109/54.914613

  130. A system level memory power optimization technique using multiple supply and threshold voltages Reviewed

    Tohru Ishihara, Kunihiro Asada

    Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 456 - 461   2001.1

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  131. 可変電源電圧プロセッサに対するリアルタイムタスクスケジューリング手法 Reviewed

    大隈孝憲, 石原亨, 安浦寛人

    電子情報通信学会論文誌   Vol. J83-C ( 6 ) page: 454-462   2000.6

     More details

    Language:Japanese   Publishing type:Research paper (scientific journal)  

  132. Flexible system LSI for embedded systems and its optimization techniques Reviewed

    A. Inoue; T. Ishihara; H. Yasuura

    Design Automation for Embedded Systems   Vol. 5 ( 2 ) page: 179 - 205   2000.6

     More details

    Language:English  

    DOI: 10.1023/A:1008974723452

  133. A power reduction technique with object code merging for application specific embedded processors Reviewed

    Tohru Ishihara, Hiroto Yasuura

    Proc. Design, Automation and Test in Europe (DATE)     page: 617 - 623   2000.3

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  134. System LSI design methods for low power LSIs Invited Reviewed

    H. Yasuura; T. Ishihara

    IEICE Transactions on Electronics   Vol. E83-C ( 2 ) page: 143 - 152   2000.2

     More details

    Authorship:Last author   Language:English  

  135. A high-performance and low-power cache architecture with speculative way-selection Reviewed

    K. Indue; T. Ishihara; K. Kai; K. Murakami

    IEICE Transactions on Electronics   Vol. E83-C ( 2 ) page: 186 - 193   2000.2

     More details

    Language:English  

  136. A memory power optimization technique for application specific embedded systems Reviewed

    T. Ishihara; H. Yasuura

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E82-A ( 11 ) page: 2366 - 2374   1999.11

     More details

    Authorship:Lead author   Language:English  

  137. Real-time task scheduling for a variable voltage processor Reviewed

    Takanori Okuma, Tohru Ishihara, Hiroto Yasuura

    Proc. the 12th International Symposium on System Synthesis (ISSS)     page: 24 - 29   1999.11

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  138. Way-predicting set-associative cache for high performance and low energy consumption Reviewed

    Koji Inoue, Tohru Ishihara, Kazuaki Murakami

    Proc. International Symposium on Low Power Electronics and Design (ISLPED)     page: 273 - 275   1999.8

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  139. Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches Reviewed

    H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E81-A ( 12 ) page: 2621 - 2629   1998.12

     More details

    Language:English   Publishing type:Research paper (scientific journal)  

  140. Programmable power management architecture for power reduction Reviewed

    T. Ishihara; H. Yasuura

    IEICE Transactions on Electronics   Vol. E81-C ( 9 ) page: 1473 - 1479   1998.9

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (scientific journal)  

  141. Voltage scheduling problem for dynamically variable voltage processors Reviewed

    Tohru Ishihara, Hiroto Yasuura

    Proc. International Symposium on Low Power Electronics and Design (ISLPED)     page: 197 - 202   1998.8

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  142. Instruction Scheduling for Power Reduction in Processor-Based System Design Reviewed

    Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura

    Proc. Design, Automation and Test in Europe (DATE)     page: 855 - 860   1998.2

     More details

    Language:English   Publishing type:Research paper (international conference proceedings)  

  143. Power-Pro: Programmable Power Management Architecture Reviewed

    Tohru Ishihara, Hiroto Yasuura

    Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 321 - 322   1998.2

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  144. Optimization of Supply Voltage Assignment for Power Reduction on Processor Based Systems Reviewed

    Tohru Ishihara, Hiroto Yasuura

    Proc. the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)     page: 170 - 177   1997.12

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  145. Experimental analysis of power estimation models of CMOS VLSI circuits Reviewed

    Tohru Ishihara, Hiroto Yasuura

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E80-A ( 3 ) page: 480 - 486   1997.3

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (scientific journal)  

  146. Basic experimentation on accuracy of power estimation for CMOS VLSI circuits Reviewed

    Tohru Ishihara, Hiroto Yasuura

    Proc. International Symposium on Low Power Electronics and Design (ISLPED)     page: 117 - 120   1996.8

     More details

    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

▼display all

Books 3

  1. Multi-Processor System-on-Chip 1

    Jun Shiomi, Tohru Ishihara( Role: Joint author ,  Chapter 10: Minimum Energy Computing via Supply and Threshold Voltage Scaling (pp. 227-254))

    Wiley – ISTE  2021.3 

     More details

    Language:English Book type:Textbook, survey, introduction

    researchmap

  2. CMOS VLSI Design - A Circuits and Systems Perspective 4th ed.

    Tohru Ishihara( Role: Joint translator ,  Chapter 5 Power)

    2014.1 

     More details

  3. Essential Issues in SOC Design: Designing Complex Systems-on-Chip

    H. Yasuura, T. Ishihara, M. Muroyama( Role: Contributor ,  Chapter 6: Energy Management Techniques for SOC Design)

    Springer  2006.10 

MISC 41

  1. 近似コンピューティング回路の設計最適化に向けた計算重要度評価技術

    陸佳萱, 増田豊, 石原亨

    情報処理学会研究報告(Web)   Vol. 2021 ( SLDM-195 )   2021

  2. 近似コンピューティング回路の品質検証を高速化するファジングテスト法

    本多佑成, 増田豊, 石原亨

    情報処理学会研究報告(Web)   Vol. 2021 ( SLDM-195 )   2021

  3. ファジングと高位合成を用いた近似コンピューティング回路のタイミング検証手法

    熊谷僚太, 増田豊, 石原亨

    情報処理学会研究報告(Web)   Vol. 2021 ( SLDM-195 )   2021

  4. Approximate Minimum Energy Point Tracking Which Guarantees Real-Time Responses of Tasks

    小森工, 増田豊, 塩見準, 石原亨

    回路とシステムワークショップ論文集(CD-ROM)   Vol. 34th   2021

  5. ニューラルネットワークの集積ナノフォトニクス実装に適した回路構造探索—Circuit-Architecture Exploration for Optical Neural Network based on Integrated Nanophotonics—VLSI設計技術

    服部 直樹, 増田 豊, 石原 亨, 塩見 準, 新家 昭彦, 納富 雅也

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 119 ( 443 ) page: 251 - 256   2020.3

     More details

    Language:Japanese   Publisher:電子情報通信学会  

    CiNii Books

    researchmap

    Other Link: http://id.ndl.go.jp/bib/030359303

  6. 遅延故障に起因する回路寿命分布の確率的高速推定手法—Stochastic fast estimation of timing error induced circuit lifetime distribution—VLSI設計技術

    富山 葉月, 増田 豊, 石原 亨

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 119 ( 443 ) page: 113 - 118   2020.3

     More details

    Language:Japanese   Publisher:電子情報通信学会  

    CiNii Books

    researchmap

    Other Link: http://id.ndl.go.jp/bib/030363102

  7. Towards the realization of low-latency and high-efficiency photoelectronic accelerators

    北翔太, 北翔太, 野崎謙悟, 野崎謙悟, 小野真証, 小野真証, 高田健太, 高田健太, 新家昭彦, 新家昭彦, CONG G., 山本宗継, 前神有里子, 大野守史, 山田浩治, 川上哲志, 井上弘士, 石原亨, 納富雅也, 納富雅也

    応用物理学会春季学術講演会講演予稿集(CD-ROM)   Vol. 67th   page: 1200 - 1200   2020

     More details

    Language:Japanese   Publisher:The Japan Society of Applied Physics  

    DOI: 10.11470/jsapmeeting.2020.1.0_1200

    J-GLOBAL

    researchmap

  8. 集積ナノフォトニクスに基づく近似並列乗算器を用いた低レイテンシ光ニューラルネットワーク—VLSI設計技術 ; デザインガイア2019 : VLSI設計の新しい大地

    塩見 準, 石原 亨, 小野寺 秀俊, 新家 昭彦, 納富 雅也

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 119 ( 282 ) page: 127 - 132   2019.11

     More details

    Language:Japanese   Publisher:電子情報通信学会  

    CiNii Books

    researchmap

  9. A Process-Scheduler-Based Approach to Minimum Energy Point Tracking

    Shengyu Liu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    DA Symposium 2019 (poster)     2019.8

     More details

    Authorship:Corresponding author   Language:English  

    researchmap

  10. 幅広い動作環境にわたってLSIの最大遅延特性を追跡するクリティカルパスレプリカの構成法—A Method of Constructing a Replica Circuit Tracking Maximum Delay Characteristics of an LSI Circuit over a Wide Range of Operating Environments—VLSI設計技術

    福田 展和, 塩見 準, 石原 亨, 小野寺 秀俊

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 118 ( 29 ) page: 25 - 30   2018.5

     More details

    Language:Japanese   Publisher:電子情報通信学会  

    CiNii Books

    researchmap

  11. 光パスゲート論理に基づく超低遅延光回路—特集 集積ナノフォトニクス研究の最前線

    新家 昭彦, 石原 亨, 井上 弘士, 野崎 謙悟, 納富 雅也

    NTT技術ジャーナル / 日本電信電話株式会社 編   Vol. 30 ( 5 ) page: 28 - 31   2018.5

     More details

    Language:Japanese   Publisher:電気通信協会  

    CiNii Books

    researchmap

  12. 光パスゲート論理に基づく光波長多重並列加算器(2)~熱光学スイッチによる動作実証~

    新家昭彦, 新家昭彦, 石原亨, 野崎謙悟, 野崎謙悟, 北翔太, 北翔太, 井上弘士, CONG Guangwei, 山田浩治, 納富雅也, 納富雅也

    応用物理学会秋季学術講演会講演予稿集(CD-ROM)   Vol. 79th   2018

  13. <高校生のページ>人に寄り添う安全安心なコンピュータの実現を目指して

    石原 亨, 小野寺 秀俊

    Cue : 京都大学電気関係教室技術情報誌   Vol. 38   page: 58 - 62   2017.9

     More details

    Language:Japanese   Publisher:京都大学電気関係教室・洛友会  

    DOI: 10.14989/227456

    CiNii Books

    researchmap

  14. IoT向け超省エネルギープロセッサのための完全ディジタル型メモリ

    塩見 準, 石原 亨, 小野寺 秀俊

    LSIとシステムのワークショップ2017 (poster)     2017.5

     More details

    Authorship:Corresponding author   Language:Japanese  

    researchmap

  15. ロジック部およびメモリ部の独立電圧制御によるプロセッサの消費エネルギー最小化 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2017)

    塩見 準, 石原 亨, 小野寺 秀俊

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 116 ( 511 ) page: 87 - 92   2017.3

     More details

    Language:Japanese   Publisher:電子情報通信学会  

    CiNii Books

    researchmap

  16. A Voltage-Scalable Fully Digital On-Chip Memory for Ultra-Low-Power IoT Processors

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    University Booth at Design, Automation and Test in Europe (DATE) 2017 (poster)     2017.3

     More details

    Language:English  

    researchmap

  17. Low-Power IoT Processor Integrating Voltage-Scalable Fully Digital Memories

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IoT Ten-Cent System-on-Chip Challenge at Design, Automation and Test in Europe (DATE) 2017 (poster)     2017.3

     More details

    Authorship:Corresponding author   Language:English  

    researchmap

  18. 低遅延な線形光学多ビット入力AND回路の検討

    北翔太, 北翔太, 野崎謙悟, 野崎謙悟, 江川巧, 石原亨, 新家昭彦, 新家昭彦, 納富雅也, 納富雅也

    応用物理学会秋季学術講演会講演予稿集(CD-ROM)   Vol. 78th   2017

  19. Optical WDM parallel adder based on optical pass gate logic (2) ~ Experimental study using thermo-optic switch ~

    Shinya Akihiko, Ishihara Tohru, Nozaki Kengo, Kita Shota, Inoue Koji, Cong Guangwei, Yamada Koji, Notomi Masaya

    JSAP Annual Meetings Extended Abstracts   Vol. 64th   page: 934 - 934   2017

     More details

    Language:Japanese   Publisher:The Japan Society of Applied Physics  

    DOI: 10.11470/jsapmeeting.2018.2.0_934

    J-GLOBAL

    researchmap

  20. A Parallel Adder Circuit based on Optical Pass-gate Logic and Its Evaluation with Optoelectronic Circuit Simulator

      Vol. 116 ( 93 ) page: 109 - 114   2016.6

     More details

    Language:Japanese  

    CiNii Books

    researchmap

  21. CMOS LSIにおけるエネルギー最小点追跡のための電源電圧としきい値電圧の動的調節指針 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2016)

    竹下 俊宏, 塩見 準, 石原 亨, 小野寺 秀俊

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 115 ( 519 ) page: 187 - 192   2016.3

     More details

    Language:Japanese   Publisher:電子情報通信学会  

    CiNii Books

    researchmap

  22. Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling Reviewed

    Toshinori Takeshita, Tohru Ishihara, Hidetoshi Onodera

    2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)     page: 1 - 4   2016

     More details

    Authorship:Corresponding author   Language:English   Publishing type:Research paper, summary (international conference)   Publisher:IEEE  

    Scaling supply voltage (V-DD) and threshold voltage (V-TH) dynamically has a strong impact on energy efficiency of CMOS LSI circuits. Techniques for optimizing V-DD and V-TH simultaneously under dynamic workloads are thus widely investigated over the past 15 years. This paper for the first time shows the following properties for dynamic voltage scaling; i) if V-DD is sufficiently higher than V-TH, tuning only V-DD with a fixed V-TH maximizes the energy efficiency, ii) if V-DD is nearthreshold, tuning only V-TH with a fixed V-DD maximizes the energy efficiency, and iii) if V-DD is subthreshold, tuning V-DD and/or V-TH for a dynamic workload does not improve energy efficiency. These properties help simplify the procedure of voltage scaling, and reduce the cost for providing different V(DD)s and V(TH)s.

    DOI: 10.1109/VLSI-DAT.2016.7482546

    Web of Science

    researchmap

  23. A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Reviewed

    Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)     page: 691 - 696   2016

     More details

    Language:English   Publishing type:Research paper, summary (international conference)   Publisher:IEEE  

    A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchronous LSI circuits. In this paper, an analytical stability model for a cross-coupled inverter operating in a sub-threshold voltage region is proposed. The proposed model analytically shows that the minimum operating voltage of the cross-coupled inverter distributes normally in a high-sigma region if the distribution of the threshold voltage is Gaussian. The minimum supply voltage at which the yield of the cross-coupled inverter becomes a specific value can be accurately derived by a simple calculation using the model. Monte-Carlo simulation assuming a commercial 28 nm process technology demonstrates the accuracy and the validity of the proposed model. Based on the model, this paper shows strategies for variation tolerant memory design.

    DOI: 10.1109/ASPDAC.2016.7428092

    Web of Science

    researchmap

  24. 光パスゲート論理に基づく光演算回路

    新家昭彦, 新家昭彦, 石原亨, 井上弘士, 野崎謙悟, 野崎謙悟, 納富雅也, 納富雅也

    応用物理学会春季学術講演会講演予稿集(CD-ROM)   Vol. 63rd   2016

  25. 光パスゲート論理に基づく光演算回路(II)

    新家昭彦, 新家昭彦, 石原亨, 井上弘士, 野崎謙悟, 野崎謙悟, 納富雅也, 納富雅也

    応用物理学会秋季学術講演会講演予稿集(CD-ROM)   Vol. 77th   2016

  26. Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    International Workshop on Variability Modeling and Charactorization     2015.11

     More details

    Language:English   Publishing type:Research paper, summary (international conference)   Publisher:IEEE  

    researchmap

    Other Link: https://dblp.uni-trier.de/db/conf/isqed/isqed2016.html#ShiomiIO16

  27. Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits

    TAKESHITA Toshihiro, NISHIZAWA Shinichi, ISLAM A.K.M. Mahfuzul, ISHIHARA Tohru, ONODERA Hidetoshi

    Technical report of IEICE. VLD   Vol. 114 ( 426 ) page: 111 - 116   2015.1

     More details

    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    Simultaneous supply and threshold voltage tuning has a strong impact on the energy reduction of LSI circuits. Therefore, techniques for optimizing the supply and threshold voltages simultaneously under a specific delay constraint of LSI circuits are widely investigated over the past 15 years. However, only a few previous work investigate techniques for effectively reducing the energy consumption of circuits with a small number of different supply and threshold voltages. In this paper, we present several interesting properties which are very useful for reducing the energy consumption of circuits with a small number of different supply and threshold voltages. Those properties are numerically explained using analytical delay and energy consumption models. Through circuit simulation using a commercial 28nm process technology model, we demonstrate that the properties presented in this paper hold for actual LSI circuits.

    CiNii Books

    researchmap

  28. Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits

      Vol. 2015 ( 20 ) page: 1 - 6   2015.1

     More details

    Language:Japanese   Publisher:Information Processing Society of Japan (IPSJ)  

    Simultaneous supply and threshold voltage tuning has a strong impact on the energy reduction of LSI circuits. Therefore, techniques for optimizing the supply and threshold voltages simultaneously under a specific delay constraint of LSI circuits are widely investigated over the past 15 years. However, only a few previous work investigate techniques for effectively reducing the energy consumption of circuits with a small number of different supply and threshold voltages. In this paper, we present several interesting properties which are very useful for reducing the energy consumption of circuits with a small number of different supply and threshold voltages. Those properties are numerically explained using analytical delay and energy consumption models. Through circuit simulation using a commercial 28nm process technology model, we demonstrate that the properties presented in this paper hold for actual LSI circuits.

    CiNii Books

    researchmap

  29. An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015)     page: 23 - 28   2015

     More details

    Language:English   Publishing type:Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher:IEEE  

    On-chip memory is one of the most energy consuming components in processors. Aggressive voltage scaling to the sub-/near-threshold region is thus applied even to the memory used for ultra-low power applications. In this paper, an energy-efficient cell-based memory structure which is stably working with a near-threshold operating voltage is proposed. The circuit simulation using a commercial 28-nm technology shows that the energy consumption for the readout operation in our memory proposed here is up to 61% less than the energy dissipated in an existing cell-based memory and a conventional SRAM circuit. The simulation using a foundry provided Monte Carlo package also shows that the 3 sigma worst case read-access time of our cell-based memory is comparable to that of the SRAM circuit.

    DOI: 10.1109/ISQED.2015.7085372

    Web of Science

    researchmap

  30. Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation Reviewed

    Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

    PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015)     page: 181 - 185   2015

     More details

    Language:English   Publishing type:Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher:IEEE  

    Energy-efficiency has become the driving force of today's LSI industry. In order to achieve minimum energy operation of LSI, we propose a built-in body biasing technique which generates independent body biases for nMOSFET and pMOSFET separately. We design and fabricate an application circuit integrated with our proposed built-in body bias generation (BBG) circuits in a 65-nm process. The application circuit consists of AES cipher and decipher modules. The BBG does not require an external supply and it is compatible with a dynamic voltage scaling scheme for the application circuit. Cell-based design of the BBG circuit has been applied to facilitate automatic place and route. Both of the AES and the BBG circuits have been routed simultaneously to reduce design and area overhead. In post-silicon, supply voltage and body bias voltages are selected to achieve the minimum energy consumption for a target frequency. From the measurement results, more than 20% of energy reduction is achieved compared with adjusting supply voltage alone.

    DOI: 10.1109/ISQED.2015.7085421

    Web of Science

    researchmap

  31. An Impact of Process Variation on Supply Voltage Dependence of Logic Path Delay Variation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    2015 International symposium on VLSI Design, Automation and Test (VLSI-DAT)     page: 1 - 4   2015

     More details

    Language:English   Publishing type:Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher:IEEE  

    Dynamic Voltage and Frequency Scaling ( DVFS) technique requires accurate observation of critical path delay for robust operation under aggressive supply voltage scaling. Logic paths contain several types of logic gates and path delay have voltage dependences because different logic gates have different voltage dependences. However, it is not well investigated that how the voltage dependence of the path delay changes induced by process variation. This paper describes the effect of the process variation on the voltage dependence of path delay. Ring Oscillator circuits fabricated in 65-nm CMOS process are used for the evaluation and analysis of the process variation dependence of the voltage delay curves.

    Web of Science

    researchmap

  32. Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    International System on Chip Conference     page: 42 - 47   2014.11

     More details

    Language:English   Publishing type:Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher:IEEE Computer Society  

    This paper describes the process variation tolerant design of DFFs for low voltage operation. Within-die random variation have a strong impact on the delay performance of DFF, especially at low supply voltage. Since a large number of DFFs are used in a VLSI chip, operation failure or timing failure of DFFs cause operation failure of a VLSI chip. This paper analyzes operation failures of DFFs using Monte-Carlo analysis and evaluate the effect of within-die variation on the delay performance of DFFs. In order to mitigate the effect of within-die variation, variation tolerant DFF design is proposed. The post layout simulation result shows increasing the sizes of the input clocked inverter and the clock driver reduce the operational failure of DFFs.

    DOI: 10.1109/SOCC.2014.6948897

    Scopus

    researchmap

  33. Variation-aware Flip-Flop energy optimization for ultra low voltage operation Reviewed

    Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    International System on Chip Conference     page: 17 - 22   2014.11

     More details

    Language:English   Publishing type:Research paper, summary (international conference)   Publisher:IEEE Computer Society  

    This paper presents an energy optimization method for a Flip-Flop (FF) circuit in a presence of manufacturing process variation. The optimal FF circuit can be obtained by simultaneously scaling the supply voltage and the transistor size with achieving a specific high yield of the circuit. Lowering the supply voltage is one of the most effective approaches for decreasing the energy consumption of the circuit. However, the increased variation in nano scale semiconductor devices causes a malfunction of FFs especially for the very low voltage operation. Therefore, it is a challenging goal for the nano scale FFs to achieve the high yield and extremely low energy consumption simultaneously. This paper proposes an approximation method for accurately estimating a minimum possible operating voltage (VDDmin) of FFs with a small number of Monte-Carlo trials. After that, for a given FF, we find a set of optimal supply voltage and the transistor sizes, which minimizes the energy consumption of the FF with achieving the specific high-sigma yield (e.g., 5σ yield). Post layout Monte-Carlo simulation results obtained using a commercial 28 nm process technology model demonstrate that the energy consumption of a FF optimized with our approach can be reduced by 17% at the best case with achieving 5σ yield.

    DOI: 10.1109/SOCC.2014.6948893

    Scopus

    researchmap

  34. A Lognormal Timing Model and Design Guidelines for Near-Threshold Circuits Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    International Workshop on Variability Modeling and Characterization (VMC)     2014.11

     More details

    Language:English  

    researchmap

  35. 排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装 (ディペンダブルコンピューティング 組込み技術とネットワークに関するワークショップETNET2014)

    高瀬 英希, 李 景洙, 石原 亨

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 113 ( 498 ) page: 85 - 90   2014.3

     More details

    Language:Japanese   Publisher:一般社団法人電子情報通信学会  

    高性能CPUコアと省電力CPUコアを排他的かつ動的に切り替えて動作するマルチパフォーマンスプロセッサのテストチップを,65nmの商用プロセステクノロジを用いて試作した.各CPUコアはそれぞれの電源電圧に最適化して設計しているため,低電圧動作時のエネルギー効率が従来型のDVFSプロセッサより高くなる.CPUコア間でオンチップメモリを共有することで,面積効率を向上させるとともにCPUコアの切替に掛かるオーバヘッドを抑止させる.さらに,組込みリアルタイムシステムへの応用を想定して,マルチパフオーマンスプロセッサの動作構成を切り替えて電力を管理する機能を提案する.電力管理機能をTOPPERS/ASPカーネル上に実装し,実チップ測定に基づいて評価した結果を報告する.

    CiNii Books

    researchmap

  36. Evaluation of Charge Scheduling on a Multi-Banked Supercapacitor Architecture for Energy Harvesting Embedded Systems

    LEE KYUNGSOO, ISHIHARA TOHRU

    IEICE technical report. Dependable computing   Vol. 113 ( 498 ) page: 127 - 132   2014.3

     More details

    Language:English   Publisher:The Institute of Electronics, Information and Communication Engineers  

    Energy-harvesting devices attract wide interest as replacements for primary batteries in low power embedded systems. This claims new energy efficient management techniques for the energy-harvesting systems dislike the previous management techniques. This paper evaluates a charge scheduling technique on a multi-banked supercapacitor architecture as well as a simple maximum point tracking algorithm (MPPT). We design an energy harvesting board with a multi-banked supercapacitor architecture, and operate it in a real system. The evaluation focuses on the energy loss reduction by the charge scheduling technique in the power supplier of the system.

    CiNii Books

    researchmap

  37. 排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装 (コンピュータシステム 組込み技術とネットワークに関するワークショップETNET2014)

    高瀬 英希, 李 景洙, 石原 亨

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 113 ( 497 ) page: 85 - 90   2014.3

     More details

    Language:Japanese   Publisher:一般社団法人電子情報通信学会  

    高性能CPUコアと省電力CPUコアを排他的かつ動的に切り替えて動作するマルチパフォーマンスプロセッサのテストチップを,65nmの商用プロセステクノロジを用いて試作した.各CPUコアはそれぞれの電源電圧に最適化して設計しているため,低電圧動作時のエネルギー効率が従来型のDVFSプロセッサより高くなる.CPUコア間でオンチップメモリを共有することで,面積効率を向上させるとともにCPUコアの切替に掛かるオーバヘッドを抑止させる.さらに,組込みリアルタイムシステムへの応用を想定して,マルチパフオーマンスプロセッサの動作構成を切り替えて電力を管理する機能を提案する.電力管理機能をTOPPERS/ASPカーネル上に実装し,実チップ測定に基づいて評価した結果を報告する.

    CiNii Books

    researchmap

  38. 排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装

    高瀬英希, 李景洙, 石原亨

    研究報告システムLSI設計技術(SLDM)   Vol. 2014 ( 15 ) page: 1 - 6   2014.3

     More details

    Language:Japanese  

    高性能 CPU コアと省電力 CPU コアを排他的かつ動的に切り替えて動作するマルチパフォーマンスプロセッサのテストチップを,65 nmの商用プロセステクノロジを用いて試作した.各 CPU コアはそれぞれの電源電圧に最適化して設計しているため,低電圧動作時のエネルギー効率が従来型の DVFS プロセッサより高くなる.CPU コア間でオンチップメモリを共有することで,面積効率を向上させるとともに CPU コアの切替に掛かるオーバヘッドを抑止させる.さらに,組込みリアルタイムシステムへの応用を想定して,マルチパフォーマンスプロセッサの動作構成を切り替えて電力を管理する機能を提案する.電力管理機能を TOPPERS/ASP カーネル上に実装し,実チップ測定に基づいて評価した結果を報告する.

    CiNii Books

    researchmap

  39. Evaluation of Charge Scheduling on a Multi-Banked Supercapacitor Architecture for Energy Harvesting Embedded Systems

      Vol. 2014 ( 22 ) page: 1 - 6   2014.3

     More details

    Language:English  

    CiNii Books

    researchmap

  40. C-12-44 Maximizing Energy Efficiency of LSI Circuits by Simultaneous Tuning of Supply Voltage and Back Bias

    Takeshita Toshihiro, Nishizawa Shinichi, Mahfuzul Islam A.K.M., Ishihara Tohru, Onodera Hidetoshi

    Proceedings of the IEICE General Conference   Vol. 2014 ( 2 ) page: 108   2014.3

     More details

    Language:Japanese   Publishing type:Research paper, summary (national, other academic conference)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    CiNii Books

    researchmap

  41. Analysis and Comparison of XOR Cell Structures for Low Voltage Circuit Design Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013)     page: 703 - 708   2013

     More details

    Language:English   Publisher:IEEE  

    The performance of standard cells has a strong impact on the performance of a circuit synthesized with the cells. Although a complementary CMOS logic is usually used in the standard cells, it is known that a pass transistor logic can improve the performance of a circuit with a smaller area in some cases. We evaluate different types of XOR cells in different voltage conditions. Results show that the dual pass transistor XOR has a better performance than the complementary CMOS XOR in 0.6V operation, while the complementary CMOS XOR has a better performance in 1.2 V operation. More specifically, the area and the power consumption of a benchmark circuit composed of the dual pass transistor XOR can be reduced by 24% and 35%, respectively, compared to those of the same circuit composed of the complementary CMOS XOR in 0.6V operation.

    DOI: 10.1109/ISQED.2013.6523687

    Web of Science

    researchmap

▼display all

Presentations 11

  1. Maximizing Energy-Efficiency of Dual-OS Platforms through DVFS Virtualization Invited International conference

    Tohru Ishihara

    International Forum on MPSoC for Software-Defined Hardware (MPSoC)  2022.6.23 

     More details

    Event date: 2022.6

    Language:English   Presentation type:Oral presentation (invited, special)  

    Venue:Les fermes de Marie, Megève, France   Country:France  

  2. Near-Threshold Cache Architecture for Ultra-Low Energy Computing Invited

    2019.7.11 

     More details

    Event date: 2019.7

    Language:English   Presentation type:Oral presentation (invited, special)  

    researchmap

  3. Minimum Energy Point Tracking Exploiting All-Digital On-Chip Sensors Invited

    Tohru Ishihara

    International Forum on MPSoC for Software-Defined Hardware  2018.7.30 

     More details

    Event date: 2018.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  4. Minimum Energy Point Tracking for Self-Powered IoT Processors Invited

    2017.7.3 

     More details

    Event date: 2017.7

    Language:English   Presentation type:Oral presentation (invited, special)  

    researchmap

  5. An Integrated Optical Parallel Adder: A First Step towards Light-Speed Data Path Operation Invited

    Tohru Ishihara

    International Forum on MPSoC for Software-Defined Hardware  2016.7.14 

     More details

    Event date: 2016.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  6. Practical Supply and Threshold Voltage Scaling for Energy Efficient Operation of Microprocessors Invited

    Tohru Ishihara

    International Forum on MPSoC for Software-Defined Hardware  2015.7.13 

     More details

    Event date: 2015.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  7. Near-Threshold Computing on Heterogeneous Multicore Architectures Invited

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore  2014.7.10 

     More details

    Event date: 2014.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  8. Power Management Techniques for Energy Harvesting Embedded Systems Invited

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore  2013.7.18 

     More details

    Event date: 2013.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  9. Loop Instruction Caching for Energy-Efficient Embedded Multitasking Systems Invited

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore  2012.7.11 

     More details

    Event date: 2012.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  10. Energy Characterization of Embedded Processors for Software Energy Optimization Invited

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore  2011.7.5 

     More details

    Event date: 2011.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  11. Real-Time Dynamic Voltage Hopping on MPSoCs Invited International conference

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore (MPSoC)  2009.8.5 

     More details

    Event date: 2009.8

    Language:English   Presentation type:Oral presentation (invited, special)  

    Venue:Savannah, Georgia, USA   Country:United States  

▼display all

KAKENHI (Grants-in-Aid for Scientific Research) 7

  1. 光と電子が密に融合する集積回路のアーキテクチャと設計技術

    Grant number:20H04155  2020.4 - 2023.3

    日本学術振興会  科学研究費助成事業 基盤研究(B)  基盤研究(B)

    石原 亨, 納富 雅也, 塩見 準, 増田 豊, 塩見 準, 納富 雅也, 増田 豊

      More details

    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\17550000 ( Direct Cost: \13500000 、 Indirect Cost:\4050000 )

    2000年以降のナノフォトニクス技術の急速な発展を背景に、光デバイスは数ミクロンのサイズまで超小型化され、光回路と電子回路を混載して集積することが可能となった。本課題は、光と電子が密に融合する光集積回路のアーキテクチャと設計技術を構築することにより、光集積回路における遅延-電力-面積のトレードオフ限界を明確にし、光集積回路の最適な構成を明らかにするものである。上記目的のために、下記の3項目に取り組む。1)回路設計段階で光集積回路の遅延、電力、面積を予測するモデルを構築する。2)光集積回路に対する設計最適化技術を構築する。3)光集積回路を非ノイマン型演算器に適用し最適化の効果を評価する。

    researchmap

  2. A Study on Optical Computer Design through Photonics and Electronics Co-Optimization

    Grant number:17K19975  2017.6 - 2020.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Research (Exploratory)  Grant-in-Aid for Challenging Research (Exploratory)

    Ishihara Tohru

      More details

    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\6370000 ( Direct Cost: \4900000 、 Indirect Cost:\1470000 )

    This project is focused on an in-network optical computing. We have developed several optical functional units such as parallel adders, parallel multipliers and optical neural networks. With the optical devices as circuit building blocks, the computational speed of the arithmetic functions is on the order of picosecond since the delay of the single optical device is less than one picosecond. This ultra-low-latency is the basic motivation of using the optical devices for the optical circuit synthesis. Several key techniques for reducing the power consumption of optical circuits have been also developed. With optoelectronic circuit simulation, we have demonstrated the light speed operation of the circuits.

    researchmap

  3. Research on computing infrastructure aimed at realizing an IoT society to come

    Grant number:17H01712  2017.4 - 2020.3

    Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (B)

    Ishihara Tohru

      More details

    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\18850000 ( Direct Cost: \14500000 、 Indirect Cost:\4350000 )

    We have developed a microprocessor and a power management algorithm running on operating systems, which always minimize the energy consumption of the microprocessor. The algorithm dynamically controls the supply voltage, threshold voltage and clock frequency of the microprocessor so that the energy consumption of the microprocessor is always minimized for a given operation condition which include ambient temperature and workload of the applications running on the microprocessor. We have developed microprocessor chips based on RISC-V, an open source microprocessor design and have confirmed that the microprocessor and the power management algorithm we have developed work effectively. More specifically, we run the power management algorithm on the microprocessor under different ambient temperature conditions using a thermostatic chamber and confirmed that the processor chip we have developed always operates with the minimum energy even in the different operating environments.

    researchmap

  4. LSI Design Method for Minimum Energy Operation

    Grant number:16H01713  2016.4 - 2020.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)  Grant-in-Aid for Scientific Research (A)

    Onodera Hidetoshi

      More details

    Authorship:Coinvestigator(s) 

    We have developed a method for deriving a set of supply voltage and threshold voltage that enables the circuit to operate at the minimum energy consumption under a wide range of operating conditions and a specified delay constraint. We experimentally confirmed using a fabricated 32-bit processor that the derived set of supply voltage and threshold voltage can operate the circuit with less than 5 % excess energy from the minimum energy consumption under a wide variety of delay constraints and operating conditions. We also developed a DLL-type body bias generator that generate P/N well-voltages independently so that the energy consumption becomes minimum, which was verified by fabricated test chips.

    researchmap

  5. A Study on on-chip memories suitable for near-threshold voltage operation

    Grant number:26540021  2014.4 - 2017.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research  Grant-in-Aid for Challenging Exploratory Research

    Ishihara Tohru

      More details

    Authorship:Principal investigator 

    Grant amount:\3640000 ( Direct Cost: \2800000 、 Indirect Cost:\840000 )

    We have developed on-chip memory subsystems running with very low supply voltages. It has a functionality to stably run with very low supply voltages down to 0.25V. We have designed memory circuits integrating our idea for saving the area and energy consumption, which demonstrated that the energy efficiency of our memory circuit is twice better than existing on-chip SRAMs. We also integrated the memory circuits on microprocessor chips. The processor chip well runs with less than 0.3V voltage supply. We have obtained several awards such as IPSJ Yamashita Memorial Award and IEEE SSCS Japan Chapter VDEC Design Award which are given for the achievements in this research project.

    researchmap

  6. A Study on Energy Harvesting Embedded Computers as a Social Infrastructure

    Grant number:26280013  2014.4 - 2017.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)  Grant-in-Aid for Scientific Research (B)

    Ishihara Tohru

      More details

    Authorship:Principal investigator 

    Grant amount:\16770000 ( Direct Cost: \12900000 、 Indirect Cost:\3870000 )

    We have developed a microprocessor system running with unstable power sources such as a photovoltaic power supply system. The microprocessor has a functionality to stably run with very low supply voltages down to 0.3V. We have fabricated several microprocessor chips integrating our idea for saving the energy dissipation, which demonstrated the energy efficiency of our idea integrated on the chip. We also developed a technique of tuning supply voltage and threshold voltage simultaneously, which minimizes the energy consumption per performance of the microprocessor. The voltage tuning technique works effectively on the microprocessor chips fabricated. We have obtained several awards such as IPSJ Yamashita Memorial Award and IEEE SOCC Best Paper Award which are given for the achievements in this research project.

    researchmap

  7. LSI design methodology that enables robust operation under the supply as low as threshold voltage by self-compensating performance variability

    Grant number:25280014  2013.4 - 2017.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)  Grant-in-Aid for Scientific Research (B)

    ONODERA Hidetoshi, NISHIZAWA Sinichi, Mahfuzul Islam A. K. M., NISHIZAWA Sinichi, Mahfuzul Islam A. K. M.

      More details

    Authorship:Coinvestigator(s) 

    Under low voltage operation, variability of circuit performance increases due to process variations, which may result in functional failure. In order to maintain robust operation under low supply voltage close to the threshold voltage of transistors, an on-chip monitor circuit for estimating process variations and a body-bias generator for compensating the estimated process variations have been developed. Analytical stability modeling for CMOS latches, which are known to be susceptible to process variations, has been developed and design guidelines for variation-tolerant latches have been derived. With those techniques, a circuit with stable operation under low supply voltage down to the threshold voltage of transistors can be realized.

    researchmap

▼display all

Industrial property rights 12

  1. 光乗算器および光乗算方法

    新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 北 翔太 , 高田 健太 , 石原 亨 , 小野寺秀俊 , 今井悠貴

     More details

    Date applied:2017.8

    Date announced:2019.3

    Patent/Registration no:特許6707752  Date registered:2020.5 

    Country of applicant:Domestic   Country of acquisition:Domestic

  2. 光論理回路

    新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 北 翔太 , 石原 亨

     More details

    Application no:2017-36318  Date applied:2017.2

    Date announced:2018.9

    Patent/Registration no:特許6699826  Date registered:2020.5 

  3. 光論理回路

    新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 石原 亨

     More details

    Date applied:2016.8

    Date announced:2018.3

    Patent/Registration no:特許6742584  Date registered:2020.7 

  4. 光乗算器および光乗算方法

    新家 昭彦, 納富 雅也, 野崎 謙悟, 北 翔太, 高田 健太, 石原 亨, 小野寺秀俊, 今井悠貴

     More details

    Applicant:日本電信電話株式会社, 国立大学法人京都大学

    Application no:特願2017-159095  Date applied:2017.8

    Announcement no:特開2019-40225  Date announced:2019.3

    Patent/Registration no:特許6707752  Date registered:2020.5  Date issued:2020.6

    researchmap

  5. 光演算器

    新家 昭彦, 納富 雅也, 野崎 謙悟, 北 翔太, 高田 健太, 石原 亨, 小野寺秀俊, 江川巧

     More details

    Applicant:日本電信電話株式会社, 国立大学法人京都大学

    Application no:特願2017-159096  Date applied:2017.8

    Announcement no:特開2019-39941  Date announced:2019.3

    researchmap

  6. 光論理回路

    新家 昭彦, 納富 雅也, 野崎 謙悟, 北 翔太, 石原 亨

     More details

    Applicant:日本電信電話株式会社, 国立大学法人京都大学

    Application no:特願2017-36318  Date applied:2017.2

    Announcement no:特開2018-141892  Date announced:2018.9

    Patent/Registration no:特許6699826  Date registered:2020.5  Date issued:2020.5

    researchmap

  7. Optical Logic Circuit

     More details

    Applicant:Nippon Telegraph and Telephone Corporation

    Application no:特願2016-168953  Date applied:2016.8

    Announcement no:特開2018-36455  Date announced:2018.3

    Patent/Registration no:特許6742584  Date registered:2020.7  Date issued:2020.8

    researchmap

  8. 光演算器

    新家昭彦, 納富雅也, 野崎謙悟, 倉持栄一, 石原亨

     More details

    Applicant:日本電信電話株式会社, 国立大学法人京都大学

    Application no:特願2016-136033  Date applied:2016.7

    Patent/Registration no:特許6468607  Date registered:2019.1  Date issued:2019.2

    researchmap

  9. 光論理回路および加算器

    新家 昭彦, 納富 雅也, 野崎 謙悟, 石原 亨, 井上弘士

     More details

    Applicant:日本電信電話株式会社, 国立大学法人京都大学

    Application no:特願2016-39778  Date applied:2016.3

    Announcement no:特開2017-158041  Date announced:2017.9

    Patent/Registration no:特許6536959  Date registered:2019.6  Date issued:2019.7

    researchmap

  10. 消費電力評価装置、電力係数作成システム、消費電力評価方法及び電力係数作成方法

    神山 剛, 宮沢 祐光, 石原 亨, 久住 憲嗣, 金田 裕介, 奥平 拓見

     More details

    Patent/Registration no:特許5429746  Date issued:2013.12

    researchmap

  11. 消費電力分析システムおよびアプリケーション開発ツール

    小西 哲平, 神山 剛, 大久保 信三, 稲村 浩, 石原 亨, 久住 憲嗣, 部谷 修平

     More details

    Patent/Registration no:特許5787259  Date issued:2015.8

    researchmap

  12. プロセッサ設計を特徴付けるための方法、装置、論理プログラム及びシステム

    石原 亨, ファルザン ファラー

     More details

    Patent/Registration no:特許5298444  Date issued:2013.6

    researchmap

▼display all

 

Teaching Experience (Off-campus) 1

  1. SoC design methodology

    2020.10 - 2021.2 Kyoto University)

     More details

    Level:Postgraduate  Country:Japan

 

Media Coverage 2

  1. 光ニューラルネットワークに関する解説と研究記事が日経エレクトロニクスに掲載 Newspaper, magazine

    日経BP社  日経エレクトロニクス  日経エレクトロニクス2021年3月号 pp.35-38  2021.3

     More details

    Author:Other 

  2. 光の伝搬でAI処理を行う光ニューラルネットワークの解説と研究記事が日経クロステックに掲載 Internet

    日経BP社  日経クロステック  https://xtech.nikkei.com/atcl/nxt/column/18/01558/00007/  2021.2

     More details

    Author:Other 

Academic Activities 5

  1. 電子情報通信学会 『Special Section on VLSI Design and CAD Algorithms』編集委員会 編集委員

    Role(s):Planning, management, etc., Peer review

    2020.4

     More details

    Type:Scientific advice/Review 

  2. IEEE Symposium on Low-Power and High-Speed Chips and Systems組織委員会 副委員長 International contribution

    Role(s):Planning, management, etc., Panel moderator, session chair, etc.

    2020.4

     More details

    Type:Competition, symposium, etc. 

  3. 電子情報通信学会回路とシステム研究専門委員会委員

    Role(s):Planning, management, etc.

    2020.4

     More details

    Type:Academic society, research group, etc. 

  4. Asia and South Pacific Design Automation Conference, Steering Committee Secretary International contribution

    Role(s):Planning, management, etc.

    2020.4

     More details

    Type:Competition, symposium, etc. 

  5. 電子情報通信学会 『Special Section on Circuit and Systems』編集委員会 編集委員

    Role(s):Planning, management, etc., Peer review

    2019.7 - 2020.9

     More details

    Type:Scientific advice/Review