Updated on 2022/03/30

写真a

 
ISHIHARA Tohru
 
Organization
Graduate School of Informatics Department of Computing and Software Systems 2 Professor
Graduate School
Graduate School of Informatics
Undergraduate School
School of Informatics Department of Computer Science
Title
Professor
Contact information
メールアドレス
External link

Degree 1

  1. Doctor of engineering ( 2000.3   Kyushu University ) 

Research Interests 1

  1. Energy efficient computing, Low power design, Optical computing

Research Areas 2

  1. Informatics / Computer system  / Energy efficient computing

  2. Informatics / Computer system  / Energy Efficient Computing

Research History 9

  1. Nagoya University   Graduate School of Informatics Department of Computing and Software Systems 2   Professor

    2018.10

  2. Kyoto University   Graduate School of Informatics Department of Communications and Computer Engineering   Associate professor

    2011.4 - 2018.9

  3. Kyushu University   System LSI Research Center   Associate professor

    2007.4 - 2011.3

  4. Kyushu University   System LSI Research Center   Assistant Professor

    2005.8 - 2007.3

  5. Fujitsu Laboratories of America   Researcher

    2003.4 - 2005.7

  6. The University of Tokyo   Assistant

    2000.4 - 2003.4

  7. Japan Society for Promotion of Science

    1997.4 - 2000.3

  8. Nagoya University   Graduate School of Informatics   Professor

    2018.10

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    Country:Japan

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  9. Kyoto University   Graduate School of Informatics   Associate professor

    2011.4 - 2018.9

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    Country:Japan

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Education 2

  1. Kyushu University

    1995.4 - 2000.3

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    Country: Japan

  2. Kyushu University   Faculty of Engineering   Department of Computer Science and Communication Engineering

    1991.4 - 1995.3

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    Country: Japan

Professional Memberships 4

  1. 電子情報通信学会

    2008.5

  2. 情報処理学会

    1994

  3. ACM

  4. IEEE Computer Society

Awards 17

  1. 科学技術分野の文部科学大臣表彰 若手科学者賞

    2009.4   文部科学省   マイクロプロセッサの省電力化に関する研究

    石原 亨

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    Country:Japan

  2. 丸文研究奨励賞

    2007.3   丸文財団   ソフトウェア制御によるシステムLSIの低消費エネルギー化と微細化への対応

    石原 亨

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    Award type:Award from publisher, newspaper, foundation, etc. 

  3. 長尾真記念特別賞

    2010.5   情報処理学会   コンピュータシステムの省エネルギー化に関する研究

    石原 亨

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    Award type:Award from Japanese society, conference, symposium, etc. 

  4. 論文賞

    2013.5   電子情報通信学会   Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications

    Lovic Eric Gauthier, 石原 亨

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    Award type:Award from Japanese society, conference, symposium, etc. 

  5. Best Paper Award

    2021.6   IEICE   Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits

    Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, and Masaya Notomi

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    Award type:Honored in official journal of a scientific society, scientific journal  Country:Japan

  6. 論文賞

    2018.6   電子情報通信学会   Analytical Stability Modeling for CMOS Latches in Low Voltage Operation

    鎌苅竜也, 塩見準,石原亨,小野寺秀俊

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    Award type:Award from Japanese society, conference, symposium, etc. 

  7. 情報処理学会創立40周年記念論文賞

    2000.3   情報処理学会   DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ

    井上弘士,石原亨,甲斐康司,村上和彰

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    Country:Japan

  8. ISLPED 1st Most Cited Paper Award

    2015.9   IEEE/ACM International Symposium on Low Power Electronics and Design   Voltage scheduling problem for dynamically variable voltage processors

    Tohru Ishihara, Hiroto Yasuura

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    Award type:Award from international society, conference, symposium, etc. 

  9. IEEE SOCC Best Paper Award

    2016.9   IEEE International System-on-Chip Conference   Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing

    Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera

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    Award type:Award from international society, conference, symposium, etc. 

  10. Outstanding Paper Award

    2010.10   Workshop on Synthesis And System Integration of Mixed Information technologies   Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications

    Lovic Gauthier, Tohru Ishihara, Hideki, Hiroyuki,Hiroaki Takada

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    Award type:Award from international society, conference, symposium, etc. 

  11. Outstanding Paper Award

    2021.3   Workshop on Synthesis And System Integration of Mixed Information technologies   An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier

    L. Hou, Y. Masuda, T. Ishihara

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    Award type:Award from international society, conference, symposium, etc. 

  12. 情報処理学会システムLSI設計技術研究会優秀論文賞

    2016.9   情報処置学会システムLSI設計技術研究会  

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    Award type:Award from Japanese society, conference, symposium, etc. 

  13. 情報処理学会システムLSI設計技術研究会優秀論文賞

    2013.8   情報処置学会システムLSI設計技術研究会  

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    Award type:Award from Japanese society, conference, symposium, etc. 

  14. 情報処理学会システムLSI設計技術研究会優秀論文賞

    2002.7   情報処置学会システムLSI設計技術研究会  

  15. LSI IPデザイン・アワード MeP賞

    2008.4  

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    Award type:Award from publisher, newspaper, foundation, etc. 

  16. LSI IPデザイン・アワード IP優秀賞

    1999.5  

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    Award type:Award from publisher, newspaper, foundation, etc. 

  17. 情報処理学会九州支部奨励賞

    1998.5  

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Papers 137

  1. An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers Reviewed

    L. Hou, Y. Masuda, and T. Ishihara

    Proc. Asia and South Pacific Design Automation Conference (ASP-DAC)     page: 568 - 573   2022.1

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  2. Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing Reviewed

    T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara

    IEEE International Symposium on Quality Electronic Design     page: 300 - 306   2021.4

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  3. An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier Reviewed

    Lingxiao Hou,Yutaka Masuda,Tohru Ishihara

    Proc. of 23rd Workshop on Synthesis And System Integration of Mixed Information technologies     2021.3

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  4. Optical-electronic implementation of artificial neural network for ultrafast and accurate inference processing Reviewed

    Naoki Hattori,Yutaka Masuda,Tohru Ishihara,Jun Shiomi,Akihiko Shinya,Masaya Notomi

    Proc. of AI and Optical Data Sciences II. International Society for Optics and Photonics   Vol. 11703   page: 1E1 - 1E17   2021.3

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

    DOI: https://doi.org/10.1117/12.2577966

    DOI: https://doi.org/10.1117/12.2577966

  5. Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design Reviewed

    Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto

    Proc. of IEEE Design, Automation and Test in Europe Conference     2021.2

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    Language:English   Publishing type:Research paper (international conference proceedings)  

  6. A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits Invited International journal

    MATSUO Ryosuke, SHIOMI Jun, ISHIHARA Tohru, ONODERA Hidetoshi, SHINYA Akihiko, NOTOMI Masaya

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. advpub ( 0 ) page: 1546 - 1554   2021

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    Authorship:Lead author, Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high-speed nature. Our method divides the target logic function into multiple sub-functions with Optical-to-Electrical (OE) converters. Each sub-function has a smaller number of inputs than that of the original function, which enables to exponentially reduce the power dissipated by an optical logic circuit representing the sub-function. The proposed synthesis method can mitigate the OE converter delay overhead by parallelizing sub-functions. We apply the proposed synthesis method to the ISCAS'85 benchmark circuits. The power consumption of the conventional circuits based on the Binary Decision Diagram (BDD) is at least three orders of magnitude larger than that of the optical logic circuits synthesized by the proposed method. The proposed method reduces the power consumption to about 100 mW. The delay of almost all the circuits synthesized by the proposed method is kept less than four times the delay of the conventional BDD-based circuit.</p>

    DOI: 10.1587/transfun.2020kep0018

    Web of Science

    CiNii Research

  7. Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation Invited International journal

    HATTORI Naoki, SHIOMI Jun, MASUDA Yutaka, ISHIHARA Tohru, SHINYA Akihiko, NOTOMI Masaya

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. advpub ( 0 ) page: 1477 - 1487   2021

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    Authorship:Lead author, Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>With the rapid progress of the integrated nanophotonics technology, the optical neural network architecture has been widely investigated. Since the optical neural network can complete the inference processing just by propagating the optical signal in the network, it is expected more than one order of magnitude faster than the electronics-only implementation of artificial neural networks (ANN). In this paper, we first propose an optical vector-matrix multiplication (VMM) circuit using wavelength division multiplexing, which enables inference processing at the speed of light with ultra-wideband. This paper next proposes optoelectronic circuit implementation for batch normalization and activation function, which significantly improves the accuracy of the inference processing without sacrificing the speed performance. Finally, using a virtual environment for machine learning and an optoelectronic circuit simulator, we demonstrate the ultra-fast and accurate operation of the optical-electronic ANN circuit.</p>

    DOI: 10.1587/transfun.2020kep0016

    Web of Science

    CiNii Research

  8. Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling Invited International journal

    MASUDA Yutaka, NAGAYAMA Jun, CHENG TaiYu, ISHIHARA Tohru, MOMIYAMA Yoichi, HASHIMOTO Masanori

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. advpub ( 0 )   2021

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    Authorship:Lead author, Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>This work proposes a design methodology that saves the power dissipation under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of computational quality, e.g., Peak Signal-to-Noise Ratio (PSNR) in the image processing domain. Conventional CPI inherently cannot reduce the delay of intrinsic critical paths (CPs), which may significantly restrict the power saving effect. On the other hand, the proposed methodology tries to reduce both intrinsic and non-intrinsic CPs. Therefore, our design dramatically reduces the supply voltage and power dissipation while satisfying the quality constraint. Moreover, for reducing co-design exploration space, the proposed methodology utilizes the exclusiveness of the paths targeted by CPI and BWS, where CPI aims at reducing the minimum supply voltage of non-intrinsic CP, and BWS focuses on intrinsic CPs in arithmetic units. From this key exclusiveness, the proposed design splits the simultaneous optimization problem into three sub-problems; (1) the determination of bit-width reduction, (2) the timing optimization for non-intrinsic CPs, and (3) investigating the minimum supply voltage of the BWS and CPI-applied circuit under quality constraint, for reducing power dissipation. Thanks to the problem splitting, the proposed methodology can efficiently find quality-constrained minimum-power design. Evaluation results show that CPI and BWS are highly compatible, and they significantly enhance the efficacy of VOS. In a case study of a GPGPU processor, the proposed design saves the power dissipation by 42.7% with an image processing workload and by 51.2% with a neural network inference workload.</p>

    DOI: 10.1587/transfun.2021vlp0002

    CiNii Research

  9. Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing Invited Reviewed International journal

    Komori Takumi, Masuda Yutaka, Shiomi Jun, Ishihara Tohru

    PROCEEDINGS OF THE 2021 TWENTY SECOND INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2021)   Vol. 2021-April   page: 300 - 306   2021

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    Authorship:Lead author, Last author, Corresponding author   Language:Japanese   Publishing type:Research paper (international conference proceedings)   Publisher:Proceedings - International Symposium on Quality Electronic Design, ISQED  

    In the upcoming Internet of Things era, reducing energy consumption of embedded processors is highly desired. Minimum Energy Point Tracking (MEPT) is one of the most efficient methods to reduce both dynamic and static energy consumption of a processor. Previous works proposed a variety of MEPT methods over the past years. However, none of them incorporate their algorithms with practical real-time operating systems, although edge computing applications often require low energy task execution with guaranteeing real-time properties. The difficulty comes from the time complexity for identifying MEP and changing voltages, which often prevents real-time task scheduling. This paper proposes an approximated MEPT algorithm, which reduces the complexity of identifying MEP down to that of Dynamic Voltage and Frequency Scaling (DVFS). We also propose a task scheduling algorithm, which adjusts processor performance to the workload, and provides a soft real-time capability to the system. With these two methods, MEPT became a general task, and the operating system stochastically adjusts the average response time of a processor to be equal to a specified deadline. The experiments using a fabricated test chip show that the energy loss induced by the proposed algorithm is only 0.5% at most, and the algorithm does not sacrifice the fundamental real-time properties.

    DOI: 10.1109/ISQED51717.2021.9424343

    Web of Science

    Scopus

  10. Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing Invited Reviewed

    Yoshisue Kazuki, Masuda Yutaka, Ishihara Tohru

    2021 IEEE 27TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS)     2021

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    Authorship:Lead author, Last author, Corresponding author   Language:Japanese   Publishing type:Research paper (international conference proceedings)   Publisher:Proceedings - 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design, IOLTS 2021  

    Approximate computing (AC) has recently emerged as a promising approach to the energy-efficient design of digital systems. For realizing the practical AC design, we need to verify whether the designed circuit can operate correctly under various operating conditions. Namely, the verification needs to efficiently find fatal logic errors or timing errors that violate the constraint of computational quality. This paper proposes a novel dynamic verification methodology of the AC circuit. The key idea of the proposed methodology is to incorporate a quality assessment capability into the Coverage-based Grey-box Fuzzing (CGF). CGF is one of the most promising techniques in the research field of software security testing. By repeating (1) mutation of test patterns, (2) execution of the program under test (PUT), and (3) aggregation of coverage information and feedback to the next test pattern generation, CGF can explore the verification space quickly and automatically. On the other hand, CGF originally cannot consider the computational quality by itself. For overcoming this quality unawareness in CGF, the proposed methodology additionally embeds the Design Under Test (DUT) mechanisms into the calculation part of computational quality. Thanks to the integration of CGF and DUT mechanism, the proposed framework realizes the quality-aware feedback loop in CGF and thus quickly enhances the verification coverage for test patterns that violate the quality constraint. In this work, we quantitatively compared the verification coverage of the approximate arithmetic circuits between the proposed methodology and the random test. In a case study of an approximate multiply-accumulate (MAC) unit, we experimentally confirmed that the proposed methodology achieves the target coverage three times faster than the random test.

    DOI: 10.1109/IOLTS52814.2021.9486690

    Web of Science

    Scopus

  11. Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing Invited International journal

    KOMORI Takumi, MASUDA Yutaka, SHIOMI Jun, ISHIHARA Tohru

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. advpub ( 0 )   2021

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    Authorship:Lead author, Last author, Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    <p>In the upcoming Internet of Things era, reducing energy consumption of embedded processors is highly desired. Minimum Energy Point Tracking (MEPT) is one of the most efficient methods to reduce both dynamic and static energy consumption of a processor. Previous works proposed a variety of MEPT methods over the past years. However, none of them incorporate their algorithms with practical real-time operating systems, although edge computing applications often require low energy task execution with guaranteeing real-time properties. The difficulty comes from the time complexity for identifying an MEP and changing voltages, which often prevents real-time task scheduling. The conventional Dynamic Voltage and Frequency Scaling (DVFS) only scales the supply voltage. On the other hand, MEPT needs to adjust the body bias voltage in addition. This additional tuning knob makes MEPT much more complicated. This paper proposes an approximate MEPT algorithm, which reduces the complexity of identifying an MEP down to that of DVFS. The key idea is to linearly approximate the relationship between the processor frequency, supply voltage, and body bias voltage. Thanks to the approximation, optimal voltages for a specified clock frequency can be derived immediately. We also propose a task scheduling algorithm, which adjusts processor performance to the workload and then provides a soft real-time capability to the system. The operating system stochastically adjusts the average response time of the processor to be equal to a specified deadline. MEPT will be performed as a general task, and its overhead is considered in the calculation of the frequency. The experiments using a fabricated test chip and on-chip sensors show that the proposed algorithm is a maximum of 16 times more energy-efficient than DVFS. Also, the energy loss induced by the approximation is only 3% at most, and the algorithm does not sacrifice the fundamental real-time properties.</p>

    DOI: 10.1587/transfun.2021vlp0007

    CiNii Research

  12. An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. Reviewed

    Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

    Proc. of International Conference on Rebooting Computing     page: 95 - 101   2020.12

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    Language:English   Publishing type:Research paper (international conference proceedings)  

  13. Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling Reviewed

    Y. Masuda,J. Nagayama,T. Y. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto

    Proc. of International Workshop on Logic and Synthesis     page: 136 - 142   2020.7

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    Language:English   Publishing type:Research paper (international conference proceedings)  

  14. A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. Reviewed

    Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

    Proc. of IEEE Computer Society Annual Symposium on VLSI     page: 488 - 493   2020.7

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  15. Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. Reviewed International coauthorship

    Khyati Kiyawat,Yutaka Masuda,Jun Shiomi,Tohru Ishihara

    Proc. of IEEE Computer Society Annual Symposium on VLSI     page: 415 - 421   2020.7

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  16. On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing Reviewed

    Hongjie Xu,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E102-A ( 12 ) page: 1741 - 1750   2019.12

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    Authorship:Corresponding author  

  17. Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits Reviewed

    Ryosuke Matsuo,Jun Shiomi,Tohru Ishihara,Hidetoshi Onodera,Akihiko Shinya,Masaya Notomi

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E102-A ( 12 ) page: 1751 - 1759   2019.12

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    Authorship:Corresponding author  

  18. An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator Invited Reviewed

    Tohru Ishihara,Jun Shiomi,Naoki Hattori,Yutaka Masuda,Akihiko Shinya,Masaya Notomi

    Proc. of IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, Information, and Computing Systems     page: 15 - 21   2019

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    Authorship:Lead author, Last author, Corresponding author   Language:Japanese  

    DOI: 10.1109/PHOTONICS49561.2019.00008

    Web of Science

    Scopus

  19. Multi-Level Optimization for Large Fan-In Optical Logic Circuits using Integrated Nanophotonics Reviewed

    Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

    Proc. of IEEE International Conference on Rebooting Computing     2018.11

  20. A power minimization technique for arithmetic circuits by cell selection Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

    Proc. of Photonics-Optics Technology Oriented Networking, Information, and Computing Systems     2018.10

  21. Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization Reviewed

    Tatsuhiro Higuchi, Tohru Ishihara, Hidetoshi Onodera

    Proc. of the 31st IEEE International System-on-Chip Conference     2018.9

  22. Independent N-well and P-well Biasing for Minimum Leakage Energy Operation Reviewed

    Yosuke Okamura, Tohru Ishihara, Hidetoshi Onodera

    Proc. of the International Symposium on On-Line Testing and Robust System Design     page: 177 - 182   2018.7

  23. Maximizing Energy Efficiency of On-Chip Caches Exploiting Hybrid Memory Structure Reviewed

    Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. of the 28th International Symposium on Power and Timing Modeling, Optimization and Simulation     page: 237 - 242   2018.7

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    Authorship:Corresponding author  

  24. A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Invited Reviewed

    Kamakari Tatsuya, Shiomi Jun, Ishihara Tohru, Onodera Hidetoshi

    2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)     page: 691 - 696   2016

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    Authorship:Lead author, Last author, Corresponding author   Language:Japanese  

    Web of Science

  25. Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing Reviewed

    T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E105-A ( 3 ) page: 497 - 508   2022.3

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  26. Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling Reviewed

    Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E105-A ( 3 ) page: 509 - 517   2022.3

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    Language:English   Publishing type:Research paper (scientific journal)  

  27. A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits Reviewed

    R. Matsuo, J. Shiomi, T. Ishihara, H. Onodera, A. Shinya, and M. Notomi,

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E104-A ( 11 ) page: 1546 - 1554   2021.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  28. Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation Reviewed

    N. Hattori, J. Shiomi, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E104-A ( 11 ) page: 1477 - 1487   2021.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)  

  29. デュアルOSと仮想化DVFSによるミックスドクリティカルシステムの消費エネルギー最小化

    小森工,増田豊,石原亨

    情報処理学会DA シンポジウム論文集     page: 15 - 23   2021.9

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    Authorship:Corresponding author   Language:Japanese   Publishing type:Research paper (conference, symposium, etc.)  

  30. タスクのリアルタイム応答を保証する近似最小エネルギー点追跡 Reviewed

    小森工,増田豊,塩見準,石原亨

    第34 回回路とシステムワークショップ論文集     page: 178 - 183   2021.8

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    Authorship:Corresponding author   Language:Japanese   Publishing type:Research paper (conference, symposium, etc.)  

  31. Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing Reviewed

    K. Yoshisue, Y. Masuda, and T. Ishihara

    IEEE 27th International Symposium on On-Line Testing and Robust System Design     2021.6

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    Authorship:Last author   Language:English   Publishing type:Research paper (international conference proceedings)  

  32. An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier Reviewed

    Lingxiao Hou, Yutaka Masuda, Tohru Ishihara

    Proc. 23rd Workshop on Synthesis And System Integration of Mixed Information technologies     2021.3

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    Authorship:Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

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  33. ファジングを用いた近似コンピューティング回路の品質検証手法の一検討

    吉末和樹, 増田豊, 石原亨

    情報処理研究報告 2020-SLDM-192(27)     2020.11

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  34. クリティカルパス・アイソレーションとビット幅削減を用いた過電圧スケーリング向け省電力設計手法

    増田豊, 長山準, 鄭泰禹, 石原亨, 籾山陽一, 橋本昌宜

    情報処理学会 DAシンポジウム論文集     2020.9

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  35. 集積ナノフォトニクスに基づく光ニューラルネットワークを対象とした回路アーキテクチャ探索

    服部直樹, 増田豊, 石原亨, 塩見準, 新家昭彦, 納富雅也

    第33回 回路とシステムワークショップ論文集     page: 10 - 15   2020.8

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  36. A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. Reviewed

    Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

    Proc. IEEE Computer Society Annual Symposium on VLSI   Vol. 2020-July   page: 488 - 493   2020.7

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    DOI: 10.1109/ISVLSI49217.2020.000-9

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  37. 集積ナノフォトニクスに基づく近似並列乗算器を用いた低レイテンシ光ニューラルネットワーク

    塩見準, 石原亨, 小野寺秀俊, 新家昭彦, 納富雅也

    デザインガイア2019     page: 1 - 6   2019.11

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  38. 二分決定グラフに基づく光論理回路の消費電力削減手法

    松尾 亮祐, 塩見 準, 小野寺 秀俊, 石原 亨, 新家 昭彦, 納富 雅也

    DAシンポジウム2019     page: 87 - 92   2019.8

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  39. 波長分割多重を用いたブース法に基づく光並列乗算器の構成手法

    今井 悠貴, 塩見 準, 石原 亨, 小野寺 秀俊, 新家 昭彦, 納富 雅也

    DAシンポジウム2019     page: 81 - 86   2019.8

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  40. 広範囲な電圧領域で動作するフリップフロップのタイミング特性モデル

    内田 翼, 塩見 準, 石原 亨, 小野寺 秀俊

    DAシンポジウム2019     page: 172 - 177   2019.8

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  41. A Design Method of a Cell-Based Amplifier for Body Bias Generation Reviewed

    Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE Transactions on IEICE Transactions on Electronics   Vol. E102-C ( 7 ) page: 565 - 572   2019.7

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    DOI: 10.1587/transele.2018CTP0014

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  42. リアルタイム電圧最適化によるマルチタスク処理の消費エネルギー最小化

    塩見準, 石原亨, 小野寺秀俊

    ETNET2019     2019.3

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  43. BDD-based Synthesis of Optical Logic Circuits Exploting Wavelength Division Multiplexing Reviewed International journal

    Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

    Proceedings of the 24th Asia and South Pacific Design Automation Conference     2019.1

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    DOI: 10.1145/3287624.3287703

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  44. An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms towards Light Speed Data Processing Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

    2018 IEEE International Conference on Rebooting Computing (ICRC)     page: 62 - 67   2018.11

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    DOI: 10.1109/ICRC.2018.8638614

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  45. A Light Speed Optical Approximate Parallel Multiplier and Its Applications Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi

    PHOTONICS: Photonics-Optics Technology Oriented Networking, Information, and Computing Systems     2018.10

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  46. セルベース設計に適合した基板バイアス制御用増幅回路の設計手法

    小柳卓也, 塩見準, 石原亨, 小野寺秀俊

    DAシンポジウム2018     page: 172 - 177   2018.8

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  47. 波長多重を用いた二分決定グラフに基づく光論理回路の合成

    松尾亮祐, 塩見凖, 石原亨, 小野寺秀俊, 新家昭彦, 納富雅也

    DAシンポジウム2018     page: 51 - 56   2018.8

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  48. 集積ナノフォトニクスに基づく近似二進対数を用いた低レイテンシ光並列乗算器

    塩見凖, 石原亨, 小野寺秀俊, 新家昭彦, 納富雅也

    DAシンポジウム2018     page: 57 - 62   2018.8

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  49. 波長多重技術を活用したBDDに基づく光論理回路の設計手法

    松尾亮祐, 塩見準, 石原亨, 小野寺秀俊, 新家昭彦, 納富雅也

    DAシンポジウム2018     page: 51 - 56   2018.8

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  50. Minimum Energy Point Tracking with All-Digital On-Chip Sensors

    Jun Shiomi, Shu Hokimoto, Tohru Ishihara, and Hidetoshi Onodera

    ASP Journal of Low Power Electronics   Vol. 14 ( 2 )   2018.6

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  51. An Integrated Nanophotonic Parallel Adder Reviewed

    Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi

    ACM Journal on Emerging Technologies in Computing (JETC)     2018.6

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  52. 幅広い動作環境にわたってLSIの最大遅延特性を追跡するクリティカルパスレプリカの構成法

    福田 展和, 塩見 準, 石原 亨, 小野寺 秀俊

    第184回システムとLSIの設計技術研究発表会   Vol. 2018-SLDM-184 ( 5 ) page: 1 - 6   2018.5

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  53. A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator Reviewed

    Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

    Japanese Journal of Applied Physics   Vol. 57 ( 4S ) page: 04FF09-1 - 04FF09-6   2018.3

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  54. A Hybrid Caching System Using SRAM and Standard-Cell Memory for Energy-Efficient Near-Threshold Circuits Reviewed

    Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies     page: 56 - 61   2018.3

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  55. On–Chip Reconfigurable Monitor Circuit for Process Variation and Temperature Estimation Reviewed

    Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

    Proc. of Annual IEEE International Conference on Microelectronic Test Structures     page: 111 - 116   2018.3

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  56. Individual Voltage Scaling in Logic and Memory Circuits towards Runtime Energy Optimization in Processors Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)     page: 45 - 50   2018.3

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  57. Energy and Delay Optimized Multiplexer-tree Structure for Scaled Voltage Operation Reviewed

    Yuta Nagaoka, Tohru Ishihara, Hidetoshi Onodera

    Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies     page: 290 - 295   2018.3

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  58. An Integrated Optical Parallel Multiplier based on Nanophotonic Analog Adders and Optoelectronic AD Converters Reviewed

    Yuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

    Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies     page: 100 - 105   2018.3

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  59. All-Digital On-Chip Heterogeneous Sensors for Tracking the Minimum Energy Point of Processors Reviewed

    Shu Hokimoto, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Proc. of Annual IEEE International Conference on Microelectronic Test Structures     page: 128 - 133   2018.3

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  60. A temperature monitor circuit with small voltage sensitivity using a topology-reconfigurable ring oscillator Reviewed

    Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

    Japanese Journal of Applied Physics   Vol. 57 ( 4S ) page: 04FF09-1 - 04FF09-6   2018.3

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  61. A Method of Minimizing Latency in Large Fan-In Optical Logic Circuits with Integrated Nanophotonic Technologies Reviewed

    Takumi Egawa, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

    Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies     page: 320 - 325   2018.3

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  62. 選択的活性化によるスタンダードセルメモリの低消費エネルギー化

    塩見準, 石原亨, 小野寺秀俊

    電子情報通信学会技術研究報告   Vol. 117 ( 455 ) page: 211 - 216   2018.3

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  63. An optical parallel multiplier using nanophotonic analog adders and optoelectronic analog-to-digital converters Reviewed

    Yuuki Imai, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Shota Kita, Kengo Nozaki, Kenta Takata, Masaya Notomi

    Optics InfoBase Conference Papers   Vol. 2018   2018

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    We proposes an architecture of an optical parallel multiplier based on an optical analog addition. With optoelectronic circuit simulation, we show that the optical multiplier is more than three times faster than the CMOS multiplier.

    DOI: 10.1364/CLEO_AT.2018.JW2A.50

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  64. A minimum energy point tracking algorithm based on dynamic voltage scaling and adaptive body biasing Reviewed

    Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E100A ( 12 ) page: 2776 - 2784   2017.12

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    Scaling the supply voltage (VDD) and threshold voltage (VTH) for minimizing the energy consumption of processors dynamically is highly desired for applications such as wireless sensor network and Internet of Things (IoT). In this paper, we refer to the pair of VDD and VTH, which minimizes the energy consumption of the processor under a given operating condition, as a minimum energy point (MEP in short). Since the MEP is heavily dependent on an operating condition determined by a chip temperature, an activity factor, a process variation, and a performance required for the processor, it is not very easy to closely track the MEP at runtime. This paper proposes a simple but effective algorithm for dynamically tracking the MEP of a processor under a wide range of operating conditions. Gate-level simulation of a 32-bit RISC processor in a 65nm process demonstrates that the proposed algorithm tracks the MEP under a situation that operating condition widely vary.

    DOI: 10.1587/transfun.E100.A.2776

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  65. A necessary and sufficient condition of supply and threshold voltages in CMOS circuits for minimum energy point operation Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E100A ( 12 ) page: 2764 - 2775   2017.12

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    Scaling supply voltage (VDD) and threshold voltage (Vth) dynamically has a strong impact on energy efficiency of CMOS LSI circuits. Techniques for optimizing VDD and Vth simultaneously under dynamic workloads are thus widely investigated over the past 15 years. In this paper, we refer to the optimum pair of VDD and Vth, which minimizes the energy consumption of a circuit under a specific performance constraint, as a minimum energy point (MEP). Based on the simple transregional models of a CMOS circuit, this paper derives a simple necessary and sufficient condition for the MEP operation. The simple condition helps find the MEP of CMOS circuits. Measurement results using standard-cell based memories (SCMs) fabricated in a 65-nm process technology also validate the condition derived in this paper.

    DOI: 10.1587/transfun.E100.A.2764

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  66. クロスバ構造を利用した論理関数参照型ルックアップテーブルの回路構成法

    長岡 悠太, 石原 亨, 小野寺 秀俊

    DAシンポジウム2017     page: 216 - 221   2017.9

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  67. リークエネルギーを最小化するP/N基板電圧の設定手法

    岡村 陽介, 石原 亨, 小野寺 秀俊

    DAシンポジウム2017     page: 157 - 162   2017.9

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  68. アクセス頻度に応じた電圧調節によるオンチップメモリの消費エネルギー最小化

    塩見 準, 石原 亨, 小野寺 秀俊

    DAシンポジウム2017     page: 151 - 156   2017.8

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  69. ナノフォトニクスを用いた高速多入力論理演算の実現法

    江川 巧, 石原 亨, 小野寺 秀俊, 新家 昭彦, 北 翔太, 野崎 謙悟, 高田 健太, 納富 雅也

    DAシンポジウム2017     page: 45 - 50   2017.8

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  70. トポロジー可変リングオシレータを用いた電圧感度の小さい動作温度モニタ

    岸本 真, 石原 亨, 小野寺 秀俊

    DAシンポジウム2017     page: 85 - 90   2017.8

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  71. ビアスイッチFPGAの性能予測モデル

    樋口 達大, 石原 亨, 小野寺 秀俊

    DAシンポジウム2017     page: 9 - 14   2017.8

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  72. 集積ナノフォトニクスに基づく光アナログ加算手法と光並列乗算器への適用

    今井 悠貴, 石原 亨, 小野寺 秀俊, 新家 昭彦, 北 翔太, 野崎 謙悟, 高田 健太, 納富 雅也

    DAシンポジウム2017     page: 51 - 56   2017.8

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  73. 最小エネルギー動作点追跡アルゴリズムの実チップ評価

    保木本 修, 塩見 準, 石原 亨, 小野寺 秀俊

    DAシンポジウム2017     page: 145 - 150   2017.8

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  74. Area-Efficient Fully Digital Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Elsevier: Integration, the VLSI Journal   ( 有り )   2017.7

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  75. ロジック部およびメモリ部の独立電圧制御によるプロセッサの消費エネルギー最小化

    塩見準, 石原亨, 小野寺秀俊

    組込み技術とネットワークに関するワークショップ ETNET2017     2017.3

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  76. On-Chip Temperature and Process Variation Sensing using a Reconfigurable Ring Oscillator Reviewed

    Tadashi Kishimoto, Tohru Ishihara, Hidetoshi Onodera

    2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)     2017

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    This paper proposes a temperature monitoring scheme using a reconfigurable ring oscillator that has been proposed to estimate process variation. New circuit configurations, whose delay characteristics are sensitive to leakage current, are proposed to exploit the exponential dependence of the leakage current to temperature. Based on transistorlevel simulation assuming a 65 nm process technology, the oscillation frequency of the proposed circuit topology shows the temperature sensitivity of 5.0 %/degrees C at 20 degrees C and 2.9 %/ degrees C at 80 degrees C with low voltage sensitivity of 0.28 degrees C/10 mV at 25 degrees C and a supply voltage of 0.9 V. Estimation error of a 65 nm test chip ranges from -0.6 degrees C to 0.4 degrees C after two-point calibration. We also proposed a method to estimate the process variation and the temperature at the same time.

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  77. Analytical Stability Modeling for CMOS Latches in Low Voltage Operation Reviewed

    Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   Vol. E99A ( 12 ) page: 2463 - 2472   2016.12

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    In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.

    DOI: 10.1587/transfun.E99.A.2463

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  78. A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016)     page: 36 - 41   2016.10

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  79. Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications Reviewed

    Kei Yoshizawa, Tohru Ishihara, Hidetoshi Onodera

    The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016)     page: 329 - 334   2016.10

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  80. Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing Reviewed

    Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera

    IEEE International System-on-Chip Conference     page: 1 - 6   2016.9

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    DOI: 10.1109/SOCC.2016.7905420

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  81. プロセッサにおける電源電圧と基板電圧の同時調節によるエネルギー最小点追跡手法

    保木本修, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2016論文集     page: 169 - 174   2016.9

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  82. 組み込みアプリケーションにおける汎用プロセッサと専用ハードウェアの性能解析-消費エネルギーと処理速度および回路規模の定量的評価

    吉澤慶, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2016論文集     page: 103 - 108   2016.9

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  83. 広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ

    塩見準, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2016論文集     page: 91 - 96   2016.9

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  84. 回路トポロジー可変なリングオシレータを用いたプロセス変動量と動作温度の推定方法

    岸本真, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2016論文集     page: 175 - 180   2016.9

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  85. 低電圧動作に適したマルチプレクサツリー構成法

    長岡悠太, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2016論文集     page: 97 - 102   2016.9

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  86. CMOS LSIにおけるエネルギー最小点追跡のための電源電圧としきい値電圧の動的調節指針

    竹下俊宏, 塩見準, 石原亨, 小野寺秀俊

    組込み技術とネットワークに関するワークショップ ETNET2016     2016.3

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  87. サブスレッショルド領域で動作するラッチ回路の動作安定性解析 Invited

    鎌苅竜也, 塩見準, 石原亨, 小野寺秀俊

    電子情報通信会技術報告 VLD2015-131, pp. 117-117     2016.2

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  88. Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    PROCEEDINGS OF 2016 26TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS)     page: 44 - 49   2016

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    This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area-and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using 65-nm FDSOI technology shows that the proposed SCM achieves area efficiency of 5.9 mu m(2) per bit (592F(2) per bit), which is less than that of the state of the art SCMs. The results also show that the energy consumption is further improved when the supply voltage scaling and back-gate biasing techniques are applied to our SCM.

    DOI: 10.1109/PATMOS.2016.7833424

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  89. Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring Reviewed

    A. K. M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEEE JOURNAL OF SOLID-STATE CIRCUITS   Vol. 50 ( 11 ) page: 2475 - 2490   2015.11

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    Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 mu m(2) and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.

    DOI: 10.1109/JSSC.2015.2461598

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  90. 統計的タイミングモデルに基づくニアスレッショルド回路のゲートサイジング

    塩見準, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2015論文集     page: 137 - 142   2015.8

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  91. サブスレッショルド領域におけるラッチ回路の動作安定性モデル

    鎌苅竜也, 塩見準, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2015論文集     page: 187 - 192   2015.8

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  92. Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   Vol. E98A ( 7 ) page: 1455 - 1466   2015.7

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    Near-threshold computing has emerged as one of the most promising solutions for enabling highly energy efficient and high performance computation of microprocessors. This paper proposes architecture-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28 nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.

    DOI: 10.1587/transfun.E98.A.1455

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  93. Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IEICE Technical Report   Vol. VLD2014-172   page: 109 - 114   2015.3

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  94. A Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation using Cell-Based Structure Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 205-210     2015.3

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  95. Layout generator with flexible grid assignment for area efficient standard cell Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    IPSJ Transactions on System LSI Design Methodology   Vol. 8   page: 131 - 135   2015.2

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    This paper discusses a standard cell layout generator that can be used to generate a standard cell library optimized to a target application. It can generate an area efficient layout from a virtual-grid symbolic layout with the ability of flexible grid positioning that considers local design rules enforced in a scaled technology. The generator reduces the cost of library design and enables an optimization of each cell with detailed layout information that can be used to estimate the performance of the cell under design. A standard cell library has been generated for commercial 28-nm FDSOI CMOS process using the proposed layout generator, and used for circuit design. Correct operation of designed circuit is observed form fabricated chip test.

    DOI: 10.2197/ipsjtsldm.8.131

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  96. An Integrated Framework for Energy Optimization of Embedded Real-Time Applications Reviewed

    Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   Vol. E97A ( 12 ) page: 2477 - 2487   2014.12

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    This paper presents a framework for reducing the energy consumption of embedded real-time systems. We implemented the presented framework as both an optimization tookchain and an energy-aware real-time operating system. The framework consists of the integration of multiple techniques to optimize the energy consumption. The main idea behind our approach is to utilize trade-offs between the energy consumption and the performance of different processor configurations during task checkpoints, and to maintain memory allocation during task context switches. In our framework, a target application is statically analyzed at both intra-task and inter-task levels. Based on these analyzed results, run-time optimization is performed in response to the behavior of the application. A case study shows that our toolchain and real-time operating systems have achieved energy reduction while satisfying the real-time performance. The toolchain has also been successfully applied to a practical application.

    DOI: 10.1587/transfun.E97.A.2477

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  97. PLLの物理レイアウト自動生成を目指した設計手法

    釡江 典裕, 土谷 亮, 石原 亨, 小野寺 秀俊

    情報処理学会DAシンポジウム2014論文集     2014.8

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  98. ニアスレッショルド電圧動作に適した単一電源で動作する高歩留まりオン チップメモリの設計

    塩見準, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2014論文集     page: 103 - 108   2014.8

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  99. 電源電圧に応じてトランジスタサイズを最適化可能なセルライブラリの生成システム

    西澤真一, 石原 亨, 小野寺秀俊

    情報処理学会DAシンポジウム2014論文集     page: 97 - 102   2014.8

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  100. 製造ばらつきを考慮した極低電圧動作向けフリップフロップの設計手法

    鎌苅竜也, 西澤真一, 石原亨, 小野寺秀俊

    情報処理学会DAシンポジウム2014論文集     page: 91 - 96   2014.8

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  101. Variation Tolerant Design of D-Flip-Flops for Low Voltage Circuit Operation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)     page: 28 - 32   2014.3

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  102. DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems Reviewed

    K. Lee, T. Ishihara

    IEICE Transactions   Vol. 96-A ( 12 ) page: 2660-2667   2013.12

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  103. Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    IEICE Transactions   Vol. 96-A ( 12 ) page: 2499-2507   2013.12

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  104. DLIC: Decoded loop instructions caching for energy-aware embedded processors Reviewed International coauthorship International journal

    Ji Gu, Hui Guo, Tohru Ishihara

    Transactions on Embedded Computing Systems   Vol. 13 ( 1 ) - 英語   2013.8

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    With the explosive proliferation of embedded systems, especially through countless portable devices and wireless equipment used, embedded systems have become indispensable to the modern society and people's life. Those devices are often battery driven. Therefore, low energy consumption in embedded processors is important and becomes critical in step with the system complexity. The on-chip instruction cache (I-cache) is usually the most energy-consuming component on the processor chip due to its large size and frequent access operations. To reduce such energy consumption, the existing loop cache approaches use a tiny decoded cache to filter the I-cache access and instruction decode activity for repeated loop iterations. However, such designs are effective for small and simple loops, and only suitable for DSP kernel-like applications. They are not effectual for many embedded applications where complex loops are common. In this article, we propose a decoded loop instruction cache (DLIC) that is small, hence energy efficient, yet can capture most loops, including large nested ones with branch executions, so that a significant amount of I-cache accesses and instruction decoding can be eradicated. The experiments on a set of embedded benchmarks show that our proposed DLIC scheme can reduce energy consumption by up to 87% as compared to normal cache-only design. On average, 66% energy can be saved on instruction fetching and decoding, while at a performance overhead of only 1.4%. © 2013 ACM.

    DOI: 10.1145/2512464

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  105. ニアスレショルド電圧動作に適したスタンダードセルの駆動力集合の決定法

    近藤正大, 石原 亨, 小野寺秀俊

    DAシンポジウム2013     page: 21 - 26   2013.8

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  106. 電源電圧・閾値電圧・パイプライン段数の同時スケーリングによるプロセッサのエネルギー高効率化設計手法

    修 斉, 石原 亨, 小野寺秀俊

    DAシンポジウム2013     page: 145 - 150   2013.8

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  107. 低電圧動作に向けたXOR論理ゲートの構成法の検討

    西澤真一, 石原 亨, 小野寺秀俊

    DAシンポジウム2013     page: 9 - 14   2013.8

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  108. An Impact of Within-Die Variation on Supply Voltage Dependence of Path Delay Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    TAU workshop     2013.3

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  109. A Standard Cell Optimization Method for Near-Threshold Voltage Operations Invited Reviewed

    Kondo Masahiro, Nishizawa Shinichi, Ishihara Tohru, Onodera Hidetoshi

    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION   Vol. 7606   page: 32 - 41   2013

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  110. A standard cell optimization method for near-threshold voltage operations Reviewed

    Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   Vol. 7606   page: 32 - 41   2013

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    Near-threshold voltage operation is a well-known solution for drastically improving the energy efficiency of microprocessors fabricated with the latest process technologies. However, it is not well studied how the optimal gate size of standard cells changes when the supply voltage of the microprocessors gets closer to the threshold voltage. This paper first shows an experimental observation that the optimal gate size for nearthreshold voltage which is 0.6V in this work is far from the optimal gate size for the nominal supply voltage which is 1.2V in our target process technology. Based on this fact, the paper next presents our cell optimization flow which finds the optimal gate sizes of individual standard cells operating at the near-threshold voltage. The experimental results show that, when operating at the 0.6V condition, the energy consumptions of several benchmark circuits synthesized with our standard cells optimized for the 0.6V condition can be reduced by 31% at the best case and by 23% on average compared with those of the same circuits synthesized with the cells optimized for the nominal supply voltage. © Springer-Verlag Berlin Heidelberg 2013.

    DOI: 10.1007/978-3-642-36157-9_4

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  111. Processor energy characterization for compiler-assisted software energy reduction Reviewed

    L. Gauthier; T. Ishihara

    Journal of Electrical and Computer Engineering   - 英語   2012

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    DOI: 10.1155/2012/786943

  112. Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications Reviewed

    Lovic Gauthier, Tohru Ishihara

    IEICE Transactions   Vol. 94-A ( 12 ) page: 2597-2608   2011.12

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  113. RTOSのハードウェア化によるソフトウェアベースTCP/IP処理の高速化と低消費電力化 Reviewed

    丸山修孝;石原亨;安浦寛人

    電子情報通信学会論文誌 A   Vol. J94-A ( 9 ) page: 692 - 701   2011.9

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  114. Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies Reviewed

    Maziar Goudarzi, Tohru Ishihara, Hamid Noori

    Transactions on High-Performance Embedded Architectures and Compilers   Vol. 3   page: 275-299   2011

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    DOI: https://doi.org/10.1007/978-3-642-19448-1_15

  115. A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems Reviewed

    Tohru ISHIHARA

    IEICE Transactions   Vol. 93-A ( 12 ) page: 2533-2541   2010.12

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  116. SRAM leakage reduction by row/column redundancy under random within-die delay variation Reviewed

    M. Goudarzi; T. Ishihara

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems   Vol. 18 ( 12 ) page: 1660 - 1671   2010

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    DOI: 10.1109/TVLSI.2009.2026048

  117. Code and data placement for embedded processors with scratchpad and cache memories Reviewed

    Y. Ishitobi; T. Ishihara; H. Yasuura

    Journal of Signal Processing Systems   Vol. 60 ( 2 ) page: 211 - 224   2010

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    DOI: 10.1007/s11265-008-0306-3

  118. Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion Reviewed

    Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura

    IPSJ Transactions on System LSI Design Methodology   Vol. 2   page: 189-199   2009.2

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  119. An Optimization Technique for Low-Energy Embedded Memory Systems Reviewed

    Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura

    IPSJ Transactions on System LSI Design Methodology   Vol. 2   page: 239-249   2009.2

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  120. Way-Scaling to Reduce Power of Cache with Delay Variation Reviewed

    Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihara

    IEICE Transactions   Vol. 91-A ( 12 ) page: 3576-3584   2008.12

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  121. A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation Reviewed

    M. Goudarzi; T. Ishihara; H. Yasuura

    Microelectronics Journal   Vol. 39 ( 12 ) page: 1797 - 1808   2008.12

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    DOI: 10.1016/j.mejo.2008.02.002

  122. Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems Reviewed

    Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami

    IEICE Transactions   Vol. 91-C ( 4 ) page: 410-417   2008.4

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  123. Value-dependence of SRAM leakage in deca-nanometer technologies Reviewed

    Maziar Goudarzi, Tohru Ishihara

    IEICE Electronic Express   Vol. 5   page: 23-28   2008.1

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  124. Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems Reviewed

    Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami

    IEICE Transactions   Vol. 90-C ( 10 ) page: 1983-1991   2007.10

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  125. オンチップメモリの高速化と低スタンバイリークを実現する閾値電圧の静的スケジューリング手法 Reviewed

    石原亨, 浅田邦博

    情報処理学会論文誌   Vol. 44 ( 5 ) page: 1284-1291   2003.5

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  126. A System Level Optimization Technique for Application Specific Low Power Memories Reviewed

    Tohru ISHIHARA, Kunihiro ASADA

    IEICE Transactions   Vol. E84-A ( 11 ) page: 2755-2761   2001.11

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  127. 入力信号パターンを考慮した低電力算術演算回路の設計手法 Reviewed

    室山真徳,石原亨,兵頭章彦,安浦寛人

    情報処理学会論文誌   Vol. 42 ( 4 ) page: 1007-1015   2001.4

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  128. DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ Reviewed

    井上弘士, 石原亨,甲斐康司,村上和彰

    情報処理学会論文誌   Vol. 42 ( 3 ) page: 419-431   2001.3

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  129. Software energy reduction techniques for variable-voltage processors Reviewed

    T. Okuma; H. Yasuura; T. Ishihara

    IEEE Design and Test of Computers   Vol. 18 ( 2 ) page: 31 - 41   2001

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    DOI: 10.1109/54.914613

  130. 可変電源電圧プロセッサに対するリアルタイムタスクスケジューリング手法 Reviewed

    大隈孝憲, 石原亨, 安浦寛人

    電子情報通信学会論文誌   Vol. J83-C ( 6 ) page: 454-462   2000.6

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  131. System LSI design methods for low power LSIs Invited Reviewed

    H. Yasuura; T. Ishihara

    IEICE Transactions on Electronics   Vol. E83-C ( 2 ) page: 143 - 152   2000

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  132. Flexible system LSI for embedded systems and its optimization techniques Reviewed

    A. Inoue; T. Ishihara; H. Yasuura

    Design Automation for Embedded Systems   Vol. 5 ( 2 ) page: 179 - 205   2000

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    DOI: 10.1023/A:1008974723452

  133. A high-performance and low-power cache architecture with speculative way-selection Reviewed

    K. Indue; T. Ishihara; K. Kai; K. Murakami

    IEICE Transactions on Electronics   Vol. E83-C ( 2 ) page: 186 - 193   2000

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  134. A memory power optimization technique for application specific embedded systems Reviewed

    T. Ishihara; H. Yasuura

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E82-A ( 11 ) page: 2366 - 2374   1999

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  135. Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches Reviewed

    H. Tomiyama; T. Ishihara; A. Inoue; H. Yasuura

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E81-A ( 12 ) page: 2621 - 2629   1998

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  136. Programmable power management architecture for power reduction Reviewed

    T. Ishihara; H. Yasuura

    IEICE Transactions on Electronics   Vol. E81-C ( 9 ) page: 1473 - 1479   1998

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  137. Experimental analysis of power estimation models of CMOS VLSI circuits Reviewed

    T. Ishihara

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol. E80-A ( 3 ) page: 480 - 486   1997

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▼display all

Books 4

  1. ウェスト&ハリスCMOS VLSI回路設計

    Weste Neil H. E., Harris David Money, 廣瀬 哲也, 高橋 篤司, 天野 英晴, 山岡 雅直, 高宮 真, 宇佐美 公良, 池田 誠, 小林 和淑, 戸川 望, 小松 聡, 平本 俊郎, 佐藤 高史, 石原 亨, 黒川 敦, 三堂 哲寿

    丸善出版  2014  ( ISBN:9784621087213

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    CiNii Books

  2. Multi-Processor System-on-Chip 1 Reviewed International journal

    Jun Shiomi;Tohru Ishihara( Role: Contributor ,  Chapter 10: Minimum Energy Computing via Supply and Threshold Voltage Scaling)

    Wiley – ISTE  2021.3 

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    Total pages:28   Responsible for pages:227-254   Language:English Book type:Scholarly book

  3. CMOS VLSI Design - A Circuits and Systems Perspective 4th ed.

    Tohru Ishihara( Role: Joint translator ,  Chapter 5 Power)

    2014.1 

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  4. Essential Issues in SOC Design: Designing Complex Systems-on-Chip

    H. Yasuura, T. Ishihara, M. Muroyama( Role: Contributor ,  Chapter 6: Energy Management Techniques for SOC Design)

    Springer  2006.10 

MISC 22

  1. Towards the realization of low-latency and high-efficiency photoelectronic accelerators

    北翔太, 北翔太, 野崎謙悟, 野崎謙悟, 小野真証, 小野真証, 高田健太, 高田健太, 新家昭彦, 新家昭彦, CONG G., 山本宗継, 前神有里子, 大野守史, 山田浩治, 川上哲志, 井上弘士, 石原亨, 納富雅也, 納富雅也

    応用物理学会春季学術講演会講演予稿集(CD-ROM)   Vol. 67th   2020

  2. A Process-Scheduler-Based Approach to Minimum Energy Point Tracking

    Shengyu Liu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    DA Symposium 2019 (poster)     2019.8

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  3. <高校生のページ>人に寄り添う安全安心なコンピュータの実現を目指して

    石原 亨, 小野寺 秀俊

    Cue : 京都大学電気関係教室技術情報誌   Vol. 38   page: 58 - 62   2017.9

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  4. IoT向け超省エネルギープロセッサのための完全ディジタル型メモリ

    塩見 準, 石原 亨, 小野寺 秀俊

    LSIとシステムのワークショップ2017 (poster)     2017.5

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  5. A Voltage-Scalable Fully Digital On-Chip Memory for Ultra-Low-Power IoT Processors

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    University Booth at Design, Automation and Test in Europe (DATE) 2017 (poster)     2017.3

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  6. Low-Power IoT Processor Integrating Voltage-Scalable Fully Digital Memories

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    IoT Ten-Cent System-on-Chip Challenge at Design, Automation and Test in Europe (DATE) 2017 (poster)     2017.3

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  7. CMOS LSIにおけるエネルギー最小点追跡のための電源電圧としきい値電圧の動的調節指針 (ディペンダブルコンピューティング) -- (組込み技術とネットワークに関するワークショップETNET2016)

    竹下 俊宏, 塩見 準, 石原 亨, 小野寺 秀俊

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 115 ( 519 ) page: 187 - 192   2016.3

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  8. Guidelines for Effective and Simplified Dynamic Supply and Threshold Voltage Scaling Reviewed

    Toshinori Takeshita, Tohru Ishihara, Hidetoshi Onodera

    2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)     page: 1 - 4   2016

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper, summary (international conference)   Publisher:IEEE  

    Scaling supply voltage (V-DD) and threshold voltage (V-TH) dynamically has a strong impact on energy efficiency of CMOS LSI circuits. Techniques for optimizing V-DD and V-TH simultaneously under dynamic workloads are thus widely investigated over the past 15 years. This paper for the first time shows the following properties for dynamic voltage scaling; i) if V-DD is sufficiently higher than V-TH, tuning only V-DD with a fixed V-TH maximizes the energy efficiency, ii) if V-DD is nearthreshold, tuning only V-TH with a fixed V-DD maximizes the energy efficiency, and iii) if V-DD is subthreshold, tuning V-DD and/or V-TH for a dynamic workload does not improve energy efficiency. These properties help simplify the procedure of voltage scaling, and reduce the cost for providing different V(DD)s and V(TH)s.

    DOI: 10.1109/VLSI-DAT.2016.7482546

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  9. A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region Reviewed

    Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)     page: 691 - 696   2016

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    A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchronous LSI circuits. In this paper, an analytical stability model for a cross-coupled inverter operating in a sub-threshold voltage region is proposed. The proposed model analytically shows that the minimum operating voltage of the cross-coupled inverter distributes normally in a high-sigma region if the distribution of the threshold voltage is Gaussian. The minimum supply voltage at which the yield of the cross-coupled inverter becomes a specific value can be accurately derived by a simple calculation using the model. Monte-Carlo simulation assuming a commercial 28 nm process technology demonstrates the accuracy and the validity of the proposed model. Based on the model, this paper shows strategies for variation tolerant memory design.

    DOI: 10.1109/ASPDAC.2016.7428092

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  10. Slew- and Variability-Aware Logical Effort for Near-Threshold Circuit Design Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    International Workshop on Variability Modeling and Charactorization     2015.11

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  11. Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits

      Vol. 2015 ( 20 ) page: 1 - 6   2015.1

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    Simultaneous supply and threshold voltage tuning has a strong impact on the energy reduction of LSI circuits. Therefore, techniques for optimizing the supply and threshold voltages simultaneously under a specific delay constraint of LSI circuits are widely investigated over the past 15 years. However, only a few previous work investigate techniques for effectively reducing the energy consumption of circuits with a small number of different supply and threshold voltages. In this paper, we present several interesting properties which are very useful for reducing the energy consumption of circuits with a small number of different supply and threshold voltages. Those properties are numerically explained using analytical delay and energy consumption models. Through circuit simulation using a commercial 28nm process technology model, we demonstrate that the properties presented in this paper hold for actual LSI circuits.

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  12. An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015)     page: 23 - 28   2015

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    Language:English   Publishing type:Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher:IEEE  

    On-chip memory is one of the most energy consuming components in processors. Aggressive voltage scaling to the sub-/near-threshold region is thus applied even to the memory used for ultra-low power applications. In this paper, an energy-efficient cell-based memory structure which is stably working with a near-threshold operating voltage is proposed. The circuit simulation using a commercial 28-nm technology shows that the energy consumption for the readout operation in our memory proposed here is up to 61% less than the energy dissipated in an existing cell-based memory and a conventional SRAM circuit. The simulation using a foundry provided Monte Carlo package also shows that the 3 sigma worst case read-access time of our cell-based memory is comparable to that of the SRAM circuit.

    DOI: 10.1109/ISQED.2015.7085372

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  13. Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation Reviewed

    Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

    PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015)     page: 181 - 185   2015

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    Language:English   Publishing type:Article, review, commentary, editorial, etc. (international conference proceedings)   Publisher:IEEE  

    Energy-efficiency has become the driving force of today's LSI industry. In order to achieve minimum energy operation of LSI, we propose a built-in body biasing technique which generates independent body biases for nMOSFET and pMOSFET separately. We design and fabricate an application circuit integrated with our proposed built-in body bias generation (BBG) circuits in a 65-nm process. The application circuit consists of AES cipher and decipher modules. The BBG does not require an external supply and it is compatible with a dynamic voltage scaling scheme for the application circuit. Cell-based design of the BBG circuit has been applied to facilitate automatic place and route. Both of the AES and the BBG circuits have been routed simultaneously to reduce design and area overhead. In post-silicon, supply voltage and body bias voltages are selected to achieve the minimum energy consumption for a target frequency. From the measurement results, more than 20% of energy reduction is achieved compared with adjusting supply voltage alone.

    DOI: 10.1109/ISQED.2015.7085421

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  14. An Impact of Process Variation on Supply Voltage Dependence of Logic Path Delay Variation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    2015 International symposium on VLSI Design, Automation and Test (VLSI-DAT)     page: 1 - 4   2015

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    Dynamic Voltage and Frequency Scaling ( DVFS) technique requires accurate observation of critical path delay for robust operation under aggressive supply voltage scaling. Logic paths contain several types of logic gates and path delay have voltage dependences because different logic gates have different voltage dependences. However, it is not well investigated that how the voltage dependence of the path delay changes induced by process variation. This paper describes the effect of the process variation on the voltage dependence of path delay. Ring Oscillator circuits fabricated in 65-nm CMOS process are used for the evaluation and analysis of the process variation dependence of the voltage delay curves.

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  15. Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation Reviewed

    Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    International System on Chip Conference     page: 42 - 47   2014.11

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    This paper describes the process variation tolerant design of DFFs for low voltage operation. Within-die random variation have a strong impact on the delay performance of DFF, especially at low supply voltage. Since a large number of DFFs are used in a VLSI chip, operation failure or timing failure of DFFs cause operation failure of a VLSI chip. This paper analyzes operation failures of DFFs using Monte-Carlo analysis and evaluate the effect of within-die variation on the delay performance of DFFs. In order to mitigate the effect of within-die variation, variation tolerant DFF design is proposed. The post layout simulation result shows increasing the sizes of the input clocked inverter and the clock driver reduce the operational failure of DFFs.

    DOI: 10.1109/SOCC.2014.6948897

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  16. Variation-aware Flip-Flop energy optimization for ultra low voltage operation Reviewed

    Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

    International System on Chip Conference     page: 17 - 22   2014.11

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    This paper presents an energy optimization method for a Flip-Flop (FF) circuit in a presence of manufacturing process variation. The optimal FF circuit can be obtained by simultaneously scaling the supply voltage and the transistor size with achieving a specific high yield of the circuit. Lowering the supply voltage is one of the most effective approaches for decreasing the energy consumption of the circuit. However, the increased variation in nano scale semiconductor devices causes a malfunction of FFs especially for the very low voltage operation. Therefore, it is a challenging goal for the nano scale FFs to achieve the high yield and extremely low energy consumption simultaneously. This paper proposes an approximation method for accurately estimating a minimum possible operating voltage (VDDmin) of FFs with a small number of Monte-Carlo trials. After that, for a given FF, we find a set of optimal supply voltage and the transistor sizes, which minimizes the energy consumption of the FF with achieving the specific high-sigma yield (e.g., 5σ yield). Post layout Monte-Carlo simulation results obtained using a commercial 28 nm process technology model demonstrate that the energy consumption of a FF optimized with our approach can be reduced by 17% at the best case with achieving 5σ yield.

    DOI: 10.1109/SOCC.2014.6948893

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  17. A Lognormal Timing Model and Design Guidelines for Near-Threshold Circuits Reviewed

    Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

    International Workshop on Variability Modeling and Characterization (VMC)     2014.11

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  18. 排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装 (ディペンダブルコンピューティング 組込み技術とネットワークに関するワークショップETNET2014)

    高瀬 英希, 李 景洙, 石原 亨

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 113 ( 498 ) page: 85 - 90   2014.3

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    Language:Japanese   Publisher:一般社団法人電子情報通信学会  

    高性能CPUコアと省電力CPUコアを排他的かつ動的に切り替えて動作するマルチパフォーマンスプロセッサのテストチップを,65nmの商用プロセステクノロジを用いて試作した.各CPUコアはそれぞれの電源電圧に最適化して設計しているため,低電圧動作時のエネルギー効率が従来型のDVFSプロセッサより高くなる.CPUコア間でオンチップメモリを共有することで,面積効率を向上させるとともにCPUコアの切替に掛かるオーバヘッドを抑止させる.さらに,組込みリアルタイムシステムへの応用を想定して,マルチパフオーマンスプロセッサの動作構成を切り替えて電力を管理する機能を提案する.電力管理機能をTOPPERS/ASPカーネル上に実装し,実チップ測定に基づいて評価した結果を報告する.

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  19. Evaluation of Charge Scheduling on a Multi-Banked Supercapacitor Architecture for Energy Harvesting Embedded Systems

    LEE KYUNGSOO, ISHIHARA TOHRU

    IEICE technical report. Dependable computing   Vol. 113 ( 498 ) page: 127 - 132   2014.3

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    Language:English   Publisher:The Institute of Electronics, Information and Communication Engineers  

    Energy-harvesting devices attract wide interest as replacements for primary batteries in low power embedded systems. This claims new energy efficient management techniques for the energy-harvesting systems dislike the previous management techniques. This paper evaluates a charge scheduling technique on a multi-banked supercapacitor architecture as well as a simple maximum point tracking algorithm (MPPT). We design an energy harvesting board with a multi-banked supercapacitor architecture, and operate it in a real system. The evaluation focuses on the energy loss reduction by the charge scheduling technique in the power supplier of the system.

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  20. 排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装 (コンピュータシステム 組込み技術とネットワークに関するワークショップETNET2014)

    高瀬 英希, 李 景洙, 石原 亨

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報   Vol. 113 ( 497 ) page: 85 - 90   2014.3

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    Language:Japanese   Publisher:一般社団法人電子情報通信学会  

    高性能CPUコアと省電力CPUコアを排他的かつ動的に切り替えて動作するマルチパフォーマンスプロセッサのテストチップを,65nmの商用プロセステクノロジを用いて試作した.各CPUコアはそれぞれの電源電圧に最適化して設計しているため,低電圧動作時のエネルギー効率が従来型のDVFSプロセッサより高くなる.CPUコア間でオンチップメモリを共有することで,面積効率を向上させるとともにCPUコアの切替に掛かるオーバヘッドを抑止させる.さらに,組込みリアルタイムシステムへの応用を想定して,マルチパフオーマンスプロセッサの動作構成を切り替えて電力を管理する機能を提案する.電力管理機能をTOPPERS/ASPカーネル上に実装し,実チップ測定に基づいて評価した結果を報告する.

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  21. 排他動作する非均質マルチコアプロセッサとそのリアルタイムOSの実装

    高瀬英希, 李景洙, 石原亨

    研究報告システムLSI設計技術(SLDM)   Vol. 2014 ( 15 ) page: 1 - 6   2014.3

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    高性能 CPU コアと省電力 CPU コアを排他的かつ動的に切り替えて動作するマルチパフォーマンスプロセッサのテストチップを,65 nmの商用プロセステクノロジを用いて試作した.各 CPU コアはそれぞれの電源電圧に最適化して設計しているため,低電圧動作時のエネルギー効率が従来型の DVFS プロセッサより高くなる.CPU コア間でオンチップメモリを共有することで,面積効率を向上させるとともに CPU コアの切替に掛かるオーバヘッドを抑止させる.さらに,組込みリアルタイムシステムへの応用を想定して,マルチパフォーマンスプロセッサの動作構成を切り替えて電力を管理する機能を提案する.電力管理機能を TOPPERS/ASP カーネル上に実装し,実チップ測定に基づいて評価した結果を報告する.

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  22. 動作状況に応じた電源電圧と基板バイアスの同時調節によるLSIのエネルギー効率最大化

    竹下俊宏, 西澤真一, Islam A.K.M. Mahfuzul, 石原 亨, 小野寺秀俊

    電子情報通信学会 2014年総合大会     2014.3

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Presentations 10

  1. Near-Threshold Cache Architecture for Ultra-Low Energy Computing Invited

    Tohru Ishihara

    International Forum on MPSoC for Software-Defined Hardware  2019.7.11 

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    Event date: 2019.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  2. Minimum Energy Point Tracking Exploiting All-Digital On-Chip Sensors Invited

    Tohru Ishihara

    International Forum on MPSoC for Software-Defined Hardware  2018.7.30 

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    Event date: 2018.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  3. An Integrated Optical Parallel Adder: A First Step towards Light-Speed Data Path Operation Invited International conference

    Tohru Ishihara

    International Forum on MPSoC for Software-defined Hardware  2016.7.14 

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    Event date: 2017.7

    Language:English   Presentation type:Oral presentation (invited, special)  

    Country:France  

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  4. Minimum Energy Point Tracking for Self-Power IoT Processors Invited

    2017.7.3 

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    Event date: 2017.7

    Language:English   Presentation type:Oral presentation (invited, special)  

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  5. An Integrated Optical Parallel Adder: A First Step towards Light-Speed Data Path Operation Invited

    Tohru Ishihara

    International Forum on MPSoC for Software-Defined Hardware  2016.7.14 

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    Event date: 2016.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  6. Practical Supply and Threshold Voltage Scaling for Energy Efficient Operation of Microprocessors Invited

    Tohru Ishihara

    International Forum on MPSoC for Software-Defined Hardware  2015.7.13 

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    Event date: 2015.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  7. Near-Threshold Computing on Heterogeneous Multicore Architectures Invited

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore  2014.7.10 

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    Event date: 2014.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  8. Power Management Techniques for Energy Harvesting Embedded Systems Invited

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore  2013.7.18 

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    Event date: 2013.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  9. Loop Instruction Caching for Energy-Efficient Embedded Multitasking Systems Invited

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore  2012.7.11 

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    Event date: 2012.7

    Language:English   Presentation type:Oral presentation (invited, special)  

  10. Energy Characterization of Embedded Processors for Software Energy Optimization Invited

    Tohru Ishihara

    International Forum on Embedded MPSoC and Multicore  2011.7.5 

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    Event date: 2011.7

    Language:English   Presentation type:Oral presentation (invited, special)  

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KAKENHI (Grants-in-Aid for Scientific Research) 7

  1. 光と電子が密に融合する集積回路のアーキテクチャと設計技術

    Grant number:20H04155  2020.4 - 2023.3

    日本学術振興会  科学研究費助成事業 基盤研究(B)  基盤研究(B)

    石原 亨, 納富 雅也, 塩見 準, 増田 豊, 納富 雅也, 塩見 準, 増田 豊

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\17550000 ( Direct Cost: \13500000 、 Indirect Cost:\4050000 )

    2000年以降のナノフォトニクス技術の急速な発展を背景に、光デバイスは数ミクロンのサイズまで超小型化され、光回路と電子回路を混載して集積することが可能となった。本課題は、光と電子が密に融合する光集積回路のアーキテクチャと設計技術を構築することにより、光集積回路における遅延-電力-面積のトレードオフ限界を明確にし、光集積回路の最適な構成を明らかにするものである。上記目的のために、下記の3項目に取り組む。1)回路設計段階で光集積回路の遅延、電力、面積を予測するモデルを構築する。2)光集積回路に対する設計最適化技術を構築する。3)光集積回路を非ノイマン型演算器に適用し最適化の効果を評価する。

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  2. A Study on Optical Computer Design through Photonics and Electronics Co-Optimization

    Grant number:17K19975  2017.6 - 2020.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Research (Exploratory)  Grant-in-Aid for Challenging Research (Exploratory)

    Ishihara Tohru

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\6370000 ( Direct Cost: \4900000 、 Indirect Cost:\1470000 )

    This project is focused on an in-network optical computing. We have developed several optical functional units such as parallel adders, parallel multipliers and optical neural networks. With the optical devices as circuit building blocks, the computational speed of the arithmetic functions is on the order of picosecond since the delay of the single optical device is less than one picosecond. This ultra-low-latency is the basic motivation of using the optical devices for the optical circuit synthesis. Several key techniques for reducing the power consumption of optical circuits have been also developed. With optoelectronic circuit simulation, we have demonstrated the light speed operation of the circuits.

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  3. Research on computing infrastructure aimed at realizing an IoT society to come

    Grant number:17H01712  2017.4 - 2020.3

    Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (B)

    Ishihara Tohru

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    Authorship:Principal investigator  Grant type:Competitive

    Grant amount:\18850000 ( Direct Cost: \14500000 、 Indirect Cost:\4350000 )

    We have developed a microprocessor and a power management algorithm running on operating systems, which always minimize the energy consumption of the microprocessor. The algorithm dynamically controls the supply voltage, threshold voltage and clock frequency of the microprocessor so that the energy consumption of the microprocessor is always minimized for a given operation condition which include ambient temperature and workload of the applications running on the microprocessor. We have developed microprocessor chips based on RISC-V, an open source microprocessor design and have confirmed that the microprocessor and the power management algorithm we have developed work effectively. More specifically, we run the power management algorithm on the microprocessor under different ambient temperature conditions using a thermostatic chamber and confirmed that the processor chip we have developed always operates with the minimum energy even in the different operating environments.

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  4. LSI Design Method for Minimum Energy Operation

    Grant number:16H01713  2016.4 - 2020.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)  Grant-in-Aid for Scientific Research (A)

    Onodera Hidetoshi

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    Authorship:Coinvestigator(s) 

    We have developed a method for deriving a set of supply voltage and threshold voltage that enables the circuit to operate at the minimum energy consumption under a wide range of operating conditions and a specified delay constraint. We experimentally confirmed using a fabricated 32-bit processor that the derived set of supply voltage and threshold voltage can operate the circuit with less than 5 % excess energy from the minimum energy consumption under a wide variety of delay constraints and operating conditions. We also developed a DLL-type body bias generator that generate P/N well-voltages independently so that the energy consumption becomes minimum, which was verified by fabricated test chips.

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  5. A Study on on-chip memories suitable for near-threshold voltage operation

    Grant number:26540021  2014.4 - 2017.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research  Grant-in-Aid for Challenging Exploratory Research

    Ishihara Tohru

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    Authorship:Principal investigator 

    Grant amount:\3640000 ( Direct Cost: \2800000 、 Indirect Cost:\840000 )

    We have developed on-chip memory subsystems running with very low supply voltages. It has a functionality to stably run with very low supply voltages down to 0.25V. We have designed memory circuits integrating our idea for saving the area and energy consumption, which demonstrated that the energy efficiency of our memory circuit is twice better than existing on-chip SRAMs. We also integrated the memory circuits on microprocessor chips. The processor chip well runs with less than 0.3V voltage supply. We have obtained several awards such as IPSJ Yamashita Memorial Award and IEEE SSCS Japan Chapter VDEC Design Award which are given for the achievements in this research project.

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  6. A Study on Energy Harvesting Embedded Computers as a Social Infrastructure

    Grant number:26280013  2014.4 - 2017.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)  Grant-in-Aid for Scientific Research (B)

    Ishihara Tohru

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    Authorship:Principal investigator 

    Grant amount:\16770000 ( Direct Cost: \12900000 、 Indirect Cost:\3870000 )

    We have developed a microprocessor system running with unstable power sources such as a photovoltaic power supply system. The microprocessor has a functionality to stably run with very low supply voltages down to 0.3V. We have fabricated several microprocessor chips integrating our idea for saving the energy dissipation, which demonstrated the energy efficiency of our idea integrated on the chip. We also developed a technique of tuning supply voltage and threshold voltage simultaneously, which minimizes the energy consumption per performance of the microprocessor. The voltage tuning technique works effectively on the microprocessor chips fabricated. We have obtained several awards such as IPSJ Yamashita Memorial Award and IEEE SOCC Best Paper Award which are given for the achievements in this research project.

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  7. LSI design methodology that enables robust operation under the supply as low as threshold voltage by self-compensating performance variability

    Grant number:25280014  2013.4 - 2017.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)  Grant-in-Aid for Scientific Research (B)

    ONODERA Hidetoshi, NISHIZAWA Sinichi, Mahfuzul Islam A. K. M., NISHIZAWA Sinichi, Mahfuzul Islam A. K. M.

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    Authorship:Coinvestigator(s) 

    Under low voltage operation, variability of circuit performance increases due to process variations, which may result in functional failure. In order to maintain robust operation under low supply voltage close to the threshold voltage of transistors, an on-chip monitor circuit for estimating process variations and a body-bias generator for compensating the estimated process variations have been developed. Analytical stability modeling for CMOS latches, which are known to be susceptible to process variations, has been developed and design guidelines for variation-tolerant latches have been derived. With those techniques, a circuit with stable operation under low supply voltage down to the threshold voltage of transistors can be realized.

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Industrial property rights 8

  1. 光乗算器および光乗算方法

    新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 北 翔太 , 高田 健太 , 石原 亨 , 小野寺秀俊 , 今井悠貴

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    Date applied:2017.8

    Date announced:2019.3

    Patent/Registration no:特許6707752  Date registered:2020.5 

    Country of applicant:Domestic   Country of acquisition:Domestic

  2. 光論理回路

    新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 北 翔太 , 石原 亨

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    Application no:2017-36318  Date applied:2017.2

    Date announced:2018.9

    Patent/Registration no:特許6699826  Date registered:2020.5 

  3. 光論理回路

    新家 昭彦 , 納富 雅也 , 野崎 謙悟 , 石原 亨

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    Date applied:2016.8

    Date announced:2018.3

    Patent/Registration no:特許6742584  Date registered:2020.7 

  4. 光乗算器および光乗算方法

    新家 昭彦, 納富 雅也, 野崎 謙悟, 北 翔太, 高田 健太, 石原 亨, 小野寺秀俊, 今井悠貴

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    Applicant:日本電信電話株式会社, 国立大学法人京都大学

    Application no:特願2017-159095  Date applied:2017.8

    Announcement no:特開2019-40225  Date announced:2019.3

    Patent/Registration no:特許6707752  Date registered:2020.5  Date issued:2020.6

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  5. 光論理回路および加算器

    新家 昭彦, 納富 雅也, 野崎 謙悟, 石原 亨, 井上弘士

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    Applicant:日本電信電話株式会社, 国立大学法人京都大学

    Application no:特願2016-39778  Date applied:2016.3

    Announcement no:特開2017-158041  Date announced:2017.9

    Patent/Registration no:特許6536959  Date registered:2019.6  Date issued:2019.7

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  6. 消費電力分析システムおよびアプリケーション開発ツール

    小西 哲平, 神山 剛, 大久保 信三, 稲村 浩, 石原 亨, 久住 憲嗣, 部谷 修平

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    Patent/Registration no:特許5787259  Date issued:2015.8

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  7. プロセッサ設計を特徴付けるための方法、装置、論理プログラム及びシステム

    石原 亨, ファルザン ファラー

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    Patent/Registration no:特許5298444  Date issued:2013.6

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  8. 消費電力評価装置、電力係数作成システム、消費電力評価方法及び電力係数作成方法

    神山 剛, 宮沢 祐光, 石原 亨, 久住 憲嗣, 金田 裕介, 奥平 拓見

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    Patent/Registration no:特許5429746  Date issued:2013.12

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Teaching Experience (Off-campus) 1

  1. SoC design methodology

    2020.10 - 2021.2 Kyoto University)

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    Level:Postgraduate  Country:Japan

 

Media Coverage 2

  1. 光ニューラルネットワークに関する解説と研究記事が日経エレクトロニクスに掲載 Newspaper, magazine

    日経BP社  日経エレクトロニクス  日経エレクトロニクス2021年3月号 pp.35-38  2021.3

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    Author:Other 

  2. 光の伝搬でAI処理を行う光ニューラルネットワークの解説と研究記事が日経クロステックに掲載 Internet

    日経BP社  日経クロステック  https://xtech.nikkei.com/atcl/nxt/column/18/01558/00007/  2021.2

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    Author:Other 

Academic Activities 5

  1. 電子情報通信学会 『Special Section on VLSI Design and CAD Algorithms』編集委員会 編集委員

    Role(s):Planning, management, etc., Peer review

    2020.4

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    Type:Scientific advice/Review 

  2. IEEE Symposium on Low-Power and High-Speed Chips and Systems組織委員会 副委員長 International contribution

    Role(s):Planning, management, etc., Panel moderator, session chair, etc.

    2020.4

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    Type:Competition, symposium, etc. 

  3. 電子情報通信学会回路とシステム研究専門委員会委員

    Role(s):Planning, management, etc.

    2020.4

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    Type:Academic society, research group, etc. 

  4. Asia and South Pacific Design Automation Conference, Steering Committee Secretary International contribution

    Role(s):Planning, management, etc.

    2020.4

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    Type:Competition, symposium, etc. 

  5. 電子情報通信学会 『Special Section on Circuit and Systems』編集委員会 編集委員

    Role(s):Planning, management, etc., Peer review

    2019.7 - 2020.9

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    Type:Scientific advice/Review