Faculty Profiles - EDAHIRO Masato

Papers - EDAHIRO Masato

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HexaCam: An FPGA-based Multi-view Camera System Reviewed

A. Monrroy, M. Hirabayashi, S. Kato, M. Edahiro, T. Miyoshi and S. Funada

Proceedings of the 3rd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'15) page： 48-53 2015.8

Real-Time Visualization of Moving Objects Reviewed

P. Ortal, S. Kato, and M. Edahiro

Proceedings of the 3rd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'15) page： 60-65 2015.8

Automatic synthesis of inter-heterogeneous-processor communication for programmable system-on-chip Reviewed

Y. Ando, Y. Ishida, S. Honda, H. Takada and M. Edahiro

IPSJ Transactions on System LSI Design Methodology Vol. 8 page： 95-99 2015.8

Automatic synthesis of inter-heterogeneous-processor communication for programmable system-on-chip Reviewed

Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro

IPSJ Transactions on System LSI Design Methodology Vol. 8 page： 95-99 2015.8

階層構造を持つメニーコアアーキテクチャへのタスクマッピング Reviewed

油谷創, 枝廣正人

情報処理学会論文誌 Vol. ５６ ( ８ ) page： 1568-1581 2015.8

階層構造を持つメニーコアアーキテクチャへのタスクマッピング Reviewed

油谷創, 枝廣正人

情報処理学会論文誌 Vol. 56 ( 8 ) page： 1568-1581 2015.8

Design Space Exploration of Control System with Hardware-implemented Interrupt Handler Reviewed

Y. Ando, S. Honda, H. Takada, M. Edahiro

Proceedings of International Conference on Information and Communication Technology for Embedded Systems (IC-ICTES) page： 1-6 2015.3

Implementation and evaluation of AES/ADPCM on STP and FPGA with High-level Synthesis Reviewed

Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro

Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page： 415-420 2015.3

Profiler for Control System in System Level Design Reviewed

T-D Miaw, Y. Ando, S. Honda, H. Takada, M. Edahiro

Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page： 46-51 2015.3

Implementation and evaluation of AES/ADPCM on STP and FPGA with High-level Synthesis Reviewed

Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro

Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page： 415-420 2015.3

Profiler for Control System in System Level Design Reviewed

T-D Miaw, Y. Ando, S. Honda, H. Takada, M. Edahiro

Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page： 46-51 2015.3

Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip Reviewed

Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro

Proceeding. of IEEE International Conference on VLSI Systems, Architecture, Technology and Applications page： 1-6 2015.1

Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip Reviewed

Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro

Proceeding. of IEEE International Conference on VLSI Systems, Architecture, Technology and Applications page： 1-6 2015.1

Design Space Exploration of Control System with Hardware-implemented Interrupt Handler Reviewed

Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro

2015 6TH INTERNATIONAL CONFERENCE OF INFORMATION AND COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS (IC-ICTES) page： 1-6 2015

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

In this paper, we propose a system-level design tool for control systems that enables the development of hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. Case studies on a motor control system show that the proposed method enables the designer to explore design space of control system, reduces the processor load and improves the latency of the interrupt processing.

Web of Science

HexaCam: An FPGA-based Multi-view Camera System Reviewed

Abraham Monrroy, Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Takefumi Miyoshi, Satoshi Funada

2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015 page： 48 - 53 2015

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

Accurate perception information of the surroundings is a desirable feature in any cyber-physical system for autonomous robotics. Besides, providing a cost-wise solution to this need, is also useful for developing other kinds of applications such as mapping, decision-making, self-localization, among others. In this work, we present and benchmark a cost-effective camera device with six image sensors attached to a custom built FPGA board. The perception information is delivered on the host side, thanks to a HOG based object detector executed on the GPU. Our conclusion is that the low cost prototype is able to acquire and extract the perception data in 9.41 frames per second.

DOI： 10.1109/CPSNA.2015.18

Web of Science

Real-Time Visualization of Moving Objects Reviewed

Patricia Ortal, Shinpei Kato, Masato Edahiro

2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015 page： 60 - 65 2015

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

The development of visualization tools that help us assimilate the information that surrounds us is essential in business environments and most research fields. Data visualization is a powerful tool that lets us recognize patterns and trends easily, allows us to extract sensible information faster, stimulates hypothesis generation, and helps us make effective decisions. This paper describes the design and implementation of a web application that displays moving objects in real-time using Google Maps. This web application was done as part of an integrated system that addresses issues related to the automated driver assistance field. Moreover, this work seeks to be a reference framework that will provide visual support for researchers in the area of mobility looking to analyze moving object trajectories, evaluate prediction models, or explain their results.

DOI： 10.1109/CPSNA.2015.20

Web of Science

制御システムのマルチ・メニーコアプロセッサ実装 Invited

枝廣正人

計測と制御 Vol. 53 ( 12 ) page： 1111-1116 2014.12

制御システムのマルチ・メニーコアプロセッサ実装 Invited

枝廣正人

計測と制御 Vol. 53 ( 12 ) page： 1111-1116 2014.12

Exploring the Problem of GPU Programming for Data-Intensive Applications: A Case Study of Multiple Expectation Maximization for Motif Elicitation Reviewed

Y. Kitsukawa, M. Hirabayashi, S. Kato, and M. Edahiro

Proceedings of the fifth symposium on Information and Communication Technology (SoICT2014) page： 256-262 2014.12

Exploring the problem of GPU programming for data-intensive applications: A case study of multiple expectation maximization for motif elicitation Reviewed

Yuki Kitsukawa, Manato Hirabayashi, Shinpei Kato, Masato Edahiro

ACM International Conference Proceeding Series Vol. 04-05- page： 256 - 262 2014.12

Language：English Publishing type：Research paper (international conference proceedings) Publisher：Association for Computing Machinery

Recently General-Purpose Computing on Graphics Processing Units (GPGPU) has been used to reduce the processing time of various applications, but the degree of acceleration by the Graphical Processing Unit (GPU) depends on the application. This study focuses on data analysis as an application example of GPGPU, specifically, the design and implementation of GPGPU computation libraries for data-intensive workloads. The effects of efficient memory allocation and high-speed read-only memories on the execution time are evaluated. In addition to employing a single GPU, the scalability using multiple GPUs is also evaluated. Compared to a Central Processing Unit (CPU) alone, the memory allocation method reduces the execution time for memory copies by approximately 60% when a GPU is used, while utilizing read-only memories results in an approximately 20% reduction in the overall program execution time. Moreover, expanding the number of GPUs from one to four reduces the execution time by approximately 10%.

DOI： 10.1145/2676585.2676616

Scopus

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Papers - EDAHIRO Masato