School of Informatics Department of Computer Science

Updated on 2025/03/26
Personnel Information
Research Activity
Education Activity
Contribution to Society
Updated on 2025/03/26
Optimization of Software on Multi- / Many-Core Processors
Block-Level Automatic Parallelization from Simulink Models
Nagoya University Graduate School of Informatics Department of Computing and Software Systems 2 Professor
2017.4
大同大学情報システム学科 非常勤講師
2014.4
More details
Country:Japan
Daido University
2014.4
早稲田大学グリーン・コンピューティング・システム研究開発センター 客員教授、非常勤講師
2011.4
More details
Country:Japan
早稲田大学グリーン・コンピューティング・システム研究開発センター 客員教授、非常勤講師
2011.4
早稲田大学グリーン・コンピューティング・システム研究開発センター 客員教授、非常勤講師
2011.4
Nagoya University Graduate School of Information Science Department of Information Engineering Integrated Circuits and Systems Professor
2011.4 - 2017.3
東京大学大学院情報理工学系研究科 客員教授、非常勤講師
2008.4
More details
Country:Japan
The University of Tokyo The Graduate School of Information Science and Technology
2008.4
中央大学大学院理工学研究科 非常勤講師
2003.4
More details
Country:Japan
中央大学大学院理工学研究科 非常勤講師
2003.4
中央大学大学院理工学研究科 非常勤講師
2003.4
NEC Corporation (Research Fellow)
1985.4 - 2011.3
More details
Country:Japan
NEC Corporation (Research Fellow)
1985.4 - 2011.3
Princeton University School of Engineering and Applied Science Department of Computer Science
1991.9 - 1999.6
More details
Country: United States
Princeton University School of Engineering and Applied Science Department of Computer Science
1991.9 - 1999.6
More details
Country: United States
Princeton University Department of Computer Science
- 1993.1
More details
Country: United States
Princeton University Department of Computer Science
- 1993.1
More details
Country: United States
The University of Tokyo Graduate School, Division of Engineering Mathematical Engineering
1983.4 - 1985.3
More details
Country: Japan
The University of Tokyo Graduate School, Division of Engineering Mathematical Engineering
1983.4 - 1985.3
More details
Country: Japan
The University of Tokyo Faculty of Engineering
1979.4 - 1983.3
More details
Country: Japan
The University of Tokyo Faculty of Engineering
1979.4 - 1983.3
More details
Country: Japan
IEEE
日本オペレーションズリサーチ学会
情報処理学会
電子情報通信学会
IEEE
電子情報通信学会
日本オペレーションズリサーチ学会
情報処理学会
組込みマルチコアコンソーシアム 会長
2014.10
JEITA マイクロプロセッサ専門委員会 委員
2009.4
情報処理学会論文誌「組込みシステム工学」特集号編集委員会 編集委員
2012.2
情報処理学会組込みシステム研究会 運営委員
2016.4
組込みマルチコアコンソーシアム 会長
2014.10
情報処理学会論文誌「組込みシステム工学」特集号編集委員会 編集委員長
2014.2 - 2016.8
情報処理学会論文誌「組込みシステム工学」特集号編集委員会 編集委員長
2014.2 - 2016.8
情報処理学会組込みシステム研究会 主査
2013.4 - 2016.3
情報処理学会組込みシステム研究会 主査
2013.4 - 2016.3
マルチ・メニーコアプラットフォーム標準化委員会 (NEDO PJ) 委員長
2013.1 - 2015.2
マルチ・メニーコアプラットフォーム標準化委員会 (NEDO PJ) 委員長
2013.1 - 2015.2
情報処理学会組込みシステムシンポジウム 実行委員長
2012.4 - 2013.3
情報処理学会組込みシステムシンポジウム 実行委員長
2012.4 - 2013.3
情報処理学会論文誌「組込みシステム工学」特集号編集委員会 編集委員
2012.2
情報処理学会組込みシステムシンポジウム プログラム委員長
2010.4 - 2011.3
情報処理学会組込みシステムシンポジウム プログラム委員長
2010.4 - 2011.3
JEITA マイクロプロセッサ専門委員会 委員
2009.4
ISE President Best Paper Award
2018.11 International SoC Design Conference Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors
Zhaoqian Zhong and Masato Edahiro
More details
Country:Korea, Republic of
ISE President Best Paper Award
2018.11 International SoC Design Conference Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors
Zhaoqian Zhong, Masato Edahiro
More details
Country:Korea, Republic of
Best Conference Paper Award
2017.11 IEEE Robotics and Automation Society Localization Based on Multiple Visual-Metric Maps
Sujiwo Muhammad Adi Puspo, Eijiro Takeuchi, Luis Yoichi Morales Saiki, Naoki Akai, Yoshiki Ninomiya, and Masato Edahiro
More details
Country:United States
第7回TOPPERS活用アイデア・アプリケーション開発コンテスト 銅賞
2017.11 TOPPERSプロジェクト モデルベース開発におけるクロスレイヤ設計手法のマルチコア上モータ制御実装への適用
竹松慎弥,鍾 兆前,井上雅理,横山静香,小島流石(大阪大),近藤真己(NECソリューションイノベータ),中本幸一(兵庫県立大),安積卓也(大阪大),道木慎二,本田晋也, 枝廣正人
More details
Country:Japan
Best Conference Paper Award
2017.11 IEEE Robotics and Automation Society Localization Based on Multiple Visual-Metric Maps
Sujiwo Muhammad Adi Puspo, Eijiro Takeuchi, Luis Yoichi Morales Saiki, Naoki Akai, Yoshiki Ninomiya, Masato Edahiro
More details
Country:United States
第7回TOPPERS活用アイデア・アプリケーション開発コンテスト 銅賞
2017.11 TOPPERSプロジェクト モデルベース開発におけるクロスレイヤ設計手法のマルチコア上モータ制御実装への適用
竹松慎弥, 鍾 兆前, 井上雅理, 横山静香, 小島流石, 近藤真己, ECソリューションイノベータ, 中本幸一, 安積卓也, 道木慎二, 本田晋也, 枝廣正人
More details
Country:Japan
2017年度コンピュータサイエンス領域奨励賞
2017.8 情報処理学会 モデルベース開発におけるマルチ・メニーコア向け自動並列化
鍾 兆前,枝廣正人
More details
Country:Japan
優秀ポスター賞
2017.8 情報処理学会組込みシステム研究会 モデルベース開発におけるクロスレイヤ設計手法のマルチコア上モータ制御実装への適用
竹松慎弥,鍾 兆前,井上雅理,横山静香,小島流石(大阪大),近藤真己(NECソリューションイノベータ),中本幸一(兵庫県立大),安積卓也(大阪大),道木慎二,本田晋也, 枝廣正人
More details
Country:Japan
2017年度コンピュータサイエンス領域奨励賞
2017.8 情報処理学会 モデルベース開発におけるマルチ・メニーコア向け自動並列化
鍾 兆前, 枝廣正人
More details
Country:Japan
優秀ポスター賞
2017.8 情報処理学会組込みシステム研究会 モデルベース開発におけるクロスレイヤ設計手法のマルチコア上モータ制御実装への適用
竹松慎弥, 鍾 兆前, 井上雅理, 横山静香, 小島流石, 近藤真己, ECソリューションイノベータ, 中本幸一, 安積卓也, 道木慎二, 本田晋也, 枝廣正人
More details
Country:Japan
優秀ポスター賞
2015.10 情報処理学会組込みシステム研究会 Simulinkモデルからのブロックレベル並列化
山口 滉平,竹松 慎弥,池田 良裕,李 瑞徳,鍾 兆前,近藤 真己,枝廣 正人
More details
Country:Japan
優秀ポスター賞
2015.10 情報処理学会組込みシステム研究会 Simulinkモデルからのブロックレベル並列化
山口 滉平, 竹松 慎弥, 池田 良裕, 李 瑞徳, 鍾 兆前, 近藤 真己, 枝廣 正人
More details
Country:Japan
平成21年度科学技術分野の文部科学大臣表彰 科学技術賞(開発部門)
2009.4 文部科学省 LSIクロック配線方式の開発
枝廣 正人
More details
Country:Japan
第18回地球環境大賞 経済産業大臣賞
2009.4 フジサンケイグループ 携帯電話向けLSIの高機能化と低消費電力化の両立
日本電気株式会社(枝廣は技術代表者)
More details
Country:Japan
平成21年度科学技術分野の文部科学大臣表彰 科学技術賞(開発部門)
2009.4 文部科学省 LSIクロック配線方式の開発
枝廣 正人
More details
Country:Japan
第18回地球環境大賞 経済産業大臣賞
2009.4 フジサンケイグループ 携帯電話向けLSIの高機能化と低消費電力化の両立
日本電気株式会社, 枝廣, 技術
More details
Country:Japan
平成19年度業績賞
2008.5 電子情報通信学会 LSIクロック配線方式の研究開発
枝廣 正人
More details
Country:Japan
平成19年度業績賞
2008.5 電子情報通信学会 LSIクロック配線方式の研究開発
枝廣 正人
More details
Country:Japan
平成19年度優秀論文賞
2007.8 情報処理学会SLDM研究会 Map Sort:マルチコアプロセッサに向けたスケーラブルなソートアルゴリズム
枝廣 正人, 山下 慶子
More details
Country:Japan
平成19年度優秀論文賞
2007.8 情報処理学会SLDM研究会 Map Sort:マルチコアプロセッサに向けたスケーラブルなソートアルゴリズム
枝廣 正人, 山下 慶子
More details
Country:Japan
IWIA2007: Best Presentation Award
2007.1 Int. Workshop on Innovative Architecture for Future Generation High-Performance Processors (IWIA) Committee Map Sort: A Scalable Sorting Algorithm for Multi-Core Processors
Masato Edahiro and Yoshiko Yamashita
More details
Country:United States
IWIA2007: Best Presentation Award
2007.1 Int. Workshop on Innovative Architecture for Future Generation High-Performance Processors (IWIA) Committee Map Sort: A Scalable Sorting Algorithm for Multi-Core Processors
Masato Edahiro, Yoshiko Yamashita
More details
Country:United States
平成6年度山下記念研究賞
1994.9 情報処理学会 スキューをゼロにする配線における遅延最小化
枝廣 正人
More details
Country:Japan
平成6年度山下記念研究賞
1994.9 情報処理学会 スキューをゼロにする配線における遅延最小化
枝廣 正人
More details
Country:Japan
平成5年度坂井記念特別賞
1994.5 情報処理学会 VLSI配置配線アルゴリズムの理論と実際に関する研究・開発
枝廣 正人
More details
Country:Japan
平成5年度坂井記念特別賞
1994.5 情報処理学会 VLSI配置配線アルゴリズムの理論と実際に関する研究・開発
枝廣 正人
More details
Country:Japan
第6回元岡賞
1991.11 元岡記念会 CADにおける配置アルゴリズムの研究
枝廣 正人
More details
Country:Japan
第6回元岡賞
1991.11 元岡記念会 CADにおける配置アルゴリズムの研究
枝廣 正人
More details
Country:Japan
平成元年度篠原記念学術奨励賞
1990.3 電子情報通信学会 階層クラスタリングを用いたスタンダードセルLSIのための配置アルゴリズム
枝廣 正人
More details
Country:Japan
平成元年度篠原記念学術奨励賞
1990.3 電子情報通信学会 階層クラスタリングを用いたスタンダードセルLSIのための配置アルゴリズム
枝廣 正人
More details
Country:Japan
第3回学生論文賞
1985.9 日本オペレーションズ・リサーチ学会 幾何学的探索算法の研究
枝廣 正人
More details
Country:Japan
第3回学生論文賞
1985.9 日本オペレーションズ・リサーチ学会 幾何学的探索算法の研究
枝廣 正人
More details
Country:Japan
Model-based Parallelization for Simulink Models on Multicore CPUs and GPUs Reviewed
Z. Zhong and M. Edahiro
International Journal of Computer & Technology Vol. 20 page: 1-13 2020.1
More details
Language:English Publishing type:Research paper (scientific journal)
Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors Reviewed
Z. Zhong, M. Edahiro
International Journal of Computer & Technology Vol. 19 page: 7470-7484 2019.2
More details
Language:English Publishing type:Research paper (scientific journal)
モデルベース開発におけるクロスレイヤ設計手法のマルチコア上モータ制御実装への適用 Reviewed
竹松慎弥,鍾 兆前,井上雅理,横山静香,小島流石(大阪大),近藤真己(NECソリューションイノベータ),中本幸一(兵庫県立大),安積卓也(大阪大),道木慎二,本田晋也, 枝廣正人
組込みシステムシンポジウム(ESS2017) page: ポスター(26) 2017.8
More details
Language:Japanese
Parallel Design of Feedback Control Systems Utilizing Dead Time for Embedded Multicore Processors Reviewed
Y. Suzuki (DENSO), K. Sata (Toyota), J. Kako (Toyota), K. Yamaguchi, F. Arakawa and M. Edahiro
IEICE TRANSACTIONS on Electronics Vol. E99-C ( 4 ) page: 491-502 2016.4
More details
Language:English Publishing type:Research paper (scientific journal)
Establishing a standard interface between multi-manycore and software tools - SHIM Reviewed
M. Gondo, F. Arakawa, and M. Edahiro
Proceedings of COOL Chips XVII page: VI-1 2014.4
More details
Language:English
Research on highly parallel embedded control system design and implementation method Invited
Masato Edahiro and Masaki Gondo
Impact Vol. 2019 ( 10 ) page: 44-46 2019.12
More details
Quality Evaluation for 3D Point Cloud Maps Using Entropy Focused on Road Surfaces
KITSUKAWA Yuki, FUKAGAWA Minato, MEGURO Junichi, KATO Shinpei, EDAHIRO Masato
Journal of the Japan Society for Precision Engineering Vol. 91 ( 3 ) page: 390 - 396 2025.3
More details
Language:Japanese Publisher:The Japan Society for Precision Engineering
<p>Current techniques for assessing the accuracy of 3D point cloud maps are often computationally demanding and lack the capability to pinpoint regions with diminished accuracy. In this research, we introduce an effective approach for evaluating the accuracy of 3D point cloud maps intended for autonomous driving systems. Our method focuses on calculating the entropy of the road surface along the vehicle's trajectory. By employing a moving average of Mean Map Entropy (MME), we can automatically identify areas where the map accuracy has degraded while also reducing the computational load. Through our evaluation, we demonstrate that the proposed method effectively detects point cloud blurring and surface duplication caused by SLAM/MMS errors.</p>
DOI: 10.2493/jjspe.91.390
Multi-Architecture Halide Template-Driven Automatic Library Function Generation for Simulink Models Reviewed
Li, Q; Wu, SW; Edahiro, M
IEEE ACCESS Vol. 13 page: 42866 - 42873 2025
More details
Language:English Publishing type:Research paper (scientific journal)
Li, Q; Edahiro, M
2024 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS, COOL CHIPS 27 2024.4
More details
Authorship:Last author Language:English Publishing type:Research paper (international conference proceedings)
Wu, SW; Kumano, S; Marume, K; Edahiro, M
IEEE ACCESS Vol. 12 page: 35779 - 35795 2024.3
More details
Authorship:Last author Language:English Publishing type:Research paper (scientific journal)
GPU-Accelerated 3D Normal Distributions Transform
Nguyen Anh, Cano Abraham Monrroy, Edahiro Masato, Kato Shinpei
Journal of Robotics and Mechatronics Vol. 35 ( 2 ) page: 445 - 459 2023.4
More details
Language:English Publisher:Fuji Technology Press Ltd.
<p>The three-dimensional (3D) normal distributions transform (NDT) is a popular scan registration method for 3D point cloud datasets. It has been widely used in sensor-based localization and mapping applications. However, the NDT cannot entirely utilize the computing power of modern many-core processors, such as graphics processing units (GPUs), because of the NDT’s linear nature. In this study, we investigated the use of NVIDIA’s GPUs and their programming platform called compute unified device architecture (CUDA) to accelerate the NDT algorithm. We proposed a design and implementation of our GPU-accelerated 3D NDT (GPU NDT). Our methods can achieve a speedup rate of up to 34 times, compared with the NDT implemented in the point cloud library (PCL).</p>
An ILP Task Mapping for MIMD Processor with Vector Accelerator in Model-Based Development Reviewed International journal
S. Wu, S. Kumano, K. Marume and M. Edahiro
2022 International Conference on Electrical, Computer and Energy Technologies (ICECET) page: 1 - 7 2022.7
More details
Authorship:Last author Language:English Publishing type:Research paper (international conference proceedings)
LLVM Instruction Latency Measurement for Software-Hardware Interface for Multi-many-core Reviewed International journal
H. Mikami, K. Torigoe, M. Inokawa, and M. Edahiro
INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY Vol. 22 page: 50 - 63 2022.5
More details
Authorship:Last author Language:English Publishing type:Research paper (scientific journal)
Other Link: https://rajpub.com/index.php/ijct/article/view/9231
Implementation of Vector Control System On Multi-Core Processor by Using Model-Based Parallelization Tool Reviewed
Kim Jinsoo, Sagae Shota, Edahiro Masato, Honda Shinya, Doki Shinji
2022 INTERNATIONAL POWER ELECTRONICS CONFERENCE (IPEC-HIMEJI 2022- ECCE ASIA) page: 1314 - 1319 2022.5
More details
Single-Shot Intrinsic Calibration for Autonomous Driving Applications Reviewed
Monrroy Cano Abraham, Lambert Jacob, Edahiro Masato, Kato Shinpei
Vol. 22 ( 5 ) 2022.3
More details
Mapping Method Usable with Clustered Many-core Platforms for Simulink Model Reviewed
Kobayashi Yutaro, Honda Kentaro, Kojima Sasuga, Fujimoto Hiroshi, Edahiro Masato, Azumi Takuya
Journal of Information Processing Vol. 30 ( 0 ) page: 141 - 150 2022.2
More details
Language:English Publisher:Information Processing Society of Japan
SHIM Standard for Control System Design on Multi-Many-Core SoC Reviewed
Edahiro Masato, Gondo Masaki
SYSTEMS, CONTROL AND INFORMATION Vol. 66 ( 1 ) page: 21 - 26 2022.1
More details
Authorship:Lead author, Last author, Corresponding author Language:Japanese Publisher:THE INSTITUTE OF SYSTEMS, CONTROL AND INFORMATION ENGINEERS
Vision-Based Sensing Systems for Autonomous Driving: Centralized or Decentralized?
Hirabayashi Manato, Saito Yukihiro, Murakami Kosuke, Ohsato Akihito, Kato Shinpei, Edahiro Masato
Journal of Robotics and Mechatronics Vol. 33 ( 3 ) page: 686 - 697 2021.6
More details
Language:English Publisher:Fuji Technology Press Ltd.
<p>The perception of the surrounding circumstances is an essential task for fully autonomous driving systems, but its high computational and network loads typically impede a single host machine from taking charge of the systems. Decentralized processing is a candidate to decrease such loads; however, it has not been clear that this approach fulfills the requirements of onboard systems, including low latency and low power consumption. Embedded oriented graphics processing units (GPUs) are attracting great interest because they provide massively parallel computation capacity with lower power consumption compared to traditional GPUs. This study explored the effects of decentralized processing on autonomous driving using embedded oriented GPUs as decentralized units. We implemented a prototype system that off-loaded image-based object detection tasks onto embedded oriented GPUs to clarify the effects of decentralized processing. The results of experimental evaluation demonstrated that decentralized processing and network quantization achieved approximately 27 ms delay between the feeding of an image and the arrival of detection results to the host as well as approximately 7 W power consumption on each GPU and network load degradation in orders of magnitude. Judging from these results, we concluded that decentralized processing could be a promising approach to decrease processing latency, network load, and power consumption toward the deployment of autonomous driving systems.</p>
Fast Euclidean Cluster Extraction Using GPUs
Anh Nguyen, Cano Abraham Monrroy, Edahiro Masato, Kato Shinpei
JOURNAL OF ROBOTICS AND MECHATRONICS Vol. 32 ( 3 ) page: 548 - 560 2020.6
More details
An Open Multi-Sensor Fusion Toolbox for Autonomous Vehicles
MONRROY CANO Abraham, TAKEUCHI Eijiro, KATO Shinpei, EDAHIRO Masato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E103.A ( 1 ) page: 252 - 264 2020.1
More details
Language:English Publisher:The Institute of Electronics, Information and Communication Engineers
<p>We present an accurate and easy-to-use multi-sensor fusion toolbox for autonomous vehicles. It includes a ‘target-less’ multi-LiDAR (Light Detection and Ranging), and Camera-LiDAR calibration, sensor fusion, and a fast and accurate point cloud ground classifier. Our calibration methods do not require complex setup procedures, and once the sensors are calibrated, our framework eases the fusion of multiple point clouds, and cameras. In addition we present an original real-time ground-obstacle classifier, which runs on the CPU, and is designed to be used with any type and number of LiDARs. Evaluation results on the KITTI dataset confirm that our calibration method has comparable accuracy with other state-of-the-art contenders in the benchmark.</p>
Kim, J; Kato, S; Honda, S; Edahiro, M; Doki, S
2020 23RD INTERNATIONAL CONFERENCE ON ELECTRICAL MACHINES AND SYSTEMS (ICEMS) page: 1951 - 1956 2020
More details
Traffic light recognition using high-definition map features
Hirabayashi Manato, Sujiwo Adi, Monrroy Abraham, Kato Shinpei, Edahiro Masato
ROBOTICS AND AUTONOMOUS SYSTEMS Vol. 111 page: 62 - 72 2019.1
More details
Kim, J; Seiya, K; Edahiro, M; Doki, S
2019 22ND INTERNATIONAL CONFERENCE ON ELECTRICAL MACHINES AND SYSTEMS (ICEMS 2019) page: 5459 - 5463 2019
More details
Mode based Parallelization for Simulink Models on Multicore CPUs and GPUs
Zhong, ZQ; Edahiro, M
2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) page: 103 - 104 2019
More details
Zhong, ZQ; Edahiro, M
2018 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) page: 117 - 118 2018
More details
Relational Joins on GPUs: A Closer Look
Yabuta, M; Nguyen, A; Kato, S; Edahiro, M; Kawashima, H
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Vol. 28 ( 9 ) page: 2663 - 2673 2017.9
More details
Robust and Accurate Monocular Vision-Based Localization in Outdoor Environments of Real-World Robot Challenge
Sujiwo Adi, Takeuchi Eijiro, Morales Luis Yoichi, Akai Naoki, Darweesh Hatem, Ninomiya Yoshiki, Edahiro Masato
JOURNAL OF ROBOTICS AND MECHATRONICS Vol. 29 ( 4 ) page: 685 - 696 2017.8
More details
Localization Based on Multiple Visual-Metric Maps
Sujiwo, A; Takeuchi, E; Morales, LY; Akai, N; Ninomiya, Y; Edahiro, M
2017 IEEE INTERNATIONAL CONFERENCE ON MULTISENSOR FUSION AND INTEGRATION FOR INTELLIGENT SYSTEMS (MFI) page: 212 - 219 2017
More details
Sujiwo Adi, Takeuchi Eijiro, Morales Luis Yoichi, Akai Naoki, Darweesh Hatem, Ninomiya Yoshiki, Edahiro Masato
Journal of Robotics and Mechatronics Vol. 29 ( 4 ) page: 685 - 696 2017
More details
Language:English Publisher:富士技術出版株式会社
<p>This paper describes our approach to perform robust monocular camera metric localization in the dynamic environments of Tsukuba Challenge 2016. We address two issues related to vision-based navigation. First, we improved the coverage by building a custom vocabulary out of the scene and improving upon place recognition routine which is key for global localization. Second, we established possibility of lifelong localization by using previous year's map. Experimental results show that localization coverage was higher than 90% for six different data sets taken in different years, while localization average errors were under 0.2 m. Finally, the average of coverage for data sets tested with maps taken in different years was of 75%.</p>
Sujiwo Adi, Ando Tomohito, Takeuchi Eijiro, Ninomiya Yoshiki, Edahiro Masato
Journal of Robotics and Mechatronics Vol. 28 ( 4 ) page: 479 - 490 2016.8
More details
Language:English Publisher:Fuji Technology Press Ltd.
<p>For the 2015 Tsukuba Challenge, we realized an implementation of vision-based localization based on ORB-SLAM. Our method combined mapping based on ORB-SLAM and Velodyne LIDAR SLAM, and utilized these maps in a localization process using only a monocular camera. We also apply sensor fusion method of odometer and ORB-SLAM from all maps. The combined method delivered better accuracy than the original ORB-SLAM, which suffered from scale ambiguities and map distance distortion. This paper reports on our experience when using ORB-SLAM for visual localization, and describes the difficulties encountered.</p>
Monocular Vision-Based Localization Using ORB-SLAM with LIDAR-Aided Mapping in Real-World Robot Challenge
Sujiwo Adi, Ando Tomohito, Takeuchi Eijiro, Ninomiya Yoshiki, Edahiro Masato
JOURNAL OF ROBOTICS AND MECHATRONICS Vol. 28 ( 4 ) page: 479 - 490 2016.8
More details
Accelerated Deformable Part Models on GPUs
Hirabayashi Manato, Kato Shinpei, Edahiro Masato, Takeda Kazuya, Mita Seiichi
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Vol. 27 ( 6 ) page: 1589 - 1602 2016.6
More details
A scalability analysis of many cores and on-chip mesh networks on the TILE-Gx platform
Liu Ye, Sasaki Hiroshi, Kato Shinpei, Edahiro Masato
2016 IEEE 10TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC) page: 46 - 52 2016
More details
Pure Pursuit Revisited: Field Testing of Autonomous Vehicles in Urban Areas
Ohta Hiroki, Akai Naoki, Takeuchi Eijiro, Kato Shinpei, Edahiro Masato
PROCEEDINGS OF 2016 IEEE 4TH INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS (CPSNA) page: 7 - 12 2016
More details
System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler
Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro
Journal of information processing Vol. 23 ( 5 ) page: 532 - 541 2015.9
More details
Language:English Publisher:一般社団法人 情報処理学会
In this paper, we propose a system-level design method for control systemsthat enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequencyof interrupts. As a result, the processor load increases, leading to a deterioration in thelatency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by aninterrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicatedhardware to be developed using a model that abstracts an interrupt, interruptprocessing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates thetarget implementation from the model. Case studies on a motor control system show that the proposed methodreduces the processor load, improves the latency of the interrupt processing,and enables the design space exploration for the control system.In this paper, we propose a system-level design method for control systemsthat enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequencyof interrupts. As a result, the processor load increases, leading to a deterioration in thelatency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by aninterrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicatedhardware to be developed using a model that abstracts an interrupt, interruptprocessing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates thetarget implementation from the model. Case studies on a motor control system show that the proposed methodreduces the processor load, improves the latency of the interrupt processing,and enables the design space exploration for the control system.
Editor's Message to Special Issue on Embedded Systems Engineering
Masato Edahiro
Journal of information processing Vol. 23 ( 2 ) page: 117 - 117 2015.3
More details
モデル予測制御における非線形漸化式実行の並列化 (コンピュータシステム)
山田 竜正, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 114 ( 506 ) page: 275 - 280 2015.3
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
近年,制御の分野では制御の高精度化が進んでいる.しかし,高精度な制御はシングルコアで処理するには演算負荷が大きい.そこでマルチ・メニーコアの使用が考えられる.高精度な制御として,モデル予測制御がある.この手法では,制御対象の振る舞いをある一定の範囲先まで計算を行う.この計算は制御対象のモデルを用いて行われ,漸化式となる.この漸化式が非線形の場合,漸化式計算は行列計算として表すことができず,計算負荷が大きい上,並列化が難しい.そこで本研究では,この時間かかる非線形漸化式や,それを含む制御の計算の並列実行を検討する.まず漸化式の計算をSimulinkモデルにより記述し,その構造を元にタスク(関数)に分割されたCコードと,そのタスクグラフを生成する.このタスクグラフに対し,CP/MISF法を使用してスケジューリングを行う.16コアのメニーコアシミュレータ上で評価した結果,CP/MISF法を使用すると,非線形漸化式の計算を16コアで10.5倍高速化できることがわかった.また,Simulated Annealing法と比較したところ,並列性能が良く,スケジューリング時間も6桁程度高速であり,CP/MISF法が,非線形漸化式の並列実行に適していることを示した.
モデル予測制御における非線形漸化式実行の並列化 (ディペンダブルコンピューティング)
山田 竜正, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 114 ( 507 ) page: 275 - 280 2015.3
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
近年,制御の分野では制御の高精度化が進んでいる.しかし,高精度な制御はシングルコアで処理するには演算負荷が大きい.そこでマルチ・メニーコアの使用が考えられる.高精度な制御として,モデル予測制御がある.この手法では,制御対象の振る舞いをある一定の範囲先まで計算を行う.この計算は制御対象のモデルを用いて行われ,漸化式となる.この漸化式が非線形の場合,漸化式計算は行列計算として表すことができず,計算負荷が大きい上,並列化が難しい.そこで本研究では,この時間かかる非線形漸化式や,それを含む制御の計算の並列実行を検討する.まず漸化式の計算をSimulinkモデルにより記述し,その構造を元にタスク(関数)に分割されたCコードと,そのタスクグラフを生成する.このタスクグラフに対し,CP/MISF法を使用してスケジューリングを行う.16コアのメニーコアシミュレータ上で評価した結果,CP/MISF法を使用すると,非線形漸化式の計算を16コアで10.5倍高速化できることがわかった.また,Simulated Annealing法と比較したところ,並列性能が良く,スケジューリング時間も6桁程度高速であり,CP/MISF法が,非線形漸化式の並列実行に適していることを示した.
山田 竜正, 枝廣 正人
情報処理学会研究報告. SLDM, [システムLSI設計技術] Vol. 2015 ( 37 ) page: 1 - 6 2015.2
More details
Language:Japanese Publisher:一般社団法人情報処理学会
近年,制御の分野では制御の高精度化が進んでいる.しかし,高精度な制御はシングルコアで処理するには演算負荷が大きい.そこでマルチ・メニーコアの使用が考えられる.高精度な制御として,モデル予測制御がある.この手法では,制御対象の振る舞いをある一定の範囲先まで計算を行う.この計算は制御対象のモデルを用いて行われ,漸化式となる.この漸化式が非線形の場合,漸化式計算は行列計算として表すことができず,計算負荷が大きい上,並列化が難しい.そこで本研究では,この時間かかる非線形漸化式や,それを含む制御の計算の並列実行を検討する.まず漸化式の計算を Simulink モデルにより記述し,その構造を元にタスク (関数) に分割された C コードと,そのタスクグラフを生成する.このタスクグラフに対し,CP/MISF 法を使用してスケジューリングを行う.16 コアのメニーコアシミュレータ上で評価した結果,CP/MISF法 を使用すると,非線形漸化式の計算を 16 コアで 10.5 倍高速化できることがわかった.また,Simulated Annealing 法と比較したところ,並列性能が良く,スケジューリング時間も 6 桁程度高速であり,CP/MISF 法が,非線形漸化式の並列実行に適していることを示した.
山田 竜正, 枝廣 正人
情報処理学会研究報告. EMB, 組込みシステム Vol. 2015 ( 37 ) page: 1 - 6 2015.2
More details
Language:Japanese Publisher:一般社団法人情報処理学会
近年,制御の分野では制御の高精度化が進んでいる.しかし,高精度な制御はシングルコアで処理するには演算負荷が大きい.そこでマルチ・メニーコアの使用が考えられる.高精度な制御として,モデル予測制御がある.この手法では,制御対象の振る舞いをある一定の範囲先まで計算を行う.この計算は制御対象のモデルを用いて行われ,漸化式となる.この漸化式が非線形の場合,漸化式計算は行列計算として表すことができず,計算負荷が大きい上,並列化が難しい.そこで本研究では,この時間かかる非線形漸化式や,それを含む制御の計算の並列実行を検討する.まず漸化式の計算を Simulink モデルにより記述し,その構造を元にタスク (関数) に分割された C コードと,そのタスクグラフを生成する.このタスクグラフに対し,CP/MISF 法を使用してスケジューリングを行う.16 コアのメニーコアシミュレータ上で評価した結果,CP/MISF法 を使用すると,非線形漸化式の計算を 16 コアで 10.5 倍高速化できることがわかった.また,Simulated Annealing 法と比較したところ,並列性能が良く,スケジューリング時間も 6 桁程度高速であり,CP/MISF 法が,非線形漸化式の並列実行に適していることを示した.
枝廣 正人
情報処理学会論文誌 Vol. 56 ( 2 ) page: 714 - 714 2015.2
More details
Language:Japanese Publisher:一般社団法人情報処理学会
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip
Ando Yuki, Ishida Yukihito, Honda Shinya, Takada Hiroaki, Edahiro Masato
Information and Media Technologies Vol. 10 ( 3 ) page: 415 - 419 2015
More details
Language:English Publisher:Information and Media Technologies Editorial Board
This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can be various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by single binary operating systems. Proposed method automatically synthesizes the inter-heterogeneous-processor communications at an application layer from a general model description. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs the system on heterogeneous multiprocessors.
DOI: 10.11185/imt.10.415
Editor's Message to Special Issue of Embedded Systems Engineering
Edahiro Masato
Journal of Information Processing Vol. 23 ( 5 ) page: 531 - 531 2015
More details
Language:English Publisher:Information Processing Society of Japan
Design Space Exploration of Control System with Hardware-implemented Interrupt Handler
Ando Yuki, Honda Shinya, Takada Hiroaki, Edahiro Masato
2015 6TH INTERNATIONAL CONFERENCE OF INFORMATION AND COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS (IC-ICTES) 2015
More details
Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip
Ando Yuki, Ishida Yukihito, Honda Shinya, Takada Hiroaki, Edahiro Masato
2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA) 2015
More details
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip
Ando Yuki, Ishida Yukihito, Honda Shinya, Takada Hiroaki, Edahiro Masato
IPSJ Transactions on System LSI Design Methodology Vol. 8 ( 0 ) page: 95 - 99 2015
More details
Language:English Publisher:Information Processing Society of Japan
This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can be various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by single binary operating systems. Proposed method automatically synthesizes the inter-heterogeneous-processor communications at an application layer from a general model description. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs the system on heterogeneous multiprocessors.
HexaCam: An FPGA-based Multi-view Camera System
Monrroy Abraham, Hirabayashi Manato, Kato Shinpei, Edahiro Masato, Miyoshi Takefumi, Funada Satoshi
2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015 page: 48 - 53 2015
More details
Real-Time Visualization of Moving Objects
Ortal Patricia, Kato Shinpei, Edahiro Masato
2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015 page: 60 - 65 2015
More details
システムレベル設計における制御システム向けプロファイル機構 (VLSI設計技術) -- (デザインガイア2014 : VLSI設計の新しい大地)
繆 同徳, 安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 114 ( 328 ) page: 75 - 80 2014.11
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
本論文ではシステムレベル設計における制御システム向けのプロファイル機構を述べる.制御システムを設計する際,センサーやアクチュエータから非同期で通知される割込みと,割込みにより優先的に処理を開始する割込み処理を考慮する必要がある.但し,既存のプロファイル機構は割込みの関連情報を取得できない.本論文では,制御システムの開発を支援するために,割込みの関連情報を取得可能なプロファイル手法を提案する.提案手法を設計事例に適用し,効果を評価した.
割込みハンドラのハードウェア化を実現するシステムレベル設計手法 (ディペンダブルコンピューティング) -- (デザインガイア2014 : VLSI設計の新しい大地)
安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 114 ( 329 ) page: 69 - 74 2014.11
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
本論文は,割込みで駆動する専用HWを設計可能な,制御システム向けのシステムレベル設計ツールについて述べる.制御システムは複雑化,処理の高度化が進み,それに伴い割込み処理の頻度が増加したことで,プロセッサ負荷の増加,消費電力の増加,割込み処理レイテンシの悪化といった問題が生じている.これらの問題を解決するため,割込みにより処理を開始し,処理中はセンサや入出力ハードウェアといったデバイスへ直接アクセスする専用ハードウェアが求められている.提案手法は,処理とデバイス間の通信,割込み,割込み処理を抽象化した制御システムモデルから,割込みで駆動するハードウェアを含む制御システムを設計可能である.モータ制御システムを対象とした評価実験により,提案手法を用いることで,プロセッサ負荷の削減,消費電力の削減,レイテンシの改善が可能なことを示す.
割込みハンドラのハードウェア化を実現するシステムレベル設計手法 (VLSI設計技術) -- (デザインガイア2014 : VLSI設計の新しい大地)
安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 114 ( 328 ) page: 69 - 74 2014.11
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
本論文は,割込みで駆動する専用HWを設計可能な,制御システム向けのシステムレベル設計ツールについて述べる.制御システムは複雑化,処理の高度化が進み,それに伴い割込み処理の頻度が増加したことで,プロセッサ負荷の増加,消費電力の増加,割込み処理レイテンシの悪化といった問題が生じている.これらの問題を解決するため,割込みにより処理を開始し,処理中はセンサや入出力ハードウェアといったデバイスへ直接アクセスする専用ハードウェアが求められている.提案手法は,処理とデバイス間の通信,割込み,割込み処理を抽象化した制御システムモデルから,割込みで駆動するハードウェアを含む制御システムを設計可能である.モータ制御システムを対象とした評価実験により,提案手法を用いることで,プロセッサ負荷の削減,消費電力の削減,レイテンシの改善が可能なことを示す.
システムレベル設計における制御システム向けプロファイル機構 (ディペンダブルコンピューティング) -- (デザインガイア2014 : VLSI設計の新しい大地)
繆 同徳, 安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 114 ( 329 ) page: 75 - 80 2014.11
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
本論文ではシステムレベル設計における制御システム向けのプロファイル機構を述べる.制御システムを設計する際,センサーやアクチュエータから非同期で通知される割込みと,割込みにより優先的に処理を開始する割込み処理を考慮する必要がある.但し,既存のプロファイル機構は割込みの関連情報を取得できない.本論文では,制御システムの開発を支援するために,割込みの関連情報を取得可能なプロファイル手法を提案する.提案手法を設計事例に適用し,効果を評価した.
油谷 創, 枝廣 正人
情報処理学会研究報告. EMB, 組込みシステム Vol. 2014 ( 3 ) page: 1 - 8 2014.9
More details
Language:Japanese Publisher:一般社団法人情報処理学会
近年,半導体技術の進展によって 1 つの LSI 上に複数のプロセッサが搭載されたマルチコアや,数十,数百のプロセッサが搭載されたメニーコアが広く使われている.また,スケーラビリティをさらに高めるために階層構造を持つメニーコアも登場している.階層型メニーコアアーキテクチャは,将来組込みプロセッサにおいても主流になると考えられている.そこで,階層構造を考慮したタスクマッピング手法を提案し,既存手法との比較評価を行った.提案手法は NN Embed 法,Topo-LB 法,Cluster-Based ILP 法と比較してそれぞれ 44%,32%,26%通信コストの少ないマッピング結果を示した.
ソフトウェア向けハードウェア性能記述を用いたマルチコアにおける性能見積り (コンピュータシステム 組込み技術とネットワークに関するワークショップETNET2014)
西村 裕, 中村 陸, 荒川 文男, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 113 ( 497 ) page: 151 - 156 2014.3
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
多種多様なメニーコアアーキテクチャが提案されてきており,今後ますます増える傾向にある.このような状況において,ソフトウェア開発ツール等がアーキテクチャ毎に個別に対応することは非効率である.これをなくすため我々は,マルチ・メニーコア標準プラットフォームの開発を進め,ソフトウェア視点での性能情報を含むハードウェア記述の標準化を提案している.本研究では,組込みメニーコアプロセッサの一つを用い,標準記述による性能見積りと実際の処理時間の差異を評価し,精度を高めるための手法及び課題について述べる.
単方向1:1高速同期機構を用いたFPGA実装と評価 (ディペンダブルコンピューティング 組込み技術とネットワークに関するワークショップETNET2014)
溝口 裕哉, 中村 陸, 安藤 友樹, 荒川 文男, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 113 ( 498 ) page: 145 - 150 2014.3
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
近年,組込み制御分野でマルチ・メニーコアの使用が主流となりつつある.複数のコアで制御プログラムを並列に動作させる場合,コア間通信のオーバーヘッドが大きな問題である.そこで,我々は単方向1:1高速同期機構とよぶ高速な通信メカニズムを提案し,その改善を図っている.本稿では,提案機構向けに新たに考案したハードウェア支援手法とFPGAによる評価結果を報告する.モーター制御アプリケーションを用いた評価では,提案手法はマルチコアRTOSの通信APIと比べ,通信時間が約12分の1に短縮された.
単方向1:1高速同期機構を用いたFPGA実装と評価 (コンピュータシステム 組込み技術とネットワークに関するワークショップETNET2014)
溝口 裕哉, 中村 陸, 安藤 友樹, 荒川 文男, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 113 ( 497 ) page: 145 - 150 2014.3
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
近年,組込み制御分野でマルチ・メニーコアの使用が主流となりつつある.複数のコアで制御プログラムを並列に動作させる場合,コア間通信のオーバーヘッドが大きな問題である.そこで,我々は単方向1:1高速同期機構とよぶ高速な通信メカニズムを提案し,その改善を図っている.本稿では,提案機構向けに新たに考案したハードウェア支援手法とFPGAによる評価結果を報告する.モーター制御アプリケーションを用いた評価では,提案手法はマルチコアRTOSの通信APIと比べ,通信時間が約12分の1に短縮された.
ソフトウェア向けハードウェア性能記述を用いたマルチコアにおける性能見積り (ディペンダブルコンピューティング 組込み技術とネットワークに関するワークショップETNET2014)
西村 裕, 中村 陸, 荒川 文男, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 113 ( 498 ) page: 151 - 156 2014.3
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
多種多様なメニーコアアーキテクチャが提案されてきており,今後ますます増える傾向にある.このような状況において,ソフトウェア開発ツール等がアーキテクチャ毎に個別に対応することは非効率である.これをなくすため我々は,マルチ・メニーコア標準プラットフォームの開発を進め,ソフトウェア視点での性能情報を含むハードウェア記述の標準化を提案している.本研究では,組込みメニーコアプロセッサの一つを用い,標準記述による性能見積りと実際の処理時間の差異を評価し,精度を高めるための手法及び課題について述べる.
Establishing a standard interface between multi-manycore and software tools - SHIM
Gondo Masaki, Arakawa Fumio, Edahiro Masato
2014 IEEE COOL CHIPS XVII 2014
More details
Power and Performance Characterization and Modeling of GPU-Accelerated Systems
Abe Yuki, Inoue Koji, Sasaki Hiroshi, Edahiro Masato, Kato Shinpei, Peres Martin
2014 IEEE 28TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM 2014
More details
Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors
Suzuki Yuta, Sata Kota, Kako Junichi, Yamaguchi Kohei, Arakawa Fumio, Edahiro Masato
2014 IEEE COOL CHIPS XVII 2014
More details
Implementation of Embedded Control Systems on Multi-Many-Core Processors
EDAHIRO Masato
Journal of The Society of Instrument and Control Engineers Vol. 53 ( 12 ) page: 1111 - 1116 2014
More details
Language:Japanese Publisher:The Society of Instrument and Control Engineers
ISHIDA Yukihito, ANDO Yuki, HONDA Shinya, TAKADA Hiroaki, EDAHIRO Masato
IEICE technical report Vol. 113 ( 325 ) page: 63 - 68 2013.11
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heterogeneous multiprocessors. Along with the increase in the use of heterogeneous multiprocessors such as FPGAs with processor cores, the cost for design and implement of the inter-processor communication becomes a problem. Focusing on that typical heterogeneous multiprocessors have inter-processor interrupts and shared memories, we propose an implementation of inter-processor communication using them. In order to increase the design efficiency, we also propose a method that automatically generates the inter-processor communication for target systems. The case study shows that automatically generated inter-processor communication exactly runs on the system with heterogeneous multiprocessors.
System-level design method considering the interrupt processing
ANDO Yuki, ISHIDA Yukihito, HONDA Shinya, TAKADA Hiroaki, EDAHIRO Masato
IEICE technical report. Dependable computing Vol. 113 ( 321 ) page: 119 - 124 2013.11
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
We propose a system level design methodology for control systems that have both input and output by abstraction of interrupt handling. Since control systems are increasing their complexity, the designers have to design them on higher level of abstraction to increase design efficiency. System level design is known as one of the way to realize that. However, they cannot handle control systems because they do not consider interrupt handling. We propose a model that deals with control systems at system level by abstraction of interrupt handling. The case study shows that our proposing model has few overhead on memory usage and execution time.
System-level design method considering the interrupt processing
ANDO Yuki, ISHIDA Yukihito, HONDA Shinya, TAKADA Hiroaki, EDAHIRO Masato
Technical report of IEICE. VLD Vol. 113 ( 320 ) page: 119 - 124 2013.11
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
We propose a system level design methodology for control systems that have both input and output by abstraction of interrupt handling. Since control systems are increasing their complexity, the designers have to design them on higher level of abstraction to increase design efficiency. System level design is known as one of the way to realize that. However, they cannot handle control systems because they do not consider interrupt handling. We propose a model that deals with control systems at system level by abstraction of interrupt handling. The case study shows that our proposing model has few overhead on memory usage and execution time.
中村陸 , 荒川文男 , 枝廣正人
情報処理学会研究報告. [システムソフトウェアとオペレーティング・システム] Vol. 2013 ( 11 ) page: 1 - 6 2013.11
More details
Language:Japanese Publisher:一般社団法人情報処理学会
組込み制御領域において,マルチ・メニーコア化とこれを活用するための制御ソフトウェアの並列化が進められている.しかし期待される処理性能のボトルネックとして,タスクスケジューリングやプロセッサ間通信のオーバヘッドが存在する.1 コア 1 タスクに静的割付けし,単方向 1:1 高速同期機構による通信を用いることで,モータ制御モデルを用いた性能評価において,メニーコア向け高機能 OS 利用と比較して通信時間を 25 分の 1 とし,実行サイクルを逐次実行よりも 25% 程度低減することができた.
中村陸 , 荒川文男 , 枝廣正人
情報処理学会研究報告. EMB, 組込みシステム Vol. 2013 ( 11 ) page: 1 - 6 2013.11
More details
Language:Japanese Publisher:一般社団法人情報処理学会
組込み制御領域において,マルチ・メニーコア化とこれを活用するための制御ソフトウェアの並列化が進められている.しかし期待される処理性能のボトルネックとして,タスクスケジューリングやプロセッサ間通信のオーバヘッドが存在する.1 コア 1 タスクに静的割付けし,単方向 1:1 高速同期機構による通信を用いることで,モータ制御モデルを用いた性能評価において,メニーコア向け高機能 OS 利用と比較して通信時間を 25 分の 1 とし,実行サイクルを逐次実行よりも 25% 程度低減することができた.
大川禎 , 枝廣正人
情報処理学会研究報告. EMB, 組込みシステム Vol. 2013 ( 2 ) page: 1 - 7 2013.9
More details
Language:Japanese Publisher:一般社団法人情報処理学会
近年,マルチコア・メニーコアが組込みシステムにおいても主流となりつつある.また,制御システムの大規模複雑化による開発工数の増大が課題となっている.そのため,メニーコアであるイベントドリブンプロセッサを用い,タスクをコアに対応させることで制御モデルの実装を行うことを考える.これにより,同一コア内でのタスクスケジューリングが不要となり,開発工数の削減が期待できる.このとき,複数の制御周期が混在するマルチレートモデル,特に制御周期が動的に変化する場合が課題となる.本論文ではマルチレート制御モデルをイベントドリブンプロセッサに実現する手法を提案し,ベンチマークとして制御モデルを実装することで,提案手法の有効性を評価した.
鈴木悠太 , 枝廣正人
情報処理学会研究報告. EMB, 組込みシステム Vol. 2013 ( 1 ) page: 1 - 8 2013.9
More details
Language:Japanese Publisher:一般社団法人情報処理学会
本研究では,組込み制御システムにおいて近年研究が進められているモデルベース並列化に着目し,制御系の離散実装時に多くあらわれる差分方程式に対して,並列化前後の誤差を 0 にする,前進差分型・後退差分型の各並列化手法とそのモデリング手法を提案する.提案手法を用いて MATLAB/Simulink で記述された実際のモータ制御モデルを並列設計し,前進差分型と比較して後退差分型の並列性の性能向上を示すと共に,従来経験的に与えられていた遅延要素の初期値設定に関して,解析的な導出方法を提案する.従来のアプローチを適用できないモデルに対して,提案手法の有効性を実証する.
CSP理論にもとづいた制御モデルのマルチコア実装向けタスク割当て (コンピュータシステム 組込み技術とネットワークに関するワークショップETNET2013)
大川 禎, 枝廣 正人, 久村 孝寛
電子情報通信学会技術研究報告 : 信学技報 Vol. 112 ( 481 ) page: 133 - 138 2013.3
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
近年,マルチコア・メニーコアが組込みシステムにおいても主流となりつつある.また,制御処理を記述する上で有効なソフトウェアモデルとして,CSP (Communicating Sequential Processes)があげられる.本論文では,汎用マイクロコントローラベースのマルチコアシステムをターゲットとし,CSPにより記述されたモーター制御モデルの実装を行い,実行時間が最小となるタスク割当てパターンを非線形計画問題によって発見した.また,従来手法から得られたタスク割り当てパターンと性能比較を行った結果,従来手法に比べ15%性能を改善することができた.
CSP理論にもとづいた制御モデルのマルチコア実装向けタスク割当て (ディペンダブルコンピューティング 組込み技術とネットワークに関するワークショップETNET2013)
大川 禎, 枝廣 正人, 久村 孝寛
電子情報通信学会技術研究報告 : 信学技報 Vol. 112 ( 482 ) page: 133 - 138 2013.3
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
近年,マルチコア・メニーコアが組込みシステムにおいても主流となりつつある.また,制御処理を記述する上で有効なソフトウェアモデルとして,CSP (Communicating Sequential Processes)があげられる.本論文では,汎用マイクロコントローラベースのマルチコアシステムをターゲットとし,CSPにより記述されたモーター制御モデルの実装を行い,実行時間が最小となるタスク割当てパターンを非線形計画問題によって発見した.また,従来手法から得られたタスク割り当てパターンと性能比較を行った結果,従来手法に比べ15%性能を改善することができた.
Cyber-Physical Systems and LSI Design Technologies
KATO Shinpei, EDAHIRO Masato
Technical report of IEICE. VLD Vol. 112 ( 451 ) page: 67 - 69 2013.3
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
Our society faces a core challenge to societal problems, including environmental pollution and aging population, and industrial problems. This raises the need of integrated infrastructure systems that bring innovations to both the society and industrial technology. One of such systems is a cyber-physical systems (CPS), which tightly coordinates computation and communication with real-world elements. CPS represents multidisciplinary computer systems and its systematic model has not been well explored. Each individual technology of CPS also faces a core challenge to meet the performance and functional requirements. In this paper. we argue a possible research direction of applying LSI design technologies to CPS in terms of optimization problems of platforms and applications, introducing cutting-edge CPS technology in the state of the art.
Jozwik Krzystof, Honda Shinya, Edahiro Masato, Tomiyama Hiroyuki, Takada Hiroaki
電子情報通信学会技術研究報告 : 信学技報 Vol. 112 ( 375 ) page: 135 - 140 2013.1
More details
Language:English Publisher:一般社団法人電子情報通信学会
Jozwik Krzystof, Honda Shinya, Edahiro Masato, Tomiyama Hiroyuki, Takada Hiroaki
電子情報通信学会技術研究報告 : 信学技報 Vol. 112 ( 377 ) page: 135 - 140 2013.1
More details
Language:English Publisher:一般社団法人電子情報通信学会
Jozwik Krzystof, Honda Shinya, Edahiro Masato, Tomiyama Hiroyuki, Takada Hiroaki
電子情報通信学会技術研究報告 : 信学技報 Vol. 112 ( 376 ) page: 135 - 140 2013.1
More details
Language:English Publisher:一般社団法人電子情報通信学会
Data Transfer Matters for GPU Computing
Fujii Yusuke, Azumi Takuya, Nishio Nobuhiko, Kato Shinpei, Edahiro Masato
2013 19TH IEEE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS 2013) page: 275 - 282 2013
More details
GPU Implementations of Object Detection using HOG Features and Deformable Models
Hirabayashi, M; Kato, S; Edahiro, M; Takeda, K; Kawano, T; Mita, S
2013 IEEE 1ST INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS (CPSNA) page: 106 - 111 2013
More details
Power and Performance of GPU-accelerated Systems: A Closer Look
Abe Yuki, Sasaki Hiroshi, Kato Shinpei, Inoue Koji, Edahiro Masato, Peres Martin
2013 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION (IISWC 2013) page: 109 - + 2013
More details
スッパキットパイサーン ウォラポン, 枝廣 正人, 今井 浩
電子情報通信学会技術研究報告. COMP, コンピュテーション Vol. 112 ( 93 ) page: 79 - 86 2012.6
More details
Language:English Publisher:一般社団法人電子情報通信学会
本研究ではマルチスカラー倍算における非対称数字表現の平均的な効率を定める手法を提案する。マルチスカラー倍算は楕円曲線デジタル署名アルゴリズム(ECDSA)において最も計算時間を要する演算であるため、表現数字集合拡大をはじめ様々な研究がされている。表現数字集合を拡大するとマルチスカラー倍算は高速化されるが、前処理に長い時間を要する。そこで、我々は非対称数字表現を提案し、マルコフ連鎖やグラフ理論を利用して解析を行った。その結果、非対称数字表現は前処理を拡大数字集合ほど必要とせず、効率も高いと確認できた。
Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis
ISHIDA Yukihito, SHIBATA Seiya, ANDO Yuki, HONDA Shinya, TAKADA Hiroaki, EDAHIRO Masato
IEICE technical report. Artificial intelligence and knowledge-based processing Vol. 112 ( 70 ) page: 77 - 82 2012.5
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FPGA and STP engine in order to confirm their performance whether they can substitute the dedicated hardware of SoC. We selected AES and ADPCM applications to compare the performance of FPGA and STP engine. The applications were synthesized with the same behavioral synthesis tools. Then, we implemented them onto FPGA and STP engine using the integrated development environments. For the evaluation, we compared them in terms of hardware area, the number of states, the number of cycles, frequency, and execution time.
Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework
KAWASHIMA HIROTAKA, ZENG GANG, TAKASE HIDEKI, Masato Edahiro, Hiroaki Takada
情報処理学会論文誌 論文誌トランザクション Vol. 5 ( 0 ) page: 133 - 142 2012
More details
Language:English Publisher:一般社団法人情報処理学会
A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice.
Special Section on Discrete Mathematics and Its Applications
CHAO Jinhui, EDAHIRO Masato, FUJITO Toshihiro, HAGIHARA Kenichi, HANDA Keiichi, HIRAISHI Kunihiko, ITO Hiro, MAMBO Masahiro, MATSUI Tomomi, MIYANO Eiji, OKAMOTO Eiji, OSAWA Shingo, OKABE Yasuo, IMAI Keiko
IEICE transactions on fundamentals of electronics, communications and computer sciences Vol. 84 ( 5 ) page: 1093 2001.5
More details
Language:English Publisher:The Institute of Electronics, Information and Communication Engineers
Parallel Metaheuristic Algorithms: for Task Scheduling Problems Reviewed
Mao Sirui, M. Edahiro
International Journal of Computer & Technology Vol. 25 page: 1-13 2025.3
More details
Authorship:Last author Language:English Publishing type:Research paper (scientific journal)
Quality Evaluation for 3D Point Cloud Maps Using Entropy Focused on Road Surfaces Reviewed
Vol. 91 ( 3 ) page: 390 - 396 2025.3
More details
Language:English Publishing type:Research paper (scientific journal)
LLVM Instruction Latency Measurement for Software-Hardware Interface for Multi-many-core Reviewed
H. Mikami, K. Torigoe, M. Inokawa, and M. Edahiro
COOL CHIPS 25 2022.4
More details
Authorship:Last author Language:English
Mapping Method Usable with Clustered Many-core Platforms for Simulink Model Reviewed
Yutaro Kobayashi, Kentaro Honda, Sasuga Kojima, Hiroshi Fujimoto, Masato Edahiro, and Takuya Azumi
Vol. 63 ( 2 ) 2022.2
More details
Language:English Publishing type:Research paper (scientific journal)
Robustness Evaluation of Vehicle Localization in 3D Map Using Convergence of Scan Matching
Kitsukawa Yuki, Minami Tatsuya, Yamazaki Yudai, Meguro Junich, Takeuchi Eijiro, Ninomiya Yoshiki, Kato Shinpei, Edahiro Masato
International Journal of Automotive Engineering Vol. 13 ( 4 ) page: 206 - 213 2022
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:Society of Automotive Engineers of Japan, INC
ABSTRACT: Ego-vehicle localization is a critical technology in autonomous driving systems, and one of the widely used methods for localization is scan matching between a 3D map and real-time LiDAR scan. This method is known to fail due to factors such as an incorrect initial position and orientation for scan matching. In this paper, we propose a simulator-based localization evaluation framework to verify the robustness of localization. By using a simulator, localization can be evaluated without driving a real vehicle, and can be evaluated by creating disturbances such as traffic jams. Our framework also allows to evaluate the robustness of localization by using multiple particles with random errors of the initial position and orientation for scan matching to simulate dead reckoning errors caused by multiple factors such as road surface conditions and tire diameter. In the evaluation experiments, we confirmed that the robustness of localization can be evaluated by applying this method to factors such as sensor setup, disturbances in the traffic environment, and the amount of 3D features in the environment.
A Study on the Implementation of Vector Control System Using the Model Base Parallelization Tool on Multi-Core Processor
Jinsoo Kim, Seiya Kato, Shinya Honda, Masato Edahiro, Shinji Doki
23rd International Conference on Electrical Machines and Systems, ICEMS 2020 page: 1951 - 1956 2020.11
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:Institute of Electrical and Electronics Engineers Inc.
The scope of embedded systems used by multi-core processors is widely applied to various products that require control, such as home appliances, industrial devices, transportation devices, and communication terminals. Model-Base Parallelization technology was proposed towards efficient parallelization to implement a control system in the introduction of multi-core processors. By applying MBP, it is possible to parallelization even details that people are not aware of, but the control system with numerous causal relationships still does not sufficiently utilize multi-core. Therefore, a method of inserting a time-delay is being studied as a method for improving the parallelization of multi-cores.In this paper, We describe the insertion location that improves parallelization and does not affect the control performance by inserting time-delay to implement the vector control system of PMSM on multi-core efficiently.
Switching Hybrid Method Based on User Similarity and Global Statistics for Collaborative Filtering Reviewed
Patricia Ortal and Masato Edahiro
IEEE Access Vol. 8 page: 213401 - 213415 2020.9
More details
Language:English Publishing type:Research paper (scientific journal)
Similarity Measure for Product Attribute Estimation Reviewed
Patricia Ortal and Masato Edahiro
IEEE Access Vol. 8 page: 179073 - 179082 2020.9
More details
Language:English Publishing type:Research paper (scientific journal)
FPGA混在のHM-SoCに対するモデルベース並列化設計開発環境の検討 Reviewed
山本 椋太, 小川 真彩高, 生沼 正博, 近藤 真己, 本田 晋也, 枝廣 正人
DAシンポジウム論文集 page: 81 - 88 2020.9
More details
Language:Japanese Publishing type:Part of collection (book)
モデルベース並列化ツールを用いたマルチコアシステム開発フローの提案 Reviewed
生沼 正博, 山本 椋太, 竹内 成樹, 権藤 正樹, 本田 晋也, 近藤 真己, 枝廣 正人
DAシンポジウム論文集 page: 73 - 80 2020.9
More details
Language:Japanese Publishing type:Part of collection (book)
Fast Euclidean Cluster Extraction Using GPUs Reviewed
Anh Nguyen, Abraham Monrroy Cano, Masato Edahiro, and Shinpei Kato
Journal of Robotics and Mechatronics Vol. 32 ( 3 ) page: 548 - 560 2020.6
More details
Language:English Publishing type:Research paper (scientific journal)
Fast Euclidean Cluster Extraction Using GPUs
Nguyen Anh, Cano Abraham Monrroy, Edahiro Masato, Kato Shinpei
Journal of Robotics and Mechatronics Vol. 32 ( 3 ) page: 548 - 560 2020.6
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:Fuji Technology Press Ltd.
<p>Clustering is the task of dividing an input dataset into groups of objects based on their similarity. This process is frequently required in many applications. However, it is computationally expensive when running on traditional CPUs due to the large number of connections and objects the system needs to inspect. In this paper, we investigate the use of NVIDIA graphics processing units and their programming platform CUDA in the acceleration of the Euclidean clustering (EC) process in autonomous driving systems. We propose GPU-accelerated algorithms for the EC problem on point cloud datasets, optimization strategies, and discuss implementation issues of each method. Our experiments show that our solution outperforms the CPU algorithm with speedup rates up to 87X on real-world datasets.</p>
An Open Multi-Sensor Fusion Toolbox for Autonomous Vehicles Reviewed
A. C. Monrroy, E. Takeuchi, M. Edahiro and S. Kato
IEICE Transastions on Fundamentals Vol. E103-A ( 1 ) page: 252-264 2020.1
More details
Language:English Publishing type:Research paper (scientific journal)
An Open Multi-Sensor Fusion Toolbox for Autonomous Vehicles Reviewed
A. C. Monrroy, E. Takeuchi, M. Edahiro, S. Kato
IEICE Transastions on Fundamentals Vol. E103-A ( 1 ) page: 252-264 2020.1
More details
Language:English Publishing type:Research paper (scientific journal)
Model-based Parallelization for Simulink Models on Multicore CPUs and GPUs Reviewed
Z. Zhong, M. Edahiro
International Journal of Computer & Technology Vol. 20 page: 1-13 2020.1
More details
Language:English Publishing type:Research paper (scientific journal)
Mapping Method of MATLAB/Simulink Model for Embedded Many-Core Platform
Kentaro Honda, Sasuga Kojima, Hiroshi Fujimoto, Masato Edahiro, Takuya Azumi
Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020 page: 182 - 186 2020
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:Institute of Electrical and Electronics Engineers Inc.
Multi-/many-core processors are being increasingly used to reduce power consumption and improve performance. In addition, the use of Model-Based Development for embedded systems has been increasing. Relative to these trends, Model-Based Parallelizer (MBP) has an essential role in parallelizing applications (i.e., Simulink blocks) at the model level. MBP maps Simulink blocks to cores using various types of information such as block characteristics, a C code, and the multi-/many-core hardware implementation. However, MBP does not consider many-core hardware with cluster structures. This paper proposes an algorithm that decides on core allocations by considering cluster structures. The proposed algorithm combines two other algorithms: one algorithm uses the core allocation of MBP and path analysis at the cluster-level and considers the influence of communication contention to decide on cluster allocations, and the other algorithm uses the results of MBP and remaps cluster allocations. The proposed algorithm produces better results than its component algorithms could separately. Evaluations demonstrate that the proposed algorithm obtained the better results than the existing method in terms of execution time on random and real models.
Similarity measure for product attribute estimation
Patricia Ortal, Masato Edahiro
IEEE Access Vol. 8 page: 179073 - 179082 2020
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:Institute of Electrical and Electronics Engineers Inc.
Representing products as a combination of properties that capture the essence of consumer sentiment is critical for companies that strive to understand consumer behavior. A catalogue of products described in terms of their attributes could offer companies a wide range of benefits
from improving existing products or developing new ones, to improving the quality of site search and offering better item recommendations to users. In this paper, we propose a method that encodes products as a sequence of attributes, each of which represents a different dimension of the consumer perception. In the proposed method, first, a base product set with known attribute values is built based on consumers’ perceptions. Then, new product attribute vectors are estimated using product similarity. The proposed method also incorporates a new similarity measure that is based on purchase behavior and which is suitable for estimating product attribute vector distances. Because it takes into account the magnitude of the individual components of the vectors under comparison, the proposed method is free from the limitations of conventional similarity measures. The results of experiments conducted using real-world data indicate that the proposed method has superior performance compared to conventional approaches in terms of mean absolute error (MAE) and root mean squared error (RMSE).
Switching Hybrid Method Based on User Similarity and Global Statistics for Collaborative Filtering
Patricia Ortal, Masato Edahiro
IEEE Access Vol. 8 page: 213401 - 213415 2020
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:Institute of Electrical and Electronics Engineers Inc.
Collaborative filtering (CF) is a technique used in recommender systems to provide meaningful suggestions based on known feedback obtained from like-minded users. The measure of similarity plays a critical role in the performance of neighborhood-based CF methods. However, conventional similarity measures suffer from limitations because they only consider the direction of the rating vectors. We propose a novel similarity measure that considers the semantic nuances of the ratings
in particular, it weights the contributions of ratings in proportion to the users' degree of indifference towards the items. Additionally, to address the sparsity problem that affects the performance of CF techniques, we propose a switching hybrid method that predicts user ratings based on either our custom similarity measure or through user and item biases. We evaluated the proposed method on six different datasets and compared it with other CF methods. The results show that the proposed recommender consistently outperforms those using conventional similarity measures when the sparsity of the dataset is high.
Research on highly parallel embedded control system design and implementation method Invited
Masato Edahiro, Masaki Gondo
Impact Vol. 2019 ( 10 ) page: 44-46 2019.12
More details
Language:English Publishing type:Research paper (scientific journal)
Model-based Parallelization for Simulink Models on Multicore CPUs and GPUs Reviewed
Z. Zhong and M. Edahiro
Proceedings of International SoC Design Conference (ISOCC 2019) page: DAS3-1 2019.10
More details
Language:English
Model-based Parallelization for Simulink Models on Multicore CPUs and GPUs Reviewed
Z. Zhong, M. Edahiro
Proceedings of International SoC Design Conference (ISOCC 2019) page: DAS3-1 2019.10
More details
Language:English Publishing type:Research paper (other academic)
Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors Reviewed
Z. Zhong, M. Edahiro
International Journal of Computer & Technology Vol. 19 page: 7470-7484 2019.2
More details
Language:English Publishing type:Research paper (scientific journal)
Traffic light recognition using high-definition map features Reviewed
M. Hirabayashi, A. Sujiwo, A. Monrroy, S. Kato, M. Edahiro
Journal of Robotics and Autonomous Systems Vol. 111 page: 62-72 2019.1
More details
Language:English Publishing type:Research paper (scientific journal)
Analysis of Memory System of Tiled Many-core Processors Reviewed
Y. Liu, S. Kato, M. Edahiro
IEEE Access 2019.1
More details
Language:English Publishing type:Research paper (scientific journal)
Traffic light recognition using high-definition map features Reviewed
M. Hirabayashi, A. Sujiwo, A. Monrroy, S. Kato, M. Edahiro
Journal of Robotics and Autonomous Systems Vol. 111 page: 62-72 2019.1
More details
Language:English Publishing type:Research paper (scientific journal)
Analysis of Memory System of Tiled Many-core Processors Reviewed
Y. Liu, S. Kato, M. Edahiro
IEEE Access Vol. 7 page: 18964 - 18977 2019
More details
Language:English Publishing type:Research paper (scientific journal)
Optimization of the Load Balancing Policy for Tiled Many-core Processors Reviewed
Y. Liu, S. Kato, M. Edahiro
IEEE Access Vol. 7 page: 10176 - 10188 2019
More details
Language:English Publishing type:Research paper (scientific journal)
Optimization of the Load Balancing Policy for Tiled Many-core Processors Reviewed
Y. Liu, S. Kato, M. Edahiro
IEEE Access Vol. 7 page: 10176 - 10188 2018.12
More details
Language:English Publishing type:Research paper (scientific journal)
Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors Reviewed
Z. Zhong, M. Edahiro
Proceedings of International SoC Design Conference (ISOCC 2018) page: DAS2-2 2018.11
More details
Language:English
Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors Reviewed
Z. Zhong, M. Edahiro
Proceedings of International SoC Design Conference (ISOCC 2018) page: DAS2-2 2018.11
More details
Language:English Publishing type:Research paper (other academic)
GPU-Accelerated VoltDB: A Case for Indexed Nested Loop Join Reviewed
N. Anh, M. Edahiro and S. Kato
Proceedings of the 2018 International Conference on High Performance Computing & Simulation (HPCS 2018) page: 204 - 212 2018.7
More details
Remapping Method to Minimize Makespan of Simulink Model for Embedded Multi-core Systems Reviewed
S. Kojima, M. Edahiro, and T. Azumi
Proceedings of the 33rd International Conference on Computers and Their Applications (CATA2018) page: T-P1-1 2018.3
More details
Language:English
Remapping Method to Minimize Makespan of Simulink Model for Embedded Multi-core Systems Reviewed
S. Kojima, M. Edahiro, T. Azumi
Proceedings of the 33rd International Conference on Computers and Their Applications (CATA2018) page: T-P1-1 2018.3
More details
Language:English Publishing type:Research paper (other academic)
組込み制御システムに対するマルチコア向けモデルレベル自動並列化手法 Reviewed
鍾兆前,枝廣正人
情報処理学会論文誌 Vol. 59 ( 2 ) page: 735-747 2018.2
More details
Language:Japanese Publishing type:Research paper (scientific journal)
組込み制御システムに対するマルチコア向けモデルレベル自動並列化手法 Reviewed
鍾兆前, 枝廣正人
情報処理学会論文誌 Vol. 59 ( 2 ) page: 735-747 2018.2
More details
Language:Japanese Publishing type:Research paper (scientific journal)
GPU-Accelerated VoltDB: A Case for Indexed Nested Loop Join Reviewed
N. Anh, M. Edahiro, S. Kato
Proceedings of the 2018 International Conference on High Performance Computing & Simulation (HPCS 2018) page: 204 - 212 2018
More details
Language:English Publishing type:Research paper (other academic)
Other Link: https://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2018.html#NguyenEK18
Is the Heap Manager Important to Many Cores?
Ye Liu 0003, Shinpei Kato, Masato Edahiro
page: 5 - 6 2018
More details
Publishing type:Research paper (international conference proceedings)
Other Link: https://dblp.uni-trier.de/db/conf/hpdc/ross2018.html#LiuKE18
Localization Based on Multiple Visual-Metric Maps Reviewed
A. Sujiwo, E. Takeuchi, L. Y. Morales, N. Akai, Y. Ninomiya, M. Edahiro
Proceedings of International Conference on Multisensor Fusion and Integration for Intelligent Systems (MFI 2017) page: 212-219 2017.11
More details
Language:English
Localization Based on Multiple Visual-Metric Maps Reviewed
A. Sujiwo, E. Takeuchi, L. Y. Morales, N. Akai, Y. Ninomiya, M. Edahiro
Proceedings of International Conference on Multisensor Fusion and Integration for Intelligent Systems (MFI 2017) page: 212-219 2017.11
More details
Language:English Publishing type:Research paper (other academic)
モデルベース開発におけるクロスレイヤ設計手法のマルチコア上モータ制御実装への適用 Reviewed
竹松慎弥, 鍾 兆前, 井上雅理, 横山静香, 小島流石, 近藤真己, ECソリューションイノベータ, 中本幸一, 安積卓也, 道木慎二, 本田晋也, 枝廣正人
組込みシステムシンポジウム(ESS2017) page: ポスター(26) 2017.8
More details
Language:Japanese Publishing type:Research paper (other academic)
Robust and Accurate Monocular Vision-Based Localization in Outdoor Environments of Real-World Robot Challenge Reviewed
A. Sujiwo, E. Takeuchi, L. Y. Morales, N. Akai, H. Darweesh, Y. Ninomiya, and M. Edahiro
Journal of Robotics and Mechatronics Vol. 29 ( 4 ) page: 685-696 2017.8
More details
Language:English Publishing type:Research paper (scientific journal)
Robust and accurate monocular vision-based localization in outdoor environments of real-world robot challenge Reviewed
Adi Sujiwo, Eijiro Takeuchi, Luis Yoichi Morales, Naoki Akai, Hatem Darweesh, Yoshiki Ninomiya, Masato Edahiro
Journal of Robotics and Mechatronics Vol. 29 ( 4 ) page: 685 - 696 2017.8
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:Fuji Technology Press
This paper describes our approach to perform robust monocular camera metric localization in the dynamic environments of Tsukuba Challenge 2016. We address two issues related to vision-based navigation. First, we improved the coverage by building a custom vocabulary out of the scene and improving upon place recognition routine which is key for global localization. Second, we established possibility of lifelong localization by using previous year’s map. Experimental results show that localization coverage was higher than 90% for six different data sets taken in different years, while localization average errors were under 0.2 m. Finally, the average of coverage for data sets tested with maps taken in different years was of 75%.
Pure Pursuit Revisited: Field Testing of Autonomous Vehicles in Urban Areas Reviewed
H. Ohta, N. Akai, E. Takeuchi, S. Kato and M. Edahiro
Proceedings of the 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'16) page: 7-12 2016.10
More details
Language:English
GPU-accelerated Index Nested Loop Join on VoltDB Reviewed
N. Anh, S. Kato and M. Edahiro
Proceedings of the 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'16) Vol. WIP page: 6 2016.10
More details
Language:English
A Feature Outlier Identification Method for Multi-object Tracking Reviewed
A. Monrroy, S. Kato and M. Edahiro
Proceedings of the 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'16) Vol. WIP page: 5 2016.10
More details
Language:English
A Feature Outlier Identification Method for Multi-object Tracking Reviewed
A. Monrroy, S. Kato, M. Edahiro
Proceedings of the 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'16) Vol. WIP page: 5 2016.10
More details
Language:English Publishing type:Research paper (other academic)
GPU-accelerated Index Nested Loop Join on VoltDB Reviewed
N. Anh, S. Kato, M. Edahiro
Proceedings of the 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'16) Vol. WIP page: 6 2016.10
More details
Language:English Publishing type:Research paper (other academic)
A Scalability Analysis of Many Cores and On-chip Mesh Networks on the TILE-Gx Platform Reviewed
Y. Liu, H. Sasaki, S. Kato, and M. Edahiro
Proceedings of IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) page: 46-52 2016.9
More details
Language:English
Monocular Vision-Based Localization Using ORB-SLAM with LIDAR-Aided Mapping in Real-World Robot Challenge Reviewed
A. Sujiwo, T. Ando, E. Takeuchi, Y. Ninomiya and M. Edahiro
Journal of Robotics and Mechatronics Vol. 28 ( 4 ) page: 479-490 2016.8
More details
Language:English Publishing type:Research paper (scientific journal)
Monocular Vision-Based Localization Using ORB-SLAM with LIDAR-Aided Mapping in Real-World Robot Challenge Reviewed
A. Sujiwo, T. Ando, E. Takeuchi, Y. Ninomiya, M. Edahiro
Journal of Robotics and Mechatronics Vol. 28 ( 4 ) page: 479-490 2016.8
More details
Language:English Publishing type:Research paper (scientific journal)
Accelerated Deformable Part Models on GPUs Reviewed
M. Hirabayashi, S. Kato, M. Edahiro, K. Takeda, and S. Mita
IEEE Transactions on Parallel & Distributed Systems Vol. 27 ( 6 ) page: 1589-1602 2016.6
More details
Language:English Publishing type:Research paper (scientific journal)
Accelerated Deformable Part Models on GPUs Reviewed
Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Kazuya Takeda, Seiichi Mita
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Vol. 27 ( 6 ) page: 1589 - 1602 2016.6
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:IEEE COMPUTER SOC
Object detection is a fundamental challenge facing intelligent applications. Image processing is a promising approach to this end, but its computational cost is often a significant problem. This paper presents schemes for accelerating the deformable part models (DPM) on graphics processing units (GPUs). DPM is a well-known algorithm for image-based object detection, and it achieves high detection rates at the expense of computational cost. GPUs are massively parallel compute devices designed to accelerate dataparallel compute-intensive workload. According to an analysis of execution times, approximately 98 percent of DPM code exhibits loop processing, which means that DPM could be highly parallelized by GPUs. In this paper, we implement DPM on the GPU by exploiting multiple parallelization schemes. Results of an experimental evaluation of this GPU-accelerated DPM implementation demonstrate that the best scheme of GPU implementations using an NVIDIA GPU achieves a speed up of 8.6x over a naive CPU-based implementation.
A scalability analysis of many cores and on-chip mesh networks on the TILE-Gx platform Reviewed
Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro
2016 IEEE 10TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC) page: 46 - 52 2016
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing manycore processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor.
We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the twodimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.
Parallel Design of Feedback Control Systems Utilizing Dead Time for Embedded Multicore Processors
SUZUKI Yuta, SATA Kota, KAKO Jun'ichi, YAMAGUCHI Kohei, ARAKAWA Fumio, EDAHIRO Masato
IEICE Transactions on Electronics Vol. E99.C ( 4 ) page: 491 - 502 2016
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:The Institute of Electronics, Information and Communication Engineers
This paper presents a parallelization method utilizing dead time to implement higher precision feedback control systems in multicore processors. The feedback control system is known to be difficult to parallelize, and it is difficult to deal with the dead time in control systems. In our method, the dead time is explicitly represented as delay elements. Then, these delay elements are distributed to the overall systems with equivalent transformation so that the system can be simulated or executed in parallel pipeline operation. In addition, we introduce a method of delay-element addition for parallelization. For a spring-mass-damper model with a dead time, parallel execution of the model using our technique achieves 3.4 times performance acceleration compared with its sequential execution on an ideal four-core simulation and 1.8 times on a cycle-accurate simulator of a four-core embedded processor as a threaded application on a real-time operating system.
Pure Pursuit Revisited: Field Testing of Autonomous Vehicles in Urban Areas Reviewed
Hiroki Ohta, Naoki Akai, Eijiro Takeuchi, Shinpei Kato, Masato Edahiro
PROCEEDINGS OF 2016 IEEE 4TH INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS (CPSNA) page: 7 - 12 2016
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
In this paper, we aim to explore path following. We implement a path following component by referring to the existing Pure Pursuit algorithm. Using the simulation and field operational test, we identified the problem in the path following component. The main problems identified were with respect to vehicles meandering off the path, turning a corner, and the instability of steering control. Therefore, we apply some modifications to the Pure Pursuit[1] algorithm. We have also conducted the simulation and field operational tests again to evaluate these modifications.
Simulinkモデルからのブロックレベル並列化 Reviewed
山口 滉平,竹松 慎弥,池田 良裕,李 瑞徳,鍾 兆前,近藤 真己(NEC情報システムズ),枝廣 正人
組込みシステムシンポジウム (ESS2015) page: ポスター(21) 2015.10
More details
Language:Japanese
Simulinkモデルからのブロックレベル並列化 Reviewed
山口 滉平, 竹松 慎弥, 池田 良裕, 李 瑞徳, 鍾 兆前, 近藤 真己, C情報システムズ, 枝廣 正人
組込みシステムシンポジウム (ESS2015) page: ポスター(21) 2015.10
More details
Language:Japanese Publishing type:Research paper (other academic)
System-level design method for control systems with hardware-implemented interrupt handler Reviewed
Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro
Journal of Information Processing Vol. 23 ( 5 ) page: 532 - 541 2015.9
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:Information Processing Society of Japan
In this paper, we propose a system-level design method for control systems that enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to a deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates the target implementation from the model. Case studies on a motor control system show that the proposed method reduces the processor load, improves the latency of the interrupt processing, and enables the design space exploration for the control system.
System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler Reviewed
Y. Ando, S. Honda, H. Takada and M. Edahiro
Journal of Information Processing Vol. 23 ( 5 ) page: 532-541 2015.9
More details
Language:English Publishing type:Research paper (scientific journal)
HexaCam: An FPGA-based Multi-view Camera System Reviewed
A. Monrroy, M. Hirabayashi, S. Kato, M. Edahiro, T. Miyoshi and S. Funada
Proceedings of the 3rd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'15) page: 48-53 2015.8
More details
Language:English
Real-Time Visualization of Moving Objects Reviewed
P. Ortal, S. Kato, and M. Edahiro
Proceedings of the 3rd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'15) page: 60-65 2015.8
More details
Language:English
Automatic synthesis of inter-heterogeneous-processor communication for programmable system-on-chip Reviewed
Y. Ando, Y. Ishida, S. Honda, H. Takada and M. Edahiro
IPSJ Transactions on System LSI Design Methodology Vol. 8 page: 95-99 2015.8
More details
Language:English Publishing type:Research paper (scientific journal)
Automatic synthesis of inter-heterogeneous-processor communication for programmable system-on-chip Reviewed
Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro
IPSJ Transactions on System LSI Design Methodology Vol. 8 page: 95-99 2015.8
More details
Language:English Publishing type:Research paper (scientific journal)
階層構造を持つメニーコアアーキテクチャへのタスクマッピング Reviewed
油谷 創, 枝廣 正人
情報処理学会論文誌 Vol. 56 ( 8 ) page: 1568-1581 2015.8
More details
Language:Japanese Publishing type:Research paper (scientific journal)
階層構造を持つメニーコアアーキテクチャへのタスクマッピング Reviewed
油谷 創, 枝廣 正人
情報処理学会論文誌 Vol. 56 ( 8 ) page: 1568-1581 2015.8
More details
Language:Japanese Publishing type:Research paper (scientific journal)
Design Space Exploration of Control System with Hardware-implemented Interrupt Handler Reviewed
Y. Ando, S. Honda, H. Takada, M. Edahiro
Proceedings of International Conference on Information and Communication Technology for Embedded Systems (IC-ICTES) page: 1-6 2015.3
More details
Language:English
Implementation and evaluation of AES/ADPCM on STP and FPGA with High-level Synthesis Reviewed
Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro
Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page: 415-420 2015.3
More details
Language:English
Profiler for Control System in System Level Design Reviewed
T-D Miaw, Y. Ando, S. Honda, H. Takada, M. Edahiro
Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page: 46-51 2015.3
More details
Language:English
Implementation and evaluation of AES/ADPCM on STP and FPGA with High-level Synthesis Reviewed
Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro
Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page: 415-420 2015.3
More details
Language:English Publishing type:Research paper (other academic)
Profiler for Control System in System Level Design Reviewed
T-D Miaw, Y. Ando, S. Honda, H. Takada, M. Edahiro
Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page: 46-51 2015.3
More details
Language:English Publishing type:Research paper (other academic)
Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip Reviewed
Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro
Proceeding. of IEEE International Conference on VLSI Systems, Architecture, Technology and Applications page: 1-6 2015.1
More details
Language:English
Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip Reviewed
Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro
Proceeding. of IEEE International Conference on VLSI Systems, Architecture, Technology and Applications page: 1-6 2015.1
More details
Language:English Publishing type:Research paper (other academic)
Design Space Exploration of Control System with Hardware-implemented Interrupt Handler Reviewed
Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro
2015 6TH INTERNATIONAL CONFERENCE OF INFORMATION AND COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS (IC-ICTES) page: 1-6 2015
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
In this paper, we propose a system-level design tool for control systems that enables the development of hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. Case studies on a motor control system show that the proposed method enables the designer to explore design space of control system, reduces the processor load and improves the latency of the interrupt processing.
HexaCam: An FPGA-based Multi-view Camera System Reviewed
Abraham Monrroy, Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Takefumi Miyoshi, Satoshi Funada
2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015 page: 48 - 53 2015
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
Accurate perception information of the surroundings is a desirable feature in any cyber-physical system for autonomous robotics. Besides, providing a cost-wise solution to this need, is also useful for developing other kinds of applications such as mapping, decision-making, self-localization, among others. In this work, we present and benchmark a cost-effective camera device with six image sensors attached to a custom built FPGA board. The perception information is delivered on the host side, thanks to a HOG based object detector executed on the GPU. Our conclusion is that the low cost prototype is able to acquire and extract the perception data in 9.41 frames per second.
Real-Time Visualization of Moving Objects Reviewed
Patricia Ortal, Shinpei Kato, Masato Edahiro
2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015 page: 60 - 65 2015
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
The development of visualization tools that help us assimilate the information that surrounds us is essential in business environments and most research fields. Data visualization is a powerful tool that lets us recognize patterns and trends easily, allows us to extract sensible information faster, stimulates hypothesis generation, and helps us make effective decisions. This paper describes the design and implementation of a web application that displays moving objects in real-time using Google Maps. This web application was done as part of an integrated system that addresses issues related to the automated driver assistance field. Moreover, this work seeks to be a reference framework that will provide visual support for researchers in the area of mobility looking to analyze moving object trajectories, evaluate prediction models, or explain their results.
制御システムのマルチ・メニーコアプロセッサ実装 Invited
枝廣 正人
計測と制御 Vol. 53 ( 12 ) page: 1111-1116 2014.12
More details
Authorship:Lead author Language:Japanese
制御システムのマルチ・メニーコアプロセッサ実装 Invited
枝廣 正人
計測と制御 Vol. 53 ( 12 ) page: 1111-1116 2014.12
More details
Language:Japanese Publishing type:Research paper (scientific journal)
Exploring the Problem of GPU Programming for Data-Intensive Applications: A Case Study of Multiple Expectation Maximization for Motif Elicitation Reviewed
Y. Kitsukawa, M. Hirabayashi, S. Kato, and M. Edahiro
Proceedings of the fifth symposium on Information and Communication Technology (SoICT2014) page: 256-262 2014.12
More details
Language:English
Exploring the problem of GPU programming for data-intensive applications: A case study of multiple expectation maximization for motif elicitation Reviewed
Yuki Kitsukawa, Manato Hirabayashi, Shinpei Kato, Masato Edahiro
ACM International Conference Proceeding Series Vol. 04-05- page: 256 - 262 2014.12
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:Association for Computing Machinery
Recently General-Purpose Computing on Graphics Processing Units (GPGPU) has been used to reduce the processing time of various applications, but the degree of acceleration by the Graphical Processing Unit (GPU) depends on the application. This study focuses on data analysis as an application example of GPGPU, specifically, the design and implementation of GPGPU computation libraries for data-intensive workloads. The effects of efficient memory allocation and high-speed read-only memories on the execution time are evaluated. In addition to employing a single GPU, the scalability using multiple GPUs is also evaluated. Compared to a Central Processing Unit (CPU) alone, the memory allocation method reduces the execution time for memory copies by approximately 60% when a GPU is used, while utilizing read-only memories results in an approximately 20% reduction in the overall program execution time. Moreover, expanding the number of GPUs from one to four reduces the execution time by approximately 10%.
Simple One-to-one Architecture for Parallel Execution of Embedded Control Systems Reviewed
R. Nakamura, F. Arakawa, and M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: 25-30 2014.8
More details
Language:English
GPU-accelerated Point Cloud Mapping for Autonomous Driving Reviewed
Y. Kitsukawa, S. Kato, and M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: WiP Session 2014.8
More details
Language:English
Evaluation of GNSS for Autonomous Driving Reviewed
H. Ohta, S. Kato, and M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: WiP Session 2014.8
More details
Language:English
Evaluation of GNSS for Autonomous Driving Reviewed
H. Ohta, S. Kato, M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: WiP Session 2014.8
More details
Language:English Publishing type:Research paper (other academic)
Simple One-to-one Architecture for Parallel Execution of Embedded Control Systems Reviewed
R. Nakamura, F. Arakawa, M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: 25-30 2014.8
More details
Language:English Publishing type:Research paper (other academic)
GPU-accelerated Point Cloud Mapping for Autonomous Driving Reviewed
Y. Kitsukawa, S. Kato, M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: WiP Session 2014.8
More details
Language:English Publishing type:Research paper (other academic)
Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors Reviewed
Y. Suzuki, K. Sata (Toyota), J. Kako (Toyota), K. Yamaguchi, F. Arakawa, and M. Edahiro
Proceedings of COOL Chips XVII page: VI-2 2014.4
More details
Language:English
Power and Performance Characterization and Modeling of GPU-accelerated Systems Reviewed
Y. Abe, H. Sasaki, S. Kato, K. Inoue, M. Edahiro, and M. Peres
Proceedings of the 28th IEEE International Parallel and Distributed Processing Symposium (IPDPS'14) page: 113-122 2014.3
More details
Language:English
Establishing a standard interface between multi-manycore and software tools - SHIM Reviewed
Masaki Gondo, Fumio Arakawa, Masato Edahiro
2014 IEEE COOL CHIPS XVII page: VI-1 2014
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
The multi core processors are becoming norm and a processor with even more than a hundred of cores are emerging. These inherently require wide range of software tools to help software developers. However, supporting these complex hardware by the tools require significant effort by the tool vendors, and each invest in adapting the new hardware by modifying their tools or creating proprietary configuration files, while often the similar set of hardware architectural information are needed. The SHIM, Software-Hardware Interface for Multi-many-core, is a joint industrial and academic effort to standardize the interface between the multicore hardware and the software tools. This extended abstract introduces SHIM, the overall architecture, the schema used, the use-cases, and a prototype tool to foster the adaption of the interface.
Power and Performance Characterization and Modeling of GPU-Accelerated Systems Reviewed
Yuki Abe, Koji Inoue, Hiroshi Sasaki, Masato Edahiro, Shinpei Kato, Martin Peres
2014 IEEE 28TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM page: 113-122 2014
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
Graphics processing units (GPUs) provide an order-of-magnitude improvement on peak performance and performance-per-watt as compared to traditional multicore CPUs. However, GPU-accelerated systems currently lack a generalized method of power and performance prediction, which prevents system designers from an ultimate goal of dynamic power and performance optimization. This is due to the fact that their power and performance characteristics are not well captured across architectures, and as a result, existing power and performance modeling approaches are only available for a limited range of particular GPUs. In this paper, we present power and performance characterization and modeling of GPU-accelerated systems across multiple generations of architectures. Characterization and modeling both play a vital role in optimization and prediction of GPU-accelerated systems. We quantify the impact of voltage and frequency scaling on each architecture with a particularly intriguing result that a cutting-edge Kepler-based GPU achieves energy saving of 75% by lowering GPU clocks in the best scenario, while Fermi-and Tesla-based GPUs achieve no greater than 40% and 13%, respectively. Considering these characteristics, we provide statistical power and performance modeling of GPU-accelerated systems simplified enough to be applicable for multiple generations of architectures. One of our findings is that even simplified statistical models are able to predict power and performance of cutting-edge GPUs within errors of 20% to 30% for any set of voltage and frequency pair.
Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors Reviewed
Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro
2014 IEEE COOL CHIPS XVII page: VI-2 2014
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.
Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors Reviewed
Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro
2014 IEEE COOL CHIPS XVII Vol. E99-C ( 4 ) page: 491-502 2014
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.
Data Transfer Matters for GPU Computing Reviewed
Y. Fujii, T. Azumi, N. Nishio, and S. Kato, and M. Edahiro
Proceedings of the 19th IEEE International Conference on Parallel and Distributed Systems (ICPADS'13) page: 275 - 282 2013.12
More details
Language:English
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, and Hiroaki Takada
International Journal of Reconfigurable Computing Vol. 2013 page: ID: 789134 2013.10
More details
Language:English Publishing type:Research paper (scientific journal)
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada
International Journal of Reconfigurable Computing Vol. 2013 page: ID: 789134 2013.10
More details
Language:English Publishing type:Research paper (scientific journal)
GPU Implementations of Object Detection using HOG Features and Deformable Models Reviewed
M. Hirabayashi, S. Kato, M. Edahiro, K. Takeda, T. Kawano, and S. Mita
Proceedings of the 1st IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'13) page: 106-111 2013.8
More details
Language:English
Data Transfer Matters for GPU Computing Reviewed
Yusuke Fujii, Takuya Azumi, Nobuhiko Nishio, Shinpei Kato, Masato Edahiro
2013 19TH IEEE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS 2013) page: 275 - 282 2013
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
Graphics processing units (GPUs) embrace many-core compute devices where massively parallel compute threads are offloaded from CPUs. This heterogeneous nature of GPU computing raises non-trivial data transfer problems especially against latency-critical real-time systems. However even the basic characteristics of data transfers associated with GPU computing are not well studied in the literature. In this paper, we investigate and characterize currently-achievable data transfer methods of cutting-edge GPU technology. We implement these methods using open-source software to compare their performance and latency for real-world systems. Our experimental results show that the hardware-assisted direct memory access (DMA) and the I/O read-and-write access methods are usually the most effective, while on-chip microcontrollers inside the GPU are useful in terms of reducing the data transfer latency for concurrent multiple data streams. We also disclose that CPU priorities can protect the performance of GPU data transfers.
Evaluation of power consumption at execution of multiple automatically parallelized and power controlled media applications on the RP2 low-power multicore Reviewed
Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) Vol. 7146 page: 31 - 45 2013
More details
Language:English Publishing type:Research paper (international conference proceedings)
This paper evaluates an automatic power reduction scheme of OSCAR automatic parallelizing compiler having power reduction control capability when multiple media applications parallelized by the OSCAR compiler are executed simultaneously on RP2, a 8-core multicore processor developed by Renesas Electronics, Hitachi, and Waseda University. OSCAR compiler enables the hierarchical multigrain parallel processing and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating and power gating for each processor core using the OSCAR multi-platform API. The RP2 has eight SH4A processor cores, each of which has power control mechanisms such as DVFS, clock gating and power gating. First, multiple applications with relatively light computational load are executed simultaneously on the RP2. The average power consumption of power controlled eight AAC encoder programs, each of which was executed on one processor, was reduced by 47%, (to 1.01W), against one AAC encoder execution on one processor (from 1.89W) without power control. Second, when multiple intermediate computational load applications are executed, the power consumptions of an AAC encoder executed on four processors with the power reduction control was reduced by 57% (to 0.84W) against an AAC encoder execution on one processor (from 1.95W). Power consumptions of one MPEG2 decoder on four processors with power reduction control was reduced by 49% (to 1.01W) against one MPEG2 decoder execution on one processor (from 1.99W). Finally, when a combination of a high computational load application program and an intermediate computational load application program are executed simultaneously, the consumed power reduced by 21% by using twice number of cores for each application. This paper confirmed parallel processing and power reduction by OSCAR compiler are efficient for multiple application executions. In execution of multiple light computational load applications, power consumption increases only 12% for one application. Parallel processing being applied to intermediate computational load applications, power consumption of executing one application on one processor core (1.49W) is almost same power consumption of two applications on eight processor cores (1.46W). © 2013 Springer-Verlag.
GPU implementations of object detection using HOG features and deformable models Reviewed
Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Kazuya Takeda, Taiki Kawano, Seiichi Mita
2013 IEEE 1st International Conference on Cyber-Physical Systems, Networks, and Applications, CPSNA 2013 page: 106 - 111 2013
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE Computer Society
Vision-based object detection using camera sensors is an essential piece of perception for autonomous vehicles. Various combinations of features and models can be applied to increase the quality and the speed of object detection. A well-known approach uses histograms of oriented gradients (HOG) with deformable models to detect a car in an image [15]. A major challenge of this approach can be found in computational cost introducing a real-time constraint relevant to the real world. In this paper, we present an implementation technique using graphics processing units (GPUs) to accelerate computations of scoring similarity of the input image and the pre-defined models. Our implementation considers the entire program structure as well as the specific algorithm for practical use. We apply the presented technique to the real-world vehicle detection program and demonstrate that our implementation using commodity GPUs can achieve speedups of 3x to 5x in frame-rate over sequential and multithreaded implementations using traditional CPUs. © 2013 IEEE.
Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework Reviewed
Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro and Hiroaki Takada
IPSJ Transactions on System LSI Design Methodology. Vol. 5 page: 133-142 2012.8
More details
Language:English Publishing type:Research paper (scientific journal)
Comparison of Preemption Schemes for Partially Reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
IEEE Embedded Systems Letters Vol. 4 ( 2 ) page: 45-48 2012.6
More details
Language:English Publishing type:Research paper (scientific journal)
Calculating Average Joint Hamming Weight for Minimal Weight Conversion of d Integers Reviewed
V. Suppakitpaisarn, M. Edahiro and H. Imai
WALCOM: Algorithms and Computation, Springer, 2012, Lecture Notes in Computer Science Vol. 7157 page: 229-240 2012.2
More details
Language:English
Fast Elliptic Curve Cryptography Using Minimal Weight Conversion of d Integers Reviewed
V. Suppakitpaisarn, M. Edahiro and H. Imai
Proceedings of the Tenth Australasian Information Security Conference (AISC 2012), ACS, 2012, Conferences in Research and Practice in Information Technology Vol. 125 page: 15-26 2012.1
More details
Language:English
Fast Elliptic Curve Cryptography Using Minimal Weight Conversion of d Integers Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
Proceedings of the Tenth Australasian Information Security Conference (AISC 2012), ACS, 2012, Conferences in Research and Practice in Information Technology Vol. 125 page: 15-26 2012.1
More details
Language:English Publishing type:Research paper (other academic)
Toward GPU-accelerated Traffic Simulation and Its Real-Time Challenge Reviewed
Manato Hirabayashi, Shinpei Kato, Masato Edahiro and Yuki Sugiyama
International Workshop on Real-Time and Distributed Computing in Emerging Applications (REACTION2012) page: 1-6 2012
More details
Language:English
Fast Elliptic Curve Cryptography Using Optimal Double-Base Chains Reviewed
V. Suppakitpaisarn, M. Edahiro and H. Imai
Proceedings of the International Conference on Informatics & Applications (ICIA2012) page: 190-204 2012
More details
Language:English
Fastest Multi-Scalar Multiplication Based on Double-Base Chain Reviewed
V. Suppakitpaisarn, M. Edahiro and H. Imai
World Congress on Internet Security (WorldCIS-2012) page: 93-98 2012
More details
Language:English
Optimal Elliptic Curve Cryptography Using Fibonacci Sequence Reviewed
V. Suppakitpaisarn, M. Edahiro and H. Imai
Proceedings of the 5th Thailand-Japan International Academic Conference (TJIA2012) page: 未登録 2012
More details
Language:English
Optimal Elliptic Curve Scalar Multiplication Using Double-Base Chains Reviewed
V. Suppakitpaisarn, M. Edahiro and H. Imai
International Journal of Digital Information and Wireless Communications (IJDIWC) Vol. 2 ( 1 ) page: 923-942 2012
More details
Language:English Publishing type:Research paper (scientific journal)
Calculating average joint hamming weight for minimal weight conversion of d integers Reviewed
Vorapong Suppakitpaisarn, Masato Edahiro, Hiroshi Imai
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) Vol. 7157 page: 229 - 240 2012
More details
Language:English Publishing type:Research paper (international conference proceedings)
In this paper, we propose an algorithm to calculate the efficiency of number representations in elliptic curve cryptography, average joint Hamming weight. The method uses Markov chains generated from a minimal weight conversion algorithm of d integers using the minimal weight conversion. With redundant representations using digit sets like {0, ±1}, it is possible to reduce computation time of the cryptosystem. Although larger digit sets make the computation time shorter, it requires longer preprocessing time. Therefore, the average joint Hamming weight is useful to evaluate digit sets. The Markov chains to find the average joint Hamming weight are derived automatically from the conversions. However, the number of states in these Markov chains is generally infinite. In [8], we propose an algorithm to reduce the number of states, but it is still unclear which representations the method can be applied for. In this paper, the finiteness of Markov chain with the existence of a stationary distribution is proven in a class of representation whose digit set D S be a finite set such that there exists a natural number Λ where D S ⊆ {0, ±1, ..., ±Λ} and {0,±1, ±Λ} ⊆ D S. The class covers most of the representation practically used in elliptic curve cryptography such as the representation which digit set are {0, ±1} and {0, ±1, ±3}. © 2012 Springer-Verlag.
Comparison of preemption schemes for partially reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
IEEE Embedded Systems Letters Vol. 4 ( 2 ) page: 45 - 48 2012
More details
Language:English Publishing type:Research paper (scientific journal)
Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization. © 2012 IEEE.
Efficient algorithms for extracting pareto-optimal hardware configurations in DEPS framework Reviewed
Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada
IPSJ Transactions on System LSI Design Methodology Vol. 5 page: 133 - 142 2012
More details
Language:English Publishing type:Research paper (scientific journal)
A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice. © 2012 Information Processing Society of Japan.
Optimal Elliptic Curve Scalar Multiplication Using Double-Base Chains Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
International Journal of Digital Information and Wireless Communications (IJDIWC) Vol. 2 ( 1 ) page: 923-942 2012
More details
Language:English Publishing type:Research paper (scientific journal)
Optimal Elliptic Curve Cryptography Using Fibonacci Sequence Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
Proceedings of the 5th Thailand-Japan International Academic Conference (TJIA2012) page: 未登録 2012
More details
Language:English Publishing type:Research paper (other academic)
Fastest Multi-Scalar Multiplication Based on Double-Base Chain Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
World Congress on Internet Security (WorldCIS-2012) page: 93-98 2012
More details
Language:English Publishing type:Research paper (other academic)
Fast Elliptic Curve Cryptography Using Optimal Double-Base Chains Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
Proceedings of the International Conference on Informatics & Applications (ICIA2012) page: 190-204 2012
More details
Language:English Publishing type:Research paper (other academic)
Toward GPU-accelerated Traffic Simulation and Its Real-Time Challenge Reviewed
Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Yuki Sugiyama
International Workshop on Real-Time and Distributed Computing in Emerging Applications (REACTION2012) page: 1-6 2012
More details
Language:English Publishing type:Research paper (other academic)
Rainbow - An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda and Hiroaki Takada
IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig) page: 416-421 2011.11
More details
Language:English
Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-power Multicore Reviewed
Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, and Hironori Kasahara
The 24th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2011) page: Session 1 2011.9
More details
Language:English
Rainbow: An OS extension for hardware multitasking on dynamically partially reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 page: 416 - 421 2011
More details
Language:English Publishing type:Research paper (international conference proceedings)
DPR (Dynamic Partial Reconfiguration) capability found in some of modern FPGAs allows implementation of a concept of a HW (Hardware) task, which similarly to its software counterpart has its state and shares time-multiplexed resources with the other tasks. While the new technology presents many advantages for embedded systems where run-time adaptability is an additional requirement, their efficient and easily portable implementations require a control software or an OS which would manage all the complexities of the underlying technology, providing an abstracted interface for the application programmer. This paper presents a novel and robust hardware multitasking extension for a conventional OS, managing task scheduling and configurations, and providing easy-to-use API (Application Programming Interface) for the application programmer. Scheduling is priority-based and takes advantage of task caching. Moreover, the extension is based on a developed design flow and embedded hardware platform allowing efficient task preemption, which can be utilized whenever it presents any benefits to the application. © 2011 IEEE.
A Robust Seamless Communication Architecture for Next-Generation Mobile Terminals on Multi-CPU SoCs Reviewed
Hiroaki Inoue, Junji Sakai, Masato Edahiro
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS Vol. 9 ( 3 ) 2010.2
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:ASSOC COMPUTING MACHINERY
We propose a robust seamless communication architecture that enables legacy mobile terminal software designed for single-CPU processors to be run on multi-CPU processors without any software modifications. This architecture features two new technologies: proxy processes, which help achieve the design of its user-level system-call hooking and a robust design method, which reduces bandwidth variation by systematic parameter optimization. Our evaluations confirmed that this architecture achieves fundamental features with satisfactory performance, that we have succeeded in getting actual mobile terminal software to run on three CPUs without modifying the software, and that the robust design method reduces bandwidth variation by 21%.
Optimal Average Joint Hamming Weight and Minimal Weight Conversion of d Integers.
Vorapong Suppakitpaisarn, Masato Edahiro, Hiroshi Imai
IACR Cryptology ePrint Archive Vol. 2010 page: 300 - 300 2010
More details
Publishing type:Research paper (scientific journal)
Other Link: https://dblp.uni-trier.de/db/journals/iacr/iacr2010.html#SuppakitpaisarnEI10
Parallelizing Fundamental Algorithms such as Sorting on Multi-core Processors for EDA Acceleration Reviewed
Masato Edahiro
PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 page: 230 - 233 2009
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
Fundamental algorithms should be parallelized to accelerate EDA software on multi-core architecture. In this paper, we introduce scalable algorithms that have scalability on multi-cores. As an example, a sorting algorithm, called Map Sort, is presented. This algorithm uses a map from subsets of input data to intervals on data range. Experimental results show that, in comparison with quick sort on a single CPU, processing time of Map Sort is comparable on a CPU and three times faster on four CPUs.
FIDES: An Advanced Chip Multiprocessor Platform for Secure Next Generation Mobile Terminals Reviewed
Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS Vol. 8 ( 1 ) 2008.12
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:ASSOC COMPUTING MACHINERY
We propose a secure platform on a chip multiprocessor, FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multigrained separation mechanisms. Four new technologies support the FIDES platform: bus filter logic, XIP kernels, policy separation, and dynamic access control. With these technologies, the FIDES platform can tolerate both application-level and kernel-level bugs on an actual download subsystem. Thus, the best-suited platform to secure next generation mobile terminals is FIDES.
MULTITASKING PARALLEL METHOD FOR HIGH-END EMBEDDED APPLIANCES Reviewed
Junji Sakai, Inoue Hiroaki, Sunao Torii, Masato Edahiro
IEEE MICRO Vol. 28 ( 5 ) page: 54 - 62 2008.9
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:IEEE COMPUTER SOC
EMBEDDED APPLIANCES SUCH AS HIGH-END CELL PHONES REQUIRE NOT ONLY HIGH PERFORMANCE BUT ALSO A PERFORMANCE GUARANTEE. THE AUTHORS DEMONSTRATE A PERFORMANCE GUARANTEE FRAMEWORK USING AN ASYMMETRIC MULTIPROCESSING APPROACH. THEY IMPLEMENTED THE PROPOSED METHOD ON A MULTICORE PROCESSOR USING LINUX. EVALUATION RESULTS SHOW THAT THE METHOD IMPROVES THE PERFORMANCE GUARANTEE WHILE MAINTAINING SOFTWARE COMPATIBILITY.
Processor virtualization for secure mobile terminals Reviewed
Hiroaki Inoue, Junji Sakai, Masato Edahiro
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS Vol. 13 ( 3 ) 2008.7
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:ASSOC COMPUTING MACHINERY
We propose a processor virtualization architecture, VIRTUS, to provide a dedicated domain for preinstalled applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies, namely, VMM asymmetrization, dynamic interdomain communication (IDC), and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor. Evaluations have shown that VMM asymmetrization results in significantly less performance degradation and LOC increase than do other VMMs. Further, dynamic IDC overhead is low enough, and virtualization-assist logic can be implemented in a sufficiently small area.
Towards scalable and secure execution platform for embedded systems Reviewed
Junji Sakai, Hiroaki Inoue, Masato Edahiro
PROCEEDINGS OF THE ASP-DAC 2007 page: 350 - + 2007
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
Reliability of embedded systems can be enhanced by multicore and partitioning approaches. Physical partitioning based on ANW multicore achieves runtime stability of multiple applications in a system and prevents the whole system shutdown as well even when a malicious code creeps in. Combined with logical partitioning by processor virtualization and SMP technologies, the multicore architecture could realize more flexible and more scalable platform for future embedded systems.
VIRTUS: A new processor virtualization architecture for security-oriented next-generation mobile terminals Reviewed
Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro
43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 page: 484 - + 2006
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:ASSOC COMPUTING MACHINERY
We propose a new processor virtualization architecture, VIRTUS, to provide a dedicated domain for pre-installed applications and virtualized domains for downloaded native applications. With it security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies: VMM asymmetrization, dynamic inter-domain communication and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor.
FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals Reviewed
Hiroaki, I, A Ikeno, M Kondo, J Sakai, M Edahiro
2005 INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS page: 178 - 183 2005
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:ASSOC COMPUTING MACHINERY
We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multi-grained separation mechanisms: coarse-grained processor-level separation of the basic-function domain from other domains for such downloaded applications, medium-grained OS-level separation, and fine-grained process-level separation within SELinux. Four new technologies, which include three enhancements to SELinux, support the FIDES platform: 1) bus filter logic for processor-level separation can be implemented as a small logic, 2) XIP kernels for memory-efficient OS-level separation can reduce memory requirements by 182%, 3) policy separation for enhanced process-level separation can apply policies 2.1 times faster at system boot-up, and 4) dynamic access control can provide secure Inter-Domain Communications (IDCs) with an overhead of only 4% for IDC system calls. We implemented SELinuxes on an ARM-based multiprocessor. Therefore, the best-suited platform to secure next generation mobile terminals is the FIDES platform, which can provide higher security as well as higher performance and lower power consumption on chip multiprocessors leading the current technology trend of microprocessors.
A new LSI Performance Prediction Model for interconnection analysis of future LSIs Reviewed
S Takahashi, M Edahiro, Y Hayashi
PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 page: 51 - 56 1998
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:IEEE
As the interconnection delays control the LSI performance, the LSI performance estimation at higher design level becomes more difficult. In this paper a new LSI performance model for the estimation is described, which is made up by adopting a new clack-skew model to the SUSPENS (Stanford University System Performance Simulator) model. Using the model, it is cleared that a specific block size, where the line delay overcomes the block cycle time, becomes shorter as the LSI generation proceeds.
AN EFFICIENT ZERO-SKEW ROUTING ALGORITHM Reviewed
M EDAHIRO
31ST DESIGN AUTOMATION CONFERENCE - PROCEEDINGS 1994 page: 375 - 380 1994
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:ASSOC COMPUTING MACHINERY
DCT/IDCT PROCESSOR FOR HDTV DEVELOPED WITH DSP SILICON COMPILER Reviewed
T MIYAZAKI, T NISHITANI, M EDAHIRO, ONO, I, K MITSUHASHI
JOURNAL OF VLSI SIGNAL PROCESSING Vol. 5 ( 2-3 ) page: 151 - 158 1993.4
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:KLUWER ACADEMIC PUBL
This article presents a discrete cosine transform (DCI) processor for high definition television (HDTV) by using an extended version of DSP Silicon Compiler. The extension is mainly concerned with module generation functions.A matrix-vector product module composed of multiply-accumulators (MACs) is newly added to the silicon compiler. The compiler accomplishes placement of leaf-cells and routing between the cells, referring to a prototype layout for the MAC. The prototype, which consists of a Booth multiplier and a carry look ahead adder, is carefully designed to attain high operation speed. The processor developed by the silicon compiler carries out 8 x 8 DCT and its inverse transform (IDCT). In order to evaluate the newly extended functions in the compiler, the architecture employed for the processor is based on the matrix-vector product method. By using DSP Silicon Compiler and 0.8 mum triple metal CMOS technology, the DCT processor is easily implemented with error-free environment and achieves a 50MHz data rate, which meets Japanese HDTV base line signal processing. The chip is implemented on a 12.80 x 12.57 mm2 area.
A CLUSTERING-BASED OPTIMIZATION ALGORITHM IN ZERO-SKEW ROUTINGS Reviewed
M EDAHIRO
30TH DESIGN AUTOMATION CONFERENCE : PROCEEDINGS 1993 page: 612 - 616 1993
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:ASSOC COMPUTING MACHINERY
DELAY MINIMIZATION FOR ZERO-SKEW ROUTING Reviewed
M EDAHIRO
1993 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS page: 563 - 566 1993
More details
Language:English Publishing type:Research paper (international conference proceedings) Publisher:I E E E, COMPUTER SOC PRESS
A BUCKETING ALGORITHM FOR THE ORTHOGONAL SEGMENT INTERSECTION SEARCH PROBLEM AND ITS PRACTICAL EFFICIENCY Reviewed
M EDAHIRO, K TANAKA, T HOSHINO, T ASANO
ALGORITHMICA Vol. 4 ( 1 ) page: 61 - 76 1989
More details
Language:English Publishing type:Research paper (scientific journal) Publisher:SPRINGER VERLAG
DOI: 10.1007/BF01553879
Practical use of Bucketing Techniques in Computational Geometry Reviewed
Takao Asano, Masato Edahiro, Hiroshi Imai, Masao Iri, Kazuo Murota
Machine Intelligence and Pattern Recognition Vol. 2 ( C ) page: 153 - 195 1985.1
More details
Language:English Publishing type:Research paper (scientific journal)
Techniques for using “buckets” to improve the efficiency of several computational-geometrical algorithms are described, together with examples illustrating the practical importance of the bucketing techniques. Specifically, they are applied to the problems of minimum-weight perfect matchings in the plane, two-dimensional Voronoi diagrams, point location and range search in the plane, and shortest paths in networks. © 1985, Elsevier Inc. All rights reserved.
A new pointlocation algorithm and its practical efficiency-comparison with existing algorithms
EDAHIRO M.
ACM Trans. Graphics Vol. 3 page: 86 - 109 1984
More details
枝廣 正人, 黒田 一朗, 情報処理学会組込みシステム研究会
CQ出版 2015 ( ISBN:9784789852227 )
More details
枝廣 正人, 黒田 一朗, 情報処理学会組込みシステム研究会
CQ出版 2009 ( ISBN:9784789845496 )
More details
マルチコアハンドブック応用編(第4-2章「開発環境」担当)
JEITAマイクロプロセッサ専門委員会( Role: Joint author)
JEITA 2010
More details
Language:Japanese
知識ベース「知識の森」(10群3編「システムオンチップ技術」編とりまとめ)
電子情報通信学会( Role: Joint author)
電子情報通信学会 2010
More details
Language:Japanese
マルチコアハンドブック応用編(第4-2章「開発環境」担当)
JEITAマイクロプロセッサ専門委員会( Role: Joint author)
JEITA 2010
More details
Responsible for pages:(第4-2章「開発環境」を担当) Language:Japanese
知識ベース「知識の森」(10群3編「システムオンチップ技術」編とりまとめ)
電子情報通信学会( Role: Joint author)
電子情報通信学会 2010
More details
Responsible for pages:(10群3編「システムオンチップ技術」編のとりまとめと一部執筆を担当) Language:Japanese
組込みプロセッサ技術
枝廣 正人, 黒田 一朗( Role: Joint author)
CQ出版社「組込みシステム基礎技術全集 vol. 2」 2009.3 ( ISBN:978-4-7898-4549-6 )
More details
Language:Japanese
組込みプロセッサ技術
枝廣 正人, 黒田 一朗( Role: Joint author)
CQ出版社「組込みシステム基礎技術全集 vol. 2」 2009.3 ( ISBN:9784789845496 )
More details
Responsible for pages:(第8章の執筆を除く全体を担当) Language:Japanese
組込みシステム概論(第4章「ハードウェア要素技術」担当)
戸川 望, 高田 広章, 枝廣 正人, 沢田 篤史, 清水 徹, 中島 達夫, 平山 雅之( Role: Joint author)
CQ出版社「組込みシステム基礎技術全集 vol. 1」 2008.3 ( ISBN:978-4-7898-4550-2 )
More details
Language:Japanese
組込みシステム概論(第4章「ハードウェア要素技術」担当)
戸川 望, 高田 広章, 枝廣 正人, 沢田 篤史, 清水 徹, 中島 達夫, 平山 雅之( Role: Joint author)
CQ出版社「組込みシステム基礎技術全集 vol. 1」 2008.3 ( ISBN:9784789845502 )
More details
Responsible for pages:(第4章「ハードウェア要素技術」を担当) Language:Japanese
情報システムハンドブック(「幾何学的アルゴリズム」項目担当)
培風館( Role: Joint author)
培風館 2000
More details
Language:Japanese
情報システムハンドブック(「幾何学的アルゴリズム」項目担当)
培風館( Role: Joint author)
培風館 2000
More details
Responsible for pages:(「幾何学的アルゴリズム」の項目を担当) Language:Japanese
新編OR事典(「VLSIマルチスキャンチェイン最適化アルゴリズム」項目担当)
日本オペレーションズ・リサーチ学会( Role: Joint author)
日本オペレーションズ・リサーチ学会 1989
More details
Language:Japanese
新編OR事典(「VLSIマルチスキャンチェイン最適化アルゴリズム」項目担当)
日本オペレーションズ, リサーチ学会( Role: Joint author)
日本オペレーションズ・リサーチ学会 1989
More details
Responsible for pages:(「VLSIマルチスキャンチェイン最適化アルゴリズム」の項目を担当) Language:Japanese
Practical Use of Bucketing Techniques in Computational Geometry, Computational Geometry (G. T. Toussaint, ed.)
T. Asano, M. Edahiro, H. Imai, M. Iri, K. Murota( Role: Joint author)
North-Holland 1985
More details
Language:English
Practical Use of Bucketing Techniques in Computational Geometry, Computational Geometry (G. T. Toussaint, ed.)
T. Asano, M. Edahiro, H. Imai, M. Iri, K. Murota( Role: Joint author)
North-Holland 1985
More details
Responsible for pages:153-195 Language:English
複雑化するSoC上での制御設計を支援するSHIM標準化活動 Invited
枝廣 正人、権藤 正樹
システム/制御/情報 Vol. 66 ( 1 ) page: 21 - 26 2022.1
More details
Authorship:Lead author Language:Japanese Publishing type:Article, review, commentary, editorial, etc. (scientific journal)
Optimization of the Load Balancing Policy for Tiled Many-core Processors Reviewed
Y. Liu, S. Kato, M. Edahiro
IEEE Access 2018.12
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors Reviewed
Z. Zhong, M. Edahiro
Proceedings of International SoC Design Conference (ISOCC 2018) page: DAS2-2 2018.11
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Traffic light recognition using high-definition map features Reviewed
M. Hirabayashi, A. Sujiwo, A. Monrroy, S. Kato, M. Edahiro
Journal of Robotics and Autonomous Systems Vol. 111 page: 62 - 72 2018.11
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
組込み制御システムに対するマルチコア向けモデルレベル自動並列化手法 Reviewed
鍾兆前, 枝廣正人
情報処理学会論文誌 Vol. 59 ( 2 ) page: 735-747 2018.2
More details
Language:Japanese Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
Localization Based on Multiple Visual-Metric Maps Reviewed
A. Sujiwo, E. Takeuchi, L. Y. Morales, N. Akai, Y. Ninomiya, M. Edahiro
Proceedings of International Conference on Multisensor Fusion and Integration for Intelligent Systems (MFI 2017) page: 212-219 2017.11
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Relational Joins on GPUs: A Closer Look
Hideyuki Kawashima, Masato Edahiro, Shinpei Kato, Anh Nguyen, Makoto Yabuta
IEEE Transactions on Parallel and Distributed Systems Vol. 28 ( 9 ) page: 2663 - 2673 2017.9
More details
Language:English Publisher:IEEE
モデルベース開発におけるクロスレイヤ設計手法のマルチコア上モータ制御実装への適用 Reviewed
竹松慎弥, 鍾 兆前, 井上雅理, 横山静香, 小島流石, 近藤真己, ECソリューションイノベータ, 中本幸一, 安積卓也, 道木慎二, 本田晋也, 枝廣正人
組込みシステムシンポジウム(ESS2017) page: ポスター(26) 2017.8
More details
Language:Japanese Publishing type:Research paper, summary (national, other academic conference)
Robust and accurate monocular vision-based localization in outdoor environments of real-world robot challenge Reviewed
Adi Sujiwo, Eijiro Takeuchi, Luis Yoichi Morales, Naoki Akai, Hatem Darweesh, Yoshiki Ninomiya, Masato Edahiro
Journal of Robotics and Mechatronics Vol. 29 ( 4 ) page: 685 - 696 2017.8
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal) Publisher:Fuji Technology Press
This paper describes our approach to perform robust monocular camera metric localization in the dynamic environments of Tsukuba Challenge 2016. We address two issues related to vision-based navigation. First, we improved the coverage by building a custom vocabulary out of the scene and improving upon place recognition routine which is key for global localization. Second, we established possibility of lifelong localization by using previous year’s map. Experimental results show that localization coverage was higher than 90% for six different data sets taken in different years, while localization average errors were under 0.2 m. Finally, the average of coverage for data sets tested with maps taken in different years was of 75%.
Runtime and code generation for Automotive RTOS of multirate model in model base parallelization
Vol. 116 ( 511 ) page: 21 - 26 2017.3
More details
Language:Japanese
Performance improvement of multirate Simulink models by model analysis
Vol. 116 ( 510 ) page: 267 - 272 2017.3
More details
Language:Japanese
A study on Data Parallelization in Model Based Parallelizer
Vol. 116 ( 510 ) page: 263 - 266 2017.3
More details
Language:Japanese
A Feature Outlier Identification Method for Multi-object Tracking Reviewed
A. Monrroy, S. Kato, M. Edahiro
Proceedings of the 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'16) Vol. WIP page: 5 2016.10
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
GPU-accelerated Index Nested Loop Join on VoltDB Reviewed
N. Anh, S. Kato, M. Edahiro
Proceedings of the 4th IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'16) Vol. WIP page: 6 2016.10
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Monocular Vision-Based Localization Using ORB-SLAM with LIDAR-Aided Mapping in Real-World Robot Challenge Reviewed
A. Sujiwo, T. Ando, E. Takeuchi, Y. Ninomiya, M. Edahiro
Journal of Robotics and Mechatronics Vol. 28 ( 4 ) page: 479-490 2016.8
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
Accelerated Deformable Part Models on GPUs Reviewed
Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Kazuya Takeda, Seiichi Mita
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Vol. 27 ( 6 ) page: 1589 - 1602 2016.6
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal) Publisher:IEEE COMPUTER SOC
Object detection is a fundamental challenge facing intelligent applications. Image processing is a promising approach to this end, but its computational cost is often a significant problem. This paper presents schemes for accelerating the deformable part models (DPM) on graphics processing units (GPUs). DPM is a well-known algorithm for image-based object detection, and it achieves high detection rates at the expense of computational cost. GPUs are massively parallel compute devices designed to accelerate dataparallel compute-intensive workload. According to an analysis of execution times, approximately 98 percent of DPM code exhibits loop processing, which means that DPM could be highly parallelized by GPUs. In this paper, we implement DPM on the GPU by exploiting multiple parallelization schemes. Results of an experimental evaluation of this GPU-accelerated DPM implementation demonstrate that the best scheme of GPU implementations using an NVIDIA GPU achieves a speed up of 8.6x over a naive CPU-based implementation.
A scalability analysis of many cores and on-chip mesh networks on the TILE-Gx platform Reviewed
Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro
2016 IEEE 10TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC) page: 46 - 52 2016
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing manycore processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor.
We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the twodimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.
Pure Pursuit Revisited: Field Testing of Autonomous Vehicles in Urban Areas Reviewed
Hiroki Ohta, Naoki Akai, Eijiro Takeuchi, Shinpei Kato, Masato Edahiro
PROCEEDINGS OF 2016 IEEE 4TH INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS (CPSNA) page: 7 - 12 2016
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
In this paper, we aim to explore path following. We implement a path following component by referring to the existing Pure Pursuit algorithm. Using the simulation and field operational test, we identified the problem in the path following component. The main problems identified were with respect to vehicles meandering off the path, turning a corner, and the instability of steering control. Therefore, we apply some modifications to the Pure Pursuit[1] algorithm. We have also conducted the simulation and field operational tests again to evaluate these modifications.
Simulinkモデルからのブロックレベル並列化 Reviewed
山口 滉平, 竹松 慎弥, 池田 良裕, 李 瑞徳, 鍾 兆前, 近藤 真己, C情報システムズ, 枝廣 正人
組込みシステムシンポジウム (ESS2015) page: ポスター(21) 2015.10
More details
Language:Japanese Publishing type:Research paper, summary (national, other academic conference)
System-level design method for control systems with hardware-implemented interrupt handler Reviewed
Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro
Journal of Information Processing Vol. 23 ( 5 ) page: 532 - 541 2015.9
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal) Publisher:Information Processing Society of Japan
In this paper, we propose a system-level design method for control systems that enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to a deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates the target implementation from the model. Case studies on a motor control system show that the proposed method reduces the processor load, improves the latency of the interrupt processing, and enables the design space exploration for the control system.
階層構造を持つメニーコアアーキテクチャへのタスクマッピング Reviewed
油谷 創, 枝廣 正人
情報処理学会論文誌 Vol. 56 ( 8 ) page: 1568-1581 2015.8
More details
Language:Japanese Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
Implementation and evaluation of AES/ADPCM on STP and FPGA with High-level Synthesis Reviewed
Y. Ando, Y. Ishida, S. Honda, H. Takada, M. Edahiro
Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page: 415-420 2015.3
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Profiler for Control System in System Level Design Reviewed
T-D Miaw, Y. Ando, S. Honda, H. Takada, M. Edahiro
Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI) page: 46-51 2015.3
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip Reviewed
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro
2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA) page: 1-6 2015
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.
Real-Time Visualization of Moving Objects Reviewed
Patricia Ortal, Shinpei Kato, Masato Edahiro
2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015 page: 60 - 65 2015
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
The development of visualization tools that help us assimilate the information that surrounds us is essential in business environments and most research fields. Data visualization is a powerful tool that lets us recognize patterns and trends easily, allows us to extract sensible information faster, stimulates hypothesis generation, and helps us make effective decisions. This paper describes the design and implementation of a web application that displays moving objects in real-time using Google Maps. This web application was done as part of an integrated system that addresses issues related to the automated driver assistance field. Moreover, this work seeks to be a reference framework that will provide visual support for researchers in the area of mobility looking to analyze moving object trajectories, evaluate prediction models, or explain their results.
HexaCam: An FPGA-based Multi-view Camera System Reviewed
Abraham Monrroy, Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Takefumi Miyoshi, Satoshi Funada
2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015 page: 48 - 53 2015
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
Accurate perception information of the surroundings is a desirable feature in any cyber-physical system for autonomous robotics. Besides, providing a cost-wise solution to this need, is also useful for developing other kinds of applications such as mapping, decision-making, self-localization, among others. In this work, we present and benchmark a cost-effective camera device with six image sensors attached to a custom built FPGA board. The perception information is delivered on the host side, thanks to a HOG based object detector executed on the GPU. Our conclusion is that the low cost prototype is able to acquire and extract the perception data in 9.41 frames per second.
Design Space Exploration of Control System with Hardware-implemented Interrupt Handler Reviewed
Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro
2015 6TH INTERNATIONAL CONFERENCE OF INFORMATION AND COMMUNICATION TECHNOLOGY FOR EMBEDDED SYSTEMS (IC-ICTES) page: 1-6 2015
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
In this paper, we propose a system-level design tool for control systems that enables the development of hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. Case studies on a motor control system show that the proposed method enables the designer to explore design space of control system, reduces the processor load and improves the latency of the interrupt processing.
Automatic synthesis of inter-heterogeneous-processor communication implementation for programmable system-on-chip Reviewed
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro
2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA) Vol. 8 page: 95-99 2015
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal) Publisher:IEEE
This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.
制御システムのマルチ・メニーコアプロセッサ実装 Invited
枝廣 正人
計測と制御 Vol. 53 ( 12 ) page: 1111-1116 2014.12
More details
Language:Japanese Publishing type:Article, review, commentary, editorial, etc. (scientific journal)
Exploring the problem of GPU programming for data-intensive applications: A case study of multiple expectation maximization for motif elicitation Reviewed
Yuki Kitsukawa, Manato Hirabayashi, Shinpei Kato, Masato Edahiro
ACM International Conference Proceeding Series Vol. 04-05- page: 256 - 262 2014.12
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:Association for Computing Machinery
Recently General-Purpose Computing on Graphics Processing Units (GPGPU) has been used to reduce the processing time of various applications, but the degree of acceleration by the Graphical Processing Unit (GPU) depends on the application. This study focuses on data analysis as an application example of GPGPU, specifically, the design and implementation of GPGPU computation libraries for data-intensive workloads. The effects of efficient memory allocation and high-speed read-only memories on the execution time are evaluated. In addition to employing a single GPU, the scalability using multiple GPUs is also evaluated. Compared to a Central Processing Unit (CPU) alone, the memory allocation method reduces the execution time for memory copies by approximately 60% when a GPU is used, while utilizing read-only memories results in an approximately 20% reduction in the overall program execution time. Moreover, expanding the number of GPUs from one to four reduces the execution time by approximately 10%.
システムレベル設計における制御システム向けプロファイル機構 (VLSI設計技術) -- (デザインガイア2014 : VLSI設計の新しい大地)
繆 同徳, 安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 114 ( 328 ) page: 75 - 80 2014.11
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
本論文ではシステムレベル設計における制御システム向けのプロファイル機構を述べる.制御システムを設計する際,センサーやアクチュエータから非同期で通知される割込みと,割込みにより優先的に処理を開始する割込み処理を考慮する必要がある.但し,既存のプロファイル機構は割込みの関連情報を取得できない.本論文では,制御システムの開発を支援するために,割込みの関連情報を取得可能なプロファイル手法を提案する.提案手法を設計事例に適用し,効果を評価した.
割込みハンドラのハードウェア化を実現するシステムレベル設計手法 (VLSI設計技術) -- (デザインガイア2014 : VLSI設計の新しい大地)
安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 Vol. 114 ( 328 ) page: 69 - 74 2014.11
More details
Language:Japanese Publisher:一般社団法人電子情報通信学会
本論文は,割込みで駆動する専用HWを設計可能な,制御システム向けのシステムレベル設計ツールについて述べる.制御システムは複雑化,処理の高度化が進み,それに伴い割込み処理の頻度が増加したことで,プロセッサ負荷の増加,消費電力の増加,割込み処理レイテンシの悪化といった問題が生じている.これらの問題を解決するため,割込みにより処理を開始し,処理中はセンサや入出力ハードウェアといったデバイスへ直接アクセスする専用ハードウェアが求められている.提案手法は,処理とデバイス間の通信,割込み,割込み処理を抽象化した制御システムモデルから,割込みで駆動するハードウェアを含む制御システムを設計可能である.モータ制御システムを対象とした評価実験により,提案手法を用いることで,プロセッサ負荷の削減,消費電力の削減,レイテンシの改善が可能なことを示す.
繆同徳, 安藤友樹, 本田晋也, 高田広章, 枝廣正人
研究報告システムとLSIの設計技術(SLDM) Vol. 2014 ( 6 ) page: 1 - 6 2014.11
More details
Language:Japanese
本論文ではシステムレベル設計における制御システム向けのプロファイル機構を述べる.制御システムを設計する際,センサーやアクチュエータから非同期で通知される割込みと,割込みにより優先的に処理を開始する割込み処理を考慮する必要がある.但し,既存のプロファイル機構は割込みの関連情報を取得できない.本論文では,制御システムの開発を支援するために,割込みの関連情報を取得可能なプロファイル手法を提案する.提案手法を設計事例に適用し,効果を評価した.
割込みハンドラのハードウェア化を実現するシステムレベル設計手法
安藤友樹, 本田晋也, 高田広章, 枝廣正人
研究報告システムとLSIの設計技術(SLDM) Vol. 2014 ( 5 ) page: 1 - 6 2014.11
More details
Language:Japanese
本論文は,割込みで駆動する専用HWを設計可能な,制御システム向けのシステムレベル設計ツールについて述べる.制御システムは複雑化,処理の高度化が進み,それに伴い割込み処理の頻度が増加したことで,プロセッサ負荷の増加,消費電力の増加,割込み処理レイテンシの悪化といった問題が生じている.これらの問題を解決するため,割込みにより処理を開始し,処理中はセンサや入出力ハードウェアといったデバイスへ直接アクセスする専用ハードウェアが求められている.提案手法は,処理とデバイス間の通信,割込み,割込み処理を抽象化した制御システムモデルから,割込みで駆動するハードウェアを含む制御システムを設計可能である.モータ制御システムを対象とした評価実験により,提案手法を用いることで,プロセッサ負荷の削減,消費電力の削減,レイテンシの改善が可能なことを示す.
油谷 創, 枝廣 正人
研究報告組込みシステム(EMB) Vol. 2014 ( 3 ) page: 1 - 8 2014.9
More details
Language:Japanese Publisher:一般社団法人情報処理学会
近年,半導体技術の進展によって 1 つの LSI 上に複数のプロセッサが搭載されたマルチコアや,数十,数百のプロセッサが搭載されたメニーコアが広く使われている.また,スケーラビリティをさらに高めるために階層構造を持つメニーコアも登場している.階層型メニーコアアーキテクチャは,将来組込みプロセッサにおいても主流になると考えられている.そこで,階層構造を考慮したタスクマッピング手法を提案し,既存手法との比較評価を行った.提案手法は NN Embed 法,Topo-LB 法,Cluster-Based ILP 法と比較してそれぞれ 44%,32%,26%通信コストの少ないマッピング結果を示した.
Evaluation of GNSS for Autonomous Driving Reviewed
H. Ohta, S. Kato, M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: WiP Session 2014.8
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Simple One-to-one Architecture for Parallel Execution of Embedded Control Systems Reviewed
R. Nakamura, F. Arakawa, M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: 25-30 2014.8
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
GPU-accelerated Point Cloud Mapping for Autonomous Driving Reviewed
Y. Kitsukawa, S. Kato, M. Edahiro
Proceedings of the 2nd IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA'14) page: WiP Session 2014.8
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Establishing a standard interface between multi-manycore and software tools - SHIM Reviewed
Masaki Gondo, Fumio Arakawa, Masato Edahiro
2014 IEEE COOL CHIPS XVII page: VI-1 2014
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
The multi core processors are becoming norm and a processor with even more than a hundred of cores are emerging. These inherently require wide range of software tools to help software developers. However, supporting these complex hardware by the tools require significant effort by the tool vendors, and each invest in adapting the new hardware by modifying their tools or creating proprietary configuration files, while often the similar set of hardware architectural information are needed. The SHIM, Software-Hardware Interface for Multi-many-core, is a joint industrial and academic effort to standardize the interface between the multicore hardware and the software tools. This extended abstract introduces SHIM, the overall architecture, the schema used, the use-cases, and a prototype tool to foster the adaption of the interface.
Power and Performance Characterization and Modeling of GPU-Accelerated Systems Reviewed
Yuki Abe, Koji Inoue, Hiroshi Sasaki, Masato Edahiro, Shinpei Kato, Martin Peres
2014 IEEE 28TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM page: 113-122 2014
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
Graphics processing units (GPUs) provide an order-of-magnitude improvement on peak performance and performance-per-watt as compared to traditional multicore CPUs. However, GPU-accelerated systems currently lack a generalized method of power and performance prediction, which prevents system designers from an ultimate goal of dynamic power and performance optimization. This is due to the fact that their power and performance characteristics are not well captured across architectures, and as a result, existing power and performance modeling approaches are only available for a limited range of particular GPUs. In this paper, we present power and performance characterization and modeling of GPU-accelerated systems across multiple generations of architectures. Characterization and modeling both play a vital role in optimization and prediction of GPU-accelerated systems. We quantify the impact of voltage and frequency scaling on each architecture with a particularly intriguing result that a cutting-edge Kepler-based GPU achieves energy saving of 75% by lowering GPU clocks in the best scenario, while Fermi-and Tesla-based GPUs achieve no greater than 40% and 13%, respectively. Considering these characteristics, we provide statistical power and performance modeling of GPU-accelerated systems simplified enough to be applicable for multiple generations of architectures. One of our findings is that even simplified statistical models are able to predict power and performance of cutting-edge GPUs within errors of 20% to 30% for any set of voltage and frequency pair.
Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors Reviewed
Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro
2014 IEEE COOL CHIPS XVII page: VI-2 2014
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.
Parallel Design of Control Systems Utilizing Dead Time for Embedded Multicore Processors Reviewed
Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro
2014 IEEE COOL CHIPS XVII Vol. E99-C ( 4 ) page: 491-502 2014
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal) Publisher:IEEE
This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.
ISHIDA Yukihito, ANDO Yuki, HONDA Shinya, TAKADA Hiroaki, EDAHIRO Masato
IEICE technical report Vol. 113 ( 325 ) page: 63 - 68 2013.11
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heterogeneous multiprocessors. Along with the increase in the use of heterogeneous multiprocessors such as FPGAs with processor cores, the cost for design and implement of the inter-processor communication becomes a problem. Focusing on that typical heterogeneous multiprocessors have inter-processor interrupts and shared memories, we propose an implementation of inter-processor communication using them. In order to increase the design efficiency, we also propose a method that automatically generates the inter-processor communication for target systems. The case study shows that automatically generated inter-processor communication exactly runs on the system with heterogeneous multiprocessors.
System-level design method considering the interrupt processing
ANDO Yuki, ISHIDA Yukihito, HONDA Shinya, TAKADA Hiroaki, EDAHIRO Masato
IEICE technical report. Dependable computing Vol. 113 ( 321 ) page: 119 - 124 2013.11
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
We propose a system level design methodology for control systems that have both input and output by abstraction of interrupt handling. Since control systems are increasing their complexity, the designers have to design them on higher level of abstraction to increase design efficiency. System level design is known as one of the way to realize that. However, they cannot handle control systems because they do not consider interrupt handling. We propose a model that deals with control systems at system level by abstraction of interrupt handling. The case study shows that our proposing model has few overhead on memory usage and execution time.
Jozwik Krzysztof, Honda Shinya, Edahiro Masato, Tomiyama Hiroyuki, Takada Hiroaki
Technical report of IEICE. VLD Vol. 112 ( 375 ) page: 135 - 140 2013.1
More details
Language:English Publisher:The Institute of Electronics, Information and Communication Engineers
Jozwik Krzysztof, Honda Shinya, Edahiro Masato, Tomiyama Hiroyuki, Takada Hiroaki
IEICE technical report. Computer systems Vol. 112 ( 376 ) page: 135 - 140 2013.1
More details
Language:English Publisher:The Institute of Electronics, Information and Communication Engineers
Rainbow: An operating system for software-hardware multitasking on dynamically partially reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada
International Journal of Reconfigurable Computing Vol. 2013 page: ID: 789134 2013
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
Dynamic Partial Reconfiguration technology coupled with an Operating System for Reconfigurable Systems (OS4RS) allows for implementation of a hardware task concept, that is, an active computing object which can contend for reconfigurable computing resources and request OS services in a way software task does in a conventional OS. In this work, we show a complete model and implementation of a lightweight OS4RS supporting preemptable and clock-scalable hardware tasks. We also propose a novel, lightweight scheduling mechanism allowing for timely and priority-based reservation of reconfigurable resources, which aims at usage of preemption only at the time it brings benefits to the performance of a system. The architecture of the scheduler and the way it schedules allocations of the hardware tasks result in shorter latency of system calls, thereby reducing the overall OS overhead. Finally, we present a novel model and implementation of a channel-based intertask communication and synchronization suitable for software-hardware multitasking with preemptable and clock-scalable hardware tasks. It allows for optimizations of the communication on per task basis and utilizes point-to-point message passing rather than shared-memory communication, whenever it is possible. Extensive overhead tests of the OS4RS services as well as application speedup tests show efficiency of our approach. © 2013 Krzysztof Jozwik et al.
DOI: 10.1155/2013/789134
GPU implementations of object detection using HOG features and deformable models Reviewed
Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Kazuya Takeda, Taiki Kawano, Seiichi Mita
2013 IEEE 1st International Conference on Cyber-Physical Systems, Networks, and Applications, CPSNA 2013 page: 106 - 111 2013
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE Computer Society
Vision-based object detection using camera sensors is an essential piece of perception for autonomous vehicles. Various combinations of features and models can be applied to increase the quality and the speed of object detection. A well-known approach uses histograms of oriented gradients (HOG) with deformable models to detect a car in an image [15]. A major challenge of this approach can be found in computational cost introducing a real-time constraint relevant to the real world. In this paper, we present an implementation technique using graphics processing units (GPUs) to accelerate computations of scoring similarity of the input image and the pre-defined models. Our implementation considers the entire program structure as well as the specific algorithm for practical use. We apply the presented technique to the real-world vehicle detection program and demonstrate that our implementation using commodity GPUs can achieve speedups of 3x to 5x in frame-rate over sequential and multithreaded implementations using traditional CPUs. © 2013 IEEE.
Evaluation of power consumption at execution of multiple automatically parallelized and power controlled media applications on the RP2 low-power multicore Reviewed
Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, Hironori Kasahara
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) Vol. 7146 page: 31 - 45 2013
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
This paper evaluates an automatic power reduction scheme of OSCAR automatic parallelizing compiler having power reduction control capability when multiple media applications parallelized by the OSCAR compiler are executed simultaneously on RP2, a 8-core multicore processor developed by Renesas Electronics, Hitachi, and Waseda University. OSCAR compiler enables the hierarchical multigrain parallel processing and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating and power gating for each processor core using the OSCAR multi-platform API. The RP2 has eight SH4A processor cores, each of which has power control mechanisms such as DVFS, clock gating and power gating. First, multiple applications with relatively light computational load are executed simultaneously on the RP2. The average power consumption of power controlled eight AAC encoder programs, each of which was executed on one processor, was reduced by 47%, (to 1.01W), against one AAC encoder execution on one processor (from 1.89W) without power control. Second, when multiple intermediate computational load applications are executed, the power consumptions of an AAC encoder executed on four processors with the power reduction control was reduced by 57% (to 0.84W) against an AAC encoder execution on one processor (from 1.95W). Power consumptions of one MPEG2 decoder on four processors with power reduction control was reduced by 49% (to 1.01W) against one MPEG2 decoder execution on one processor (from 1.99W). Finally, when a combination of a high computational load application program and an intermediate computational load application program are executed simultaneously, the consumed power reduced by 21% by using twice number of cores for each application. This paper confirmed parallel processing and power reduction by OSCAR compiler are efficient for multiple application executions. In execution of multiple light computational load applications, power consumption increases only 12% for one application. Parallel processing being applied to intermediate computational load applications, power consumption of executing one application on one processor core (1.49W) is almost same power consumption of two applications on eight processor cores (1.46W). © 2013 Springer-Verlag.
Data Transfer Matters for GPU Computing Reviewed
Yusuke Fujii, Takuya Azumi, Nobuhiko Nishio, Shinpei Kato, Masato Edahiro
2013 19TH IEEE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS 2013) page: 275 - 282 2013
More details
Language:English Publishing type:Research paper, summary (national, other academic conference) Publisher:IEEE
Graphics processing units (GPUs) embrace many-core compute devices where massively parallel compute threads are offloaded from CPUs. This heterogeneous nature of GPU computing raises non-trivial data transfer problems especially against latency-critical real-time systems. However even the basic characteristics of data transfers associated with GPU computing are not well studied in the literature. In this paper, we investigate and characterize currently-achievable data transfer methods of cutting-edge GPU technology. We implement these methods using open-source software to compare their performance and latency for real-world systems. Our experimental results show that the hardware-assisted direct memory access (DMA) and the I/O read-and-write access methods are usually the most effective, while on-chip microcontrollers inside the GPU are useful in terms of reducing the data transfer latency for concurrent multiple data streams. We also disclose that CPU priorities can protect the performance of GPU data transfers.
Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis
ISHIDA Yukihito, SHIBATA Seiya, ANDO Yuki, HONDA Shinya, TAKADA Hiroaki, EDAHIRO Masato
IEICE technical report. Artificial intelligence and knowledge-based processing Vol. 112 ( 70 ) page: 77 - 82 2012.5
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FPGA and STP engine in order to confirm their performance whether they can substitute the dedicated hardware of SoC. We selected AES and ADPCM applications to compare the performance of FPGA and STP engine. The applications were synthesized with the same behavioral synthesis tools. Then, we implemented them onto FPGA and STP engine using the integrated development environments. For the evaluation, we compared them in terms of hardware area, the number of states, the number of cycles, frequency, and execution time.
Checkpoint Selection for DEPS Framework Based on Quantitative Evaluation of DEPS Profile Invited Reviewed
H. Kawashima, G. Zeng, H. Takase, M. Edahiro, H. Takada
17th Workshop on Synthesis and System Integration of Mixed Information Technologies page: 174-179 2012.3
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Fast Elliptic Curve Cryptography Using Minimal Weight Conversion of d Integers Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
Proceedings of the Tenth Australasian Information Security Conference (AISC 2012), ACS, 2012, Conferences in Research and Practice in Information Technology Vol. 125 page: 15-26 2012.1
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Calculating average joint hamming weight for minimal weight conversion of d integers Reviewed
Vorapong Suppakitpaisarn, Masato Edahiro, Hiroshi Imai
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) Vol. 7157 page: 229 - 240 2012
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
In this paper, we propose an algorithm to calculate the efficiency of number representations in elliptic curve cryptography, average joint Hamming weight. The method uses Markov chains generated from a minimal weight conversion algorithm of d integers using the minimal weight conversion. With redundant representations using digit sets like {0, ±1}, it is possible to reduce computation time of the cryptosystem. Although larger digit sets make the computation time shorter, it requires longer preprocessing time. Therefore, the average joint Hamming weight is useful to evaluate digit sets. The Markov chains to find the average joint Hamming weight are derived automatically from the conversions. However, the number of states in these Markov chains is generally infinite. In [8], we propose an algorithm to reduce the number of states, but it is still unclear which representations the method can be applied for. In this paper, the finiteness of Markov chain with the existence of a stationary distribution is proven in a class of representation whose digit set D S be a finite set such that there exists a natural number Λ where D S ⊆ {0, ±1, ..., ±Λ} and {0,±1, ±Λ} ⊆ D S. The class covers most of the representation practically used in elliptic curve cryptography such as the representation which digit set are {0, ±1} and {0, ±1, ±3}. © 2012 Springer-Verlag.
Toward GPU-accelerated Traffic Simulation and Its Real-Time Challenge Reviewed
Manato Hirabayashi, Shinpei Kato, Masato Edahiro, Yuki Sugiyama
International Workshop on Real-Time and Distributed Computing in Emerging Applications (REACTION2012) page: 1-6 2012
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Optimal Elliptic Curve Scalar Multiplication Using Double-Base Chains Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
International Journal of Digital Information and Wireless Communications (IJDIWC) Vol. 2 ( 1 ) page: 923-942 2012
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
Optimal Elliptic Curve Cryptography Using Fibonacci Sequence Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
Proceedings of the 5th Thailand-Japan International Academic Conference (TJIA2012) page: 未登録 2012
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Fastest Multi-Scalar Multiplication Based on Double-Base Chain Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
World Congress on Internet Security (WorldCIS-2012) page: 93-98 2012
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Fast Elliptic Curve Cryptography Using Optimal Double-Base Chains Reviewed
V. Suppakitpaisarn, M. Edahiro, H. Imai
Proceedings of the International Conference on Informatics & Applications (ICIA2012) page: 190-204 2012
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Efficient algorithms for extracting pareto-optimal hardware configurations in DEPS framework Reviewed
Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada
IPSJ Transactions on System LSI Design Methodology Vol. 5 page: 133 - 142 2012
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice. © 2012 Information Processing Society of Japan.
Comparison of preemption schemes for partially reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
IEEE Embedded Systems Letters Vol. 4 ( 2 ) page: 45 - 48 2012
More details
Language:English Publishing type:Rapid communication, short report, research note, etc. (scientific journal)
Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization. © 2012 IEEE.
Hardware Multitasking in Dynamically Partially Reconfigurable FPGA-based Embedded Systems Invited Reviewed
K. Jozwik, H. Tomiyama, M. Edahiro, S. Honda, H. Takada
Int'l SoC Design Conference page: 183-186 2011.11
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
Evaluation of Power Consumption by Executing Media Applications on Low-power Multicore RP2
Vol. 2011 ( 1 ) page: 1 - 8 2011.3
More details
Rainbow: An OS extension for hardware multitasking on dynamically partially reconfigurable FPGAs Reviewed
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 page: 416 - 421 2011
More details
Language:English Publishing type:Research paper, summary (national, other academic conference)
DPR (Dynamic Partial Reconfiguration) capability found in some of modern FPGAs allows implementation of a concept of a HW (Hardware) task, which similarly to its software counterpart has its state and shares time-multiplexed resources with the other tasks. While the new technology presents many advantages for embedded systems where run-time adaptability is an additional requirement, their efficient and easily portable implementations require a control software or an OS which would manage all the complexities of the underlying technology, providing an abstracted interface for the application programmer. This paper presents a novel and robust hardware multitasking extension for a conventional OS, managing task scheduling and configurations, and providing easy-to-use API (Application Programming Interface) for the application programmer. Scheduling is priority-based and takes advantage of task caching. Moreover, the extension is based on a developed design flow and embedded hardware platform allowing efficient task preemption, which can be utilized whenever it presents any benefits to the application. © 2011 IEEE.
MIYAMOTO TAKAMICHI, MASE MASAYOSHI, KIMURA KEIJI, ISHIZAKA KAZUHISA, SAKAI JUNJI, EDAHIRO MASATO, KASAHARA HIRONORI
Vol. 2010 ( 9 ) page: 1 - 8 2010.2
More details
Software Technology for Multicore Systems : Software Platform for Embedded Multi-core Processor
SAKAI Junji, INOUE Hiroaki, EDAHIRO Masato
IPSJ Magazine Vol. 47 ( 1 ) page: 29 - 33 2006.1
More details
Language:Japanese Publisher:Information Processing Society of Japan (IPSJ)
Other Link: http://id.nii.ac.jp/1001/00065529/
Clock Tree Synthesis for Shrinking a Chip Design
INOUE Hiroaki, EDAHIRO Masato
Technical report of IEICE. VLD Vol. 100 ( 293 ) page: 23 - 28 2000.9
More details
Language:Japanese Publisher:The Institute of Electronics, Information and Communication Engineers
In this report, we present a new Clock Tree Synthesis(CTS)for shrinking a chip design. It minimizes clock skew of the chip through scaling by executing the traditional CTS with two tuned parameters for the target process instead of those for the current process. Since the program and design libraries of CTS do not need to be modified at all and it is executed with the original design data, we can take the advantage of reusing all optimized scripts for CAD which have been already designed. Then, evaluation shows our CTS keeps the skew minimized regardless of shrinking the chip and has sufficient effects on reducing clock skew compared with the traditional one. Consequently, it enables us to extend the application of scaling to LSI design.
IEEE2804 SHIM: Software-Hardware Interface for Multi-Many-Core Invited International conference
枝廣 正人
2022.6.23
More details
Event date: 2022.6
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
マルチコア向けモデルベース開発のためのモデル分割とその設計検証
今井 俊輔, 生沼 正博, 嶋田 卓尚, 竹内 成樹, 枝廣 正人
ETNET2025 2025.3.19 情報処理学会
More details
Event date: 2025.3
Language:Japanese Presentation type:Oral presentation (general)
Venue:沖永良部 Country:Japan
ハードウェア抽象化記述SHIMにおけるDNNを用いたソフトウェア実行時間推定手法
岩井 星良, 荒島 聡太, 枝廣 正人
ETNET2025 2025.3.17 情報処理学会
More details
Event date: 2025.3
Language:Japanese Presentation type:Oral presentation (general)
Venue:沖永良部 Country:Japan
Multi-Architecture Halide Template-Driven Automatic Library Function Generation for Simulink Models
李 騏, 武 山モン, 枝廣 正人
ETNET2025 2025.3.19 情報処理学会
More details
Event date: 2025.3
Language:English Presentation type:Oral presentation (general)
Venue:沖永良部 Country:Japan
タスクスケジューリング問題への並列メタヒューリス ティックスの適用
毛 思睿、枝廣 正人
日本オペレーションズ・リサーチ学会2025年春季研究発表会 2025.3.6 日本オペレーションズ・リサーチ学会
More details
Event date: 2025.3
Language:Japanese Presentation type:Oral presentation (general)
Venue:武蔵野市 Country:Japan
マルチコア向けモデルベース開発のためのモデル分割とその設計検証
今井 俊輔, 生沼 正博, 嶋田 卓尚, 竹内 成樹, 枝廣 正人
SWEST2024 2024.8.29 SWEST 実行委員会
More details
Event date: 2024.8
Language:Japanese Presentation type:Oral presentation (general)
Venue:下呂市 Country:Japan
マイクロコントローラ向けROS2の低速通信路を持つ小規模組込みシステム向けの効率化
小坂 直輝、本田 晋也、大谷 寿賀子、枝廣 正人
ETNET2024 2024.3.23 情報処理学会
More details
Event date: 2024.3
Language:Japanese Presentation type:Oral presentation (general)
Venue:壱岐市 Country:Japan
マルチレート制御モデルの並列化アルゴリズムの設計と形式検証
近藤 大起、磯部 祥尚、枝廣 正人
ETNET2024 2024.3.21 情報処理学会
More details
Event date: 2024.3
Language:Japanese Presentation type:Oral presentation (general)
Venue:壱岐市 Country:Japan
メタヒューリスティックの協調効果:クラスタリングとスケジューリング問題への応用とその比較
毛 思睿、枝廣 正人
情報処理学会第86回全国大会 2024.3.15 情報処理学会
More details
Event date: 2024.3
Language:Japanese Presentation type:Oral presentation (general)
Venue:横浜市 Country:Japan
ハードウェア抽象化記述SHIMにおけるDNNを用いたLLVM命令実行時間推定手法
岩井 星良、枝廣 正人
情報処理学会第86回全国大会 2024.3.17 情報処理学会
More details
Event date: 2024.3
Language:Japanese Presentation type:Oral presentation (general)
Venue:横浜市 Country:Japan
ベクトル演算器を有するマルチコアプロセッサ向けモデルベース並列化におけるタスクマッピングとスケジューリング手法
ブサンモン, 熊野 聡, 丸目 佳, 枝廣 正人
ETNET2023
More details
Event date: 2023.3
Language:Japanese Presentation type:Oral presentation (general)
ハードウェア抽象化記述SHIMにおけるDNNを用いたLLVM命令実行時間計測手法
三上比呂, 岩井星良, 枝廣正人
ETNET2023
More details
Event date: 2023.3
Language:Japanese Presentation type:Oral presentation (general)
モデルベース開発における並列性能向上に向けた複数遅延挿入手法
寒河江翔太, キムジンス, 新田果菜, 道木慎二, 本田晋也, 枝廣正人
ETNET2023
More details
Event date: 2023.3
Language:Japanese Presentation type:Oral presentation (general)
RISC-Vベクトル命令を用いた4次元不等間マップ補間処理の並列化
佐藤創太, 陳雨飛, 枝廣正人
ETNET2023
More details
Event date: 2023.3
Language:Japanese Presentation type:Oral presentation (general)
マルチコアでソフトウェアはどのように動くのか Invited
枝廣 正人
組込みマルチコアサミット2022 2022.11.17
More details
Event date: 2022.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
組込みマルチコアコンソーシアムについて Invited
枝廣 正人
組込みマルチコアサミット2022 2022.11.17
More details
Event date: 2022.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
パーティショニングOS向けユーザモードTCP/IPプロトコルスタック
手塚 湧太郎, 本田 晋也, 大谷 寿賀子, 枝廣 正人
ETNET2022 2022.3.10
More details
Event date: 2022.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース並列化アルゴリズムの定理証明器による形式検証
岩田 駿, 磯部 祥尚, 枝廣 正人
ETNET2022 2022.3.11
More details
Event date: 2022.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みマルチコアコンソーシアムについて Invited
枝廣 正人
組込みマルチコアサミット2021
More details
Event date: 2021.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
ハードウェア抽象化記述SHIMと性能見積 Invited
枝廣 正人
組込みマルチコアサミット2021
More details
Event date: 2021.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
ROMへのアクセスレイテンシが大きいマイコンを対象とした畳み込みニューラルネットワークの最適化
下平 健太, 本田 晋也, 高田 広章, 枝廣 正人
ETNET2021
More details
Event date: 2021.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
車載制御モデルの並列設計におけるランタイム性能解析と効率化
加藤 聖也, 寒河江 翔太, 山本 椋太, 生沼 正博, キム ジンス, 道木 慎二, 本田 晋也, 枝廣 正人
ETNET2021
More details
Event date: 2021.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
データ並列性を持つSimulinkモデルからのコード生成
徐 品, 枝廣 正人
ETNET2021
More details
Event date: 2021.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
ハードウェア抽象化記述SHIMにおけるLLVM命令実行時間計測手法
井ノ川 誠, 枝廣 正人
ETNET2021
More details
Event date: 2021.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
C言語ベースのシステムレベル設計における低コストで高速な協調検証環境
稲石 日奈子, 山本 椋太, 伊藤 慎治, 本田 晋也, 枝廣 正人
ETNET2021
More details
Event date: 2021.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース並列化ツールを用いたモデルレベルブロック分割手法の検討
山田亜汰朗, 生沼正博, 木村一臣, 山本椋太, 枝廣正人
第55回組込みシステム研究会
More details
Event date: 2020.12
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
A DNN implementation on FPGAs from the existing DNN framework using HLS
Kim Hyunjae, Ryota Yamamoto, Shinya Honda,Masato Edahiro
More details
Event date: 2020.12
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
高位合成によるFPGA向けDNN推論器に対する前処理の検討
田中彬義, 山本椋太, 伊藤慎治, 本田晋也, 枝廣正人
第55回組込みシステム研究会
More details
Event date: 2020.12
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
時間パーティショニング機構を持つリアルタイムOSの性能評価手法
手塚湧太郎, 本田晋也, 大谷寿賀子, 枝廣正人
第55回組込みシステム研究会
More details
Event date: 2020.12
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みマルチコアコンソーシアムについて
枝廣 正人
組込みマルチコアサミット2020
More details
Event date: 2020.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
SimulinkモデルからCPUとアクセラレータの併用コードの作成手法
甲斐琢朗, 森裕司(NSITEXE), 枝廣正人
ETNET2020
More details
Event date: 2020.2
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
ハードウェア抽象化記述SHIMによる性能見積のためのLLVM-IR命令実行時間計測手法
鳥越 敬,枝廣 正人
ETNET2020
More details
Event date: 2020.2
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
共有メモリ付階層型制御モデルの並列化アルゴリズムのCSPによる形式化とFDRによる検証
于文博,磯部 祥尚(産業技術総合研究所),枝廣 正人
ETNET2020
More details
Event date: 2020.2
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みマルチコアコンソーシアムについて
枝廣 正人
組込みマルチコアサミット2019
More details
Event date: 2019.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
レガシコードを含むモデルベース開発における並列化手法
黒柳 彰宏,金森公洋,枝廣 正人
ETNET2019
More details
Event date: 2019.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
ハードウェア抽象化記述SHIMとSHIMulatorによるソフトウェア動的性能見積手法
佐合 惇,枝廣 正人
ETNET2019
More details
Event date: 2019.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース並列化アルゴリズムの形式化と正当性の証明
多門 俊哉,枝廣 正人,磯部 祥尚(産業技術総合研究所)
ETNET2019
More details
Event date: 2019.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース並列化ツールによるマルチコアプロセッサ上へのベクトル制御系実装の検討
吉田 恭介(日立製作所), 井上 雅理, 井ノ川 誠, 黒柳 彰宏, 本田 晋也, 枝廣 正人, 道木 慎二, 小島 流石(阪大), 安積 卓也(阪大), 中本 幸一(兵庫県立大)
平成31年電気学会全国大会論文集
More details
Event date: 2019.3
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
モータ制御系のマルチコア実装時における並列度向上に向けて遅延を導入した電流制御系の解析
キム ジンス, 井上 雅理, 加藤 聖也, 黒柳 彰宏, 枝廣 正人, 道木 慎二
平成31年電気学会全国大会論文集
More details
Event date: 2019.3
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
組込みマルチコアコンソーシアムについて
枝廣 正人
組込みマルチコアサミット2018
More details
Event date: 2018.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
EMC活動の紹介とビジョン
枝廣 正人
組込み向け マルチ・メニーコア ソフトウェア開発 テクニカルセミナー
More details
Event date: 2018.9
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
マルチコアプロセッサ上への実装時における並列度向上に向けたマルチレート電流制御系の解析
井上 雅理, 黒柳 彰宏, 枝廣 正人, 道木 慎二
平成30年電気学会産業応用部門大会
More details
Event date: 2018.8
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
制御モデルに内在する遅延を用いた並列化
池田 良裕,鈴木 悠太(デンソー),峰田 憲一(デンソー),森 裕司(デンソー),井上 雅理,道木 慎二,枝廣 正人
ETNET2018
More details
Event date: 2018.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
ニューラルネットによるモデル予測制御高速化
竹松 慎弥,嶋岡 雅浩,道木 慎二,枝廣 正人
ETNET2018
More details
Event date: 2018.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベースによる並列化コード自動生成ツールをモータ制御に適用した際の有用性評価
深谷 周平(日立交通テクノロジー), 井上 雅理, 横山 静香, 竹松 慎弥, 鍾 兆前, 本田 晋也, 枝廣 正人, 道木 慎二, 小島 流石(阪大), 安積 卓也(阪大), 近藤 真己(NECソリューションイノベータ), 中本 幸一(兵庫県立大)
平成30年電気学会全国大会
More details
Event date: 2018.3
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
モデルベース並列化における複数周期タスクを混在させたコア割り当て手法
池田 良裕,枝廣 正人
VLSI設計技術研究会
More details
Event date: 2018.2 - 2018.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みマルチコアコンソーシアムについて
枝廣 正人
組込みマルチコアサミット2017
More details
Event date: 2017.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
MBP(モデルベース並列化)を用いたクロスレイヤ設計
枝廣 正人
組込みマルチコアサミット2017
More details
Event date: 2017.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
Improving Core Allocation of Simulink Model for Embedded Multi-core Systems International conference
S. Kojima, M. Edahiro, and T. Azumi
IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2017)
More details
Event date: 2017.8
Language:English Presentation type:Poster presentation
Country:Taiwan, Province of China
組込みマルチコアコンソーシアムについて
枝廣 正人
組込みマルチコアサミット2017West
More details
Event date: 2017.7
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
ソフトのための国際標準ハードウェアモデル記述SHIM 1.0による性能見積とSHIM2.0への方向性
枝廣 正人
組込みマルチコアサミット2017West
More details
Event date: 2017.7
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
モデル解析によるマルチレートSimulinkモデル並列化
池田 良裕,市橋 友樹,仲田 壮佑,枝廣 正人
情報処理学会全国大会
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
永久磁石同期モータ電流制御系のための予測制御アルゴリズム並列化
竹松 慎弥,市村 駿太郎,岩間 拓也,嶋岡 雅浩,道木 慎二,枝廣 正人
情報処理学会全国大会
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース開発におけるKALRAY MPPA メニーコア向け並列化
鍾 兆前,枝廣 正人
情報処理学会全国大会
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース並列化(MBP)におけるマルチレートモデルの車載RTOS向けランタイムとコード生成
中野 友貴, 本田 晋也, 枝廣 正人, 鈴木 均(ルネサス エレクトロニクス)
ETNET2017
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース開発におけるマルチ・メニーコア向け自動並列化
鍾 兆前,枝廣 正人
ETNET2017
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデル解析によるマルチレートSimulinkモデルの性能向上
池田 良裕,鈴木 均(ルネサス エレクトロニクス),枝廣 正人
ETNET2017
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース開発におけるデータ並列化に関する検討
竹松 慎弥,枝廣 正人
ETNET2017
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
パス解析を用いた並列実行時メモリ読み書き順序の変化検出
杉山 由芳,枝廣 正人
ETNET2017
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
モデルベース並列化におけるCSPモデルを利用した形式検証の適用
山本 尚平, 鈴木 悠太(デンソー), 峰田 憲一(デンソー), 森 裕司(デンソー), 枝廣正人
ETNET2017
More details
Event date: 2017.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みマルチコアコンソーシアムについて
枝廣 正人
組込みマルチコアサミット2016
More details
Event date: 2016.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
ソフトのための国際標準ハードウェアモデル記述SHIM 1.0による性能見積とSHIM2.0への方向性
枝廣 正人
組込みマルチコアサミット2016
More details
Event date: 2016.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
永久磁石同期モータ電流制御系のための予測制御アルゴリズム並列化
竹松 慎弥,道木 慎二,嶋岡 雅浩,枝廣 正人
第41回組込みシステム研究会
More details
Event date: 2016.6
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
Simulinkモデルから状態方程式・出力方程式の抽出
池田 良裕,枝廣 正人
第41回組込みシステム研究会
More details
Event date: 2016.6
Language:Japanese Presentation type:Poster presentation
Country:Japan
組込みマルチコアコンソーシアムについて
枝廣 正人
組込みマルチコアサミット2015
More details
Event date: 2015.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
Simulinkモデルからのブロックレベル並列化
枝廣 正人
組込みマルチコアサミット2015
More details
Event date: 2015.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
組込みシステムでの マルチ・メニーコアプロセッサ利用に向けて ~ SHIMとモデルベース並列化 ~
枝廣 正人
CEATEC
More details
Event date: 2015.10
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
マルチ・メニーコア向けソフトウェア技術の基礎
枝廣 正人
組込みシステム開発技術展
More details
Event date: 2015.5
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
モデル予測制御における非線形漸化式実行の並列化
山田 竜正,枝廣 正人
ETNET2015
More details
Event date: 2015.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みマルチコアコンソーシアム概要
枝廣 正人
組込みマルチコアサミット2014
More details
Event date: 2014.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
Simulinkモデルベース自動並列化とSHIM
枝廣 正人
組込みマルチコアサミット2014
More details
Event date: 2014.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
システムレベル設計における制御システム向けプロファイル機構",情報処理学会研究報告
繆 同徳, 安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
デザインガイア2014
More details
Event date: 2014.11
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
割込みハンドラのハードウェア化を実現するシステムレベル設計手法", 情報処理学会研究報告
安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
デザインガイア2014
More details
Event date: 2014.11
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
階層構造を持つメニーコアアーキテクチャへのタスクマッピング
油谷 創,枝廣 正人
第34回組込みシステム研究発表会
More details
Event date: 2014.9
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
単方向1:1高速同期機構を用いたFPGA実装と評価
溝口 裕哉, 中村 陸, 安藤 友樹, 荒川 文男, 枝廣 正人
ETNET
More details
Event date: 2014.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
ソフトウェア向けハードウェア性能記述を用いたマルチコアにおける性能見積り
西村 裕, 中村 陸, 荒川 文男, 枝廣 正人
ETNET
More details
Event date: 2014.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みマルチコアECU活用に向けた内部モデル制御の効率的な並列実装
鈴木 悠太,佐多 宏太(トヨタ自動車(株)),加古 純一(トヨタ自動車(株)),枝廣 正人
制御部門マルチシンポジウム
More details
Event date: 2014.3
Language:Japanese Presentation type:Symposium, workshop panel (public)
Country:Japan
単方向1:1高速同期機構を用いた組込み制御並列化
中村 陸,荒川 文男,枝廣 正人
情報処理学会組込みシステム研究会
More details
Event date: 2013.11
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
割込み処理を考慮したシステムレベル設計手法
安藤 友樹, 石田 薫史, 本田 晋也, 高田 広章, 枝廣 正人
デザインガイア2013
More details
Event date: 2013.11
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
ヘテロマルチプロセッサシステム向けプロセッサ間通信の自動合成
石田薫史, 安藤友樹, 本田晋也,高田広章, 枝廣正人
デザインガイア2013
More details
Event date: 2013.11
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
単方向1:1高速同期機構を用いた組込み制御並列化
中村 陸,枝廣 正人
情報処理学会組込みシステムシンポジウム
More details
Event date: 2013.10
Language:Japanese Presentation type:Poster presentation
Country:Japan
マルチレート制御モデルのイベントドリブンプロセッサ実装
大川 禎 , 枝廣 正人
情報処理学会組込みシステム研究会
More details
Event date: 2013.9
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
差分方程式の解析的な並列化とそのモデリング
鈴木 悠太 , 枝廣 正人
情報処理学会組込みシステム研究会
More details
Event date: 2013.9
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みメニーコアに向けた (OSと)制御アプリ並列化
枝廣 正人
SWEST
More details
Event date: 2013.8
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
Country:Japan
マルチコア向けソフトウェア開発の基礎と最新動向
枝廣 正人
JASA中部支部 技術セミナー
More details
Event date: 2013.8
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
Country:Japan
マルチコア向けソフトウェア開発の基礎と最新動向
枝廣 正人
組込みシステム開発技術展
More details
Event date: 2013.5
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
CSP理論にもとづいた制御モデルのマルチコア実装向けタスク割当て
大川 禎 , 枝廣 正人 , 久村孝寛(NEC)
ETNET
More details
Event date: 2013.3
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
マルチ・メニーコアプロセッサを用いた 車載制御システムの実現に向けて
枝廣 正人
NCESシンポジウム
More details
Event date: 2012.10
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
Country:Japan
マルチ・メニーコア技術の基礎と省電力技術
枝廣 正人
STARCアドバンストセミナー
More details
Event date: 2012.9
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
Country:Japan
マルチコア向けソフトウェア開発の基礎と最新動向
枝廣 正人
組込みシステム開発技術展
More details
Event date: 2012.5
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
高位合成によるSTPエンジン及びFPGAへのAES/ADPCMの実装と評価
石田 薫史, 柴田 誠也, 安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
電子情報通信学会リコンフィギャラブル研究会
More details
Event date: 2012.5
Language:Japanese Presentation type:Oral presentation (general)
Country:Japan
組込みマルチ・メニーコアの現状とソフトウェア
枝廣 正人
Embedded Technology
More details
Event date: 2011.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
組込みマルチコアとソフトウェア
枝廣 正人
中部エレクトロニクスショー
More details
Event date: 2011.11
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
Hardware Multitasking in Dynamically Partially Reconfigurable FPGA-based Embedded Systems International conference
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
International SoC Design Conference (ISOCC)
More details
Event date: 2011.11
Language:English Presentation type:Oral presentation (invited, special)
Country:Korea, Republic of
マルチコア向けソフトウェア開発の基礎と最新動向
枝廣 正人
JASA近畿支部 技術セミナー
More details
Event date: 2011.10
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
Country:Japan
マルチコア向けソフトウェア開発の基礎と最新動向
枝廣 正人
組込みシステム開発技術展
More details
Event date: 2011.5
Language:Japanese Presentation type:Oral presentation (invited, special)
Country:Japan
CSP理論にもとづいた制御モデルのマルチコア実装向けタスク割当て International conference
大川 禎, 枝廣 正人, 久村孝寛
ETNET 2013.3.6
More details
Language:Japanese Presentation type:Oral presentation (general)
モデルベース並列化ツールによるマルチコアプロセッサ上へのベクトル制御系実装の検討 International conference
吉田 恭介, 井上 雅理, 井ノ川 誠, 黒柳 彰宏, 本田 晋也, 枝廣 正人, 道木 慎二, 小島 流石, 安積 卓也, 中本 幸一
平成31年電気学会全国大会論文集 2019.3.1
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
モデルベース並列化アルゴリズムの形式化と正当性の証明 International conference
多門 俊哉, 枝廣 正人, 磯部 祥尚
ETNET2019 2019.3.17
More details
Language:Japanese Presentation type:Oral presentation (general)
モデルベース並列化における複数周期タスクを混在させたコア割り当て手法 International conference
池田 良裕, 枝廣 正人
VLSI設計技術研究会 2018.2.28
More details
Language:Japanese Presentation type:Oral presentation (general)
モデルベース並列化におけるCSPモデルを利用した形式検証の適用 International conference
山本 尚平, 鈴木 悠太(デンソ, 峰田 憲一(デンソ, 森 裕司(デンソ, 枝廣正人
ETNET2017 2017.3.9
More details
Language:Japanese Presentation type:Oral presentation (general)
モデルベース並列化(MBP)におけるマルチレートモデルの車載RTOS向けランタイムとコード生成 International conference
中野 友貴, 本田 晋也, 枝廣 正人, 鈴木 均(ルネサス, エレクトロニクス
ETNET2017 2017.3.9
More details
Language:Japanese Presentation type:Oral presentation (general)
モデルベースによる並列化コード自動生成ツールをモータ制御に適用した際の有用性評価 International conference
深谷 周平, 交通テクノロジー, 井上 雅理, 横山 静香, 竹松 慎弥, 鍾 兆前, 本田 晋也, 枝廣 正人, 道木 慎二, 小島 流石, 安積 卓也, 近藤 真己, Cソリューションイノベータ, 中本 幸一
平成30年電気学会全国大会 2018.3.5
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
マルチ・メニーコア技術の基礎と省電力技術 International conference
枝廣 正人
STARCアドバンストセミナー 2012.9.25
More details
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
マルチ・メニーコア向けソフトウェア技術の基礎 International conference
枝廣 正人
組込みシステム開発技術展 2015.5.13
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
マルチ・メニーコアプロセッサを用いた 車載制御システムの実現に向けて International conference
枝廣 正人
NCESシンポジウム 2012.10.9
More details
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
マルチレート制御モデルのイベントドリブンプロセッサ実装 International conference
大川 禎, 枝廣 正人
情報処理学会組込みシステム研究会 2013.9.10
More details
Language:Japanese Presentation type:Oral presentation (general)
マルチコア向けソフトウェア開発の基礎と最新動向 International conference
枝廣 正人
JASA中部支部 技術セミナー 2013.8.5
More details
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
マルチコア向けソフトウェア開発の基礎と最新動向 International conference
枝廣 正人
組込みシステム開発技術展 2013.5.9
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
マルチコア向けソフトウェア開発の基礎と最新動向 International conference
枝廣 正人
組込みシステム開発技術展 2012.5.10
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
マルチコア向けソフトウェア開発の基礎と最新動向 International conference
枝廣 正人
JASA近畿支部 技術セミナー 2011.10.26
More details
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
マルチコア向けソフトウェア開発の基礎と最新動向 International conference
枝廣 正人
組込みシステム開発技術展 2011.5.13
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
マルチコアプロセッサ上への実装時における並列度向上に向けたマルチレート電流制御系の解析 International conference
井上 雅理, 黒柳 彰宏, 枝廣 正人, 道木 慎二
平成30年電気学会産業応用部門大会 2018.8.28
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
ヘテロマルチプロセッサシステム向けプロセッサ間通信の自動合成 International conference
石田薫史, 安藤友樹, 本田晋也, 高田広章, 枝廣正人
デザインガイア2013 2013.11
More details
Language:Japanese Presentation type:Oral presentation (general)
パス解析を用いた並列実行時メモリ読み書き順序の変化検出 International conference
杉山 由芳, 枝廣 正人
ETNET2017 2017.3.9
More details
Language:Japanese Presentation type:Oral presentation (general)
ハードウェア抽象化記述SHIMによる性能見積のためのLLVM-IR命令実行時間計測手法 International conference
鳥越 敬, 枝廣 正人
ETNET2020 2020.2.28
More details
Language:Japanese Presentation type:Oral presentation (general)
ハードウェア抽象化記述SHIMとSHIMulatorによるソフトウェア動的性能見積手法 International conference
佐合 惇, 枝廣 正人
ETNET2019 2019.3.17
More details
Language:Japanese Presentation type:Oral presentation (general)
ニューラルネットによるモデル予測制御高速化 International conference
竹松 慎弥, 嶋岡 雅浩, 道木 慎二, 枝廣 正人
ETNET2018 2018.3.7
More details
Language:Japanese Presentation type:Oral presentation (general)
ソフトウェア向けハードウェア性能記述を用いたマルチコアにおける性能見積り International conference
西村 裕, 中村 陸, 荒川 文男, 枝廣 正人
ETNET 2014.3.16
More details
Language:Japanese Presentation type:Oral presentation (general)
ソフトのための国際標準ハードウェアモデル記述SHIM 1.0による性能見積とSHIM2.0への方向性 International conference
枝廣 正人
組込みマルチコアサミット2017West 2017.7.13
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
ソフトのための国際標準ハードウェアモデル記述SHIM 1.0による性能見積とSHIM2.0への方向性 International conference
枝廣 正人
組込みマルチコアサミット2016 2016.11.17
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
システムレベル設計における制御システム向けプロファイル機構",情報処理学会研究報告 International conference
繆 同徳, 安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
デザインガイア2014 2014.11
More details
Language:Japanese Presentation type:Oral presentation (general)
Simulinkモデルベース自動並列化とSHIM International conference
枝廣 正人
組込みマルチコアサミット2014 2014.11.20
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
Simulinkモデルから状態方程式・出力方程式の抽出 International conference
池田 良裕, 枝廣 正人
第41回組込みシステム研究会 2016.6.2
More details
Language:Japanese Presentation type:Poster presentation
Simulinkモデルからのブロックレベル並列化 International conference
枝廣 正人
組込みマルチコアサミット2015 2015.11.19
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
SimulinkモデルからCPUとアクセラレータの併用コードの作成手法 International conference
甲斐琢朗, 森裕司(NSITEXE, 枝廣正人
ETNET2020 2020.2.28
More details
Language:Japanese Presentation type:Oral presentation (general)
MBP(モデルベース並列化)を用いたクロスレイヤ設計 International conference
枝廣 正人
組込みマルチコアサミット2017 2017.11.16
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
Improving Core Allocation of Simulink Model for Embedded Multi-core Systems
S. Kojima, M. Edahiro, T. Azumi
IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2017) 2017.8.16
More details
Language:English Presentation type:Poster presentation
Hardware Multitasking in Dynamically Partially Reconfigurable FPGA-based Embedded Systems
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
International SoC Design Conference (ISOCC) 2011.11
More details
Language:English Presentation type:Oral presentation (invited, special)
EMC活動の紹介とビジョン International conference
枝廣 正人
組込み向け マルチ・メニーコア ソフトウェア開発 テクニカルセミナー 2018.9.4
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
モデルベース開発におけるKALRAY MPPA メニーコア向け並列化 International conference
鍾 兆前, 枝廣 正人
情報処理学会全国大会 2017.3.16
More details
Language:Japanese Presentation type:Oral presentation (general)
高位合成によるSTPエンジン及びFPGAへのAES/ADPCMの実装と評価 International conference
石田 薫史, 柴田 誠也, 安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
電子情報通信学会リコンフィギャラブル研究会 2012.5
More details
Language:Japanese Presentation type:Oral presentation (general)
階層構造を持つメニーコアアーキテクチャへのタスクマッピング International conference
油谷 創, 枝廣 正人
第34回組込みシステム研究発表会 2014.9.17 Y. Ando, Shinya Honda, Hiroaki Takada andMasato Edahiro
More details
Language:Japanese Presentation type:Oral presentation (general)
組込みメニーコアに向けた (OSと)制御アプリ並列化 International conference
枝廣 正人
SWEST 2013.8.23
More details
Language:Japanese Presentation type:Symposium, workshop panel (nominated)
組込みマルチ・メニーコアの現状とソフトウェア International conference
枝廣 正人
Embedded Technology 2011.11.18
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアコンソーシアム概要 International conference
枝廣 正人
組込みマルチコアサミット2014 2014.11.20
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアコンソーシアムについて International conference
枝廣 正人
組込みマルチコアサミット2018 2018.11.15
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアコンソーシアムについて International conference
枝廣 正人
組込みマルチコアサミット2019 2019.11.21
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアコンソーシアムについて International conference
枝廣 正人
組込みマルチコアサミット2015 2015.11.19
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアコンソーシアムについて International conference
枝廣 正人
組込みマルチコアサミット2017West 2017.7.13
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアコンソーシアムについて International conference
枝廣 正人
組込みマルチコアサミット2017 2017.11.16
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアコンソーシアムについて International conference
枝廣 正人
組込みマルチコアサミット2016 2016.11.17
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアとソフトウェア International conference
枝廣 正人
中部エレクトロニクスショー 2011.11.15
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
組込みマルチコアECU活用に向けた内部モデル制御の効率的な並列実装 International conference
鈴木 悠太, 佐多 宏太, 加古 純一, 枝廣 正人
制御部門マルチシンポジウム 2014.3.7
More details
Language:Japanese Presentation type:Symposium, workshop panel (public)
組込みシステムでの マルチ・メニーコアプロセッサ利用に向けて ~ SHIMとモデルベース並列化 ~ International conference
枝廣 正人
CEATEC 2015.10.9
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
永久磁石同期モータ電流制御系のための予測制御アルゴリズム並列化 International conference
竹松 慎弥, 道木 慎二, 嶋岡 雅浩, 枝廣 正人
第41回組込みシステム研究会 2016.6.2
More details
Language:Japanese Presentation type:Oral presentation (general)
永久磁石同期モータ電流制御系のための予測制御アルゴリズム並列化 International conference
竹松 慎弥, 市村 駿太郎, 岩間 拓也, 嶋岡 雅浩, 道木 慎二, 枝廣 正人
情報処理学会全国大会 2017.3.16
More details
Language:Japanese Presentation type:Oral presentation (general)
差分方程式の解析的な並列化とそのモデリング International conference
鈴木 悠太, 枝廣 正人
情報処理学会組込みシステム研究会 2013.9.10
More details
Language:Japanese Presentation type:Oral presentation (general)
単方向1:1高速同期機構を用いた組込み制御並列化 International conference
中村 陸, 荒川 文男, 枝廣 正人
情報処理学会組込みシステム研究会 2013.11.26
More details
Language:Japanese Presentation type:Oral presentation (general)
単方向1:1高速同期機構を用いた組込み制御並列化 International conference
中村 陸, 枝廣 正人
情報処理学会組込みシステムシンポジウム 2013.10.17
More details
Language:Japanese Presentation type:Poster presentation
単方向1:1高速同期機構を用いたFPGA実装と評価 International conference
溝口 裕哉, 中村 陸, 安藤 友樹, 荒川 文男, 枝廣 正人
ETNET 2014.3.16
More details
Language:Japanese Presentation type:Oral presentation (general)
割込み処理を考慮したシステムレベル設計手法 International conference
安藤 友樹, 石田 薫史, 本田 晋也, 高田 広章, 枝廣 正人
デザインガイア2013 2013.11
More details
Language:Japanese Presentation type:Oral presentation (general)
割込みハンドラのハードウェア化を実現するシステムレベル設計手法", 情報処理学会研究報告 International conference
安藤 友樹, 本田 晋也, 高田 広章, 枝廣 正人
デザインガイア2014 2014.11
More details
Language:Japanese Presentation type:Oral presentation (general)
制御モデルに内在する遅延を用いた並列化 International conference
池田 良裕, 鈴木 悠太(デンソ, 峰田 憲一(デンソ, 森 裕司(デンソー, 井上 雅理, 道木 慎二, 枝廣 正人
ETNET2018 2018.3.7
More details
Language:Japanese Presentation type:Oral presentation (general)
共有メモリ付階層型制御モデルの並列化アルゴリズムのCSPによる形式化とFDRによる検証 International conference
于文博, 磯部 祥尚, 枝廣 正人
ETNET2020 2020.2.28
More details
Language:Japanese Presentation type:Oral presentation (general)
レガシコードを含むモデルベース開発における並列化手法 International conference
黒柳 彰宏, 金森公洋, 枝廣 正人
ETNET2019 2019.3.17
More details
Language:Japanese Presentation type:Oral presentation (general)
モータ制御系のマルチコア実装時における並列度向上に向けて遅延を導入した電流制御系の解析 International conference
キム ジンス, 井上 雅理, 加藤 聖也, 黒柳 彰宏, 枝廣 正人, 道木 慎二
平成31年電気学会全国大会論文集 2019.3.1
More details
Language:Japanese Presentation type:Oral presentation (invited, special)
モデル解析によるマルチレートSimulinkモデル並列化 International conference
池田 良裕, 市橋 友樹, 仲田 壮佑, 枝廣 正人
情報処理学会全国大会 2017.3.16
More details
Language:Japanese Presentation type:Oral presentation (general)
モデル解析によるマルチレートSimulinkモデルの性能向上 International conference
池田 良裕, 鈴木 均(ルネサス, エレクトロニクス, 枝廣 正人
ETNET2017 2017.3.9
More details
Language:Japanese Presentation type:Oral presentation (general)
モデル予測制御における非線形漸化式実行の並列化 International conference
山田 竜正, 枝廣 正人
ETNET2015 2015.3.6
More details
Language:Japanese Presentation type:Oral presentation (general)
モデルベース開発におけるマルチ・メニーコア向け自動並列化 International conference
鍾 兆前, 枝廣 正人
ETNET2017 2017.3.9
More details
Language:Japanese Presentation type:Oral presentation (general)
モデルベース開発におけるデータ並列化に関する検討 International conference
竹松 慎弥, 枝廣 正人
ETNET2017 2017.3.9
More details
Language:Japanese Presentation type:Oral presentation (general)
MBP (Model-Based Parallelization)
モデルベース開発からTOPPERS搭載システムへのクロスレイヤ自動設計を利用したマルチコアモータ制御実装
More details
~第7回TOPPERS活用アイデア・アプリ ケーション開発コンテスト 銅賞
~ 組込みシステムシンポジウム2017 優秀ポスター賞
MBP (Model-Based Parallelization)
モデルベース開発からTOPPERS搭載システムへのクロスレイヤ自動設計を利用したマルチコアモータ制御実装
More details
~第7回TOPPERS活用アイデア・アプリ ケーション開発コンテスト 銅賞
~ 組込みシステムシンポジウム2017 優秀ポスター賞
スケーラブルなエッジHPCを実 現するOS統合型プラットフォー ムの研究開発
2018.7 - 2021.2
高効率・高速 処理を可能と するAIチップ ・次世代コン ピューティン グの技術開発
本村真人
More details
Grant type:Competitive
Model-Based Parallelization MBP (Simulink, C/C++, AMALTHEA)
2013.4
Cooperative Research within Japan
多様なマルチ・メニーコアの高度な活用を可能にする標準プラットフォーム開発とエコシステム構築による省エネルギー技術の実用化
2013.1 - 2015.2
平成24年度 戦略的省エネルギー技術革新プログラム
More details
Grant type:Competitive
マルチ・メニーコア向けソフトウェアプラットフォーム
2011.4
国内共同研究
Grant number:16H02800 2016.4 - 2019.3
Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
Edahiro Masato, HONDA Shinya
More details
Authorship:Principal investigator
Grant amount:\17160000 ( Direct Cost: \13200000 、 Indirect Cost:\3960000 )
In this research, in order to establish a highly parallel embedded control system design and implementation method for the multi-many-core processor that mounts multiple processors on one semiconductor chip, we made four achievement: (a) established a control algorithm to realize high parallelism, (b) established a cross-layer design method, which is a co-design method between control and parallel software design, aiming at higher multi-core utilization, and demonstrated it in an actual environment with awareness of vehicle control, (c) proposed a method for minimizing the maximum execution time in parallelization for model-based development, and (d) proposed a method for high-speed embedded control simulation using PCs.
Task Mapping for Hierarchical Many-core Processors in Embedded Systems
Grant number:24500058 2012.4 - 2015.3
Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)
EDAHIRO MASATO, ABRADANI Sou
More details
Authorship:Principal investigator
Grant amount:\5200000 ( Direct Cost: \4000000 、 Indirect Cost:\1200000 )
In this research, we proposed a task mapping method that considers features of task graphs and performance characteristics of hierarchical many-core architectures.
We proposed the "HCME" toward task mapping method for "CMesh" which is a type of hierarchical many-core architectures. We also proposed a merge technique required when there are more number of tasks than the number of cores.
We compared our proposed mapping method with existing algorithms. As a result of evaluation experiments, our proposed method reduced communication cost and application completion time.
スケーラブルなエッジHPCを実 現するOS統合型プラットフォー ムの研究開発
2018.7 - 2021.2
NEDO 高効率・高速 処理を可能と するAIチップ ・次世代コン ピューティン グの技術開発
本村真人, 権藤正樹(eSOL
More details
Grant type:Competitive
マルチ・メニーコア向け高並列組み込み制御システム設計・実装手法の研究
2016.4 - 2019.3
科学研究費補助金 基盤研究(B)
枝廣 正人
More details
Authorship:Principal investigator
階層型組み込みメニーコア向けタスク配置手法の研究
2012.4 - 2015.3
科学研究費補助金 基盤研究(C)
More details
Authorship:Principal investigator
Development of Low Energy Processor Architecture
Grant number:24300012 2012.4 - 2015.3
Japan Society for the Promotion of Science Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
MOTOMURA MASATO, ASAI Tetsuya, EDAHIRO Masato, ASAI Tetsuya, EDAHIRO Masato
More details
Authorship:Collaborating Investigator(s) (not designated on Grant-in-Aid)
We have developed a processor architecture which features restricted dynamic reconfiguration of datapath for the sake of keeping general-purposeness and low-powerness at the same time, targeting toward embedded system application where those two features are mandatory requirement. We have named the architecure is named Control-Flow Driven Data-Flow Switching (CDDS), and conducted detailed design and test chip design. Through measurement of the fabricated test chip, we have confirmed reasonable power reduction by the proposed architecture. We have presented the results at one of major international conferences in circuit design, A-SSCC, and showed demonstration of the chip successfully.
階層型組み込みメニーコア向けタスク配置手法の研究
2012.4 - 2015.3
日本学術振興会 科学研究費助成事業 基盤研究(C)
More details
Grant type:Competitive
CONTROL DEVICE DESIGN METHOD AND CONTROL DEVICE
佐多宏太(トヨタ自動車) 、加古純一(トヨタ自動車) 、渡邊智(トヨタ自動車) 、鈴木悠太 、枝廣正人
More details
Patent/Registration no:EP2960727 Date registered:2018.5
Country of applicant:Foreign country
CONTROL DEVICE
佐多宏太(トヨタ自動車) 、加古純一(トヨタ自動車) 、渡邊智(トヨタ自動車) 、鈴木悠太 、枝廣正人
More details
Patent/Registration no:EP2960728 Date registered:2019.2
Country of applicant:Foreign country
CONTROL DEVICE DESIGN METHOD AND CONTROL DEVICE
佐多宏太(トヨタ自動車) 、加古純一(トヨタ自動車) 、渡邊智(トヨタ自動車) 、鈴木悠太 、枝廣正人
More details
Patent/Registration no:US10241483 Date registered:2019.3
Country of applicant:Foreign country
制御装置の設計方法及び制御装置
佐多宏太(トヨタ自動車) 、加古純一(トヨタ自動車) 、渡邊智(トヨタ自動車) 、鈴木悠太 、枝廣正人
More details
Patent/Registration no:5932128 Date registered:2015.3
Country of applicant:Domestic
制御装置
佐多宏太(トヨタ自動車) 、加古純一(トヨタ自動車) 、渡邊智(トヨタ自動車) 、鈴木悠太 、枝廣正人
More details
Patent/Registration no:5714622 Date registered:2015.3
Country of applicant:Domestic
CONTROL DEVICE DESIGN METHOD AND CONTROL DEVICE
佐多宏太(トヨタ自動車) 、加古純一(トヨタ自動車) 、渡邊智(トヨタ自動車) 、鈴木悠太 、枝廣正人
More details
Patent/Registration no:ZL201480008525.8 Date registered:2017.6
Country of applicant:Foreign country
CONTROL DEVICE
佐多宏太(トヨタ自動車) 、加古純一(トヨタ自動車) 、渡邊智(トヨタ自動車) 、鈴木悠太 、枝廣正人
More details
Patent/Registration no:ZL201480008444.8 Date registered:2017.5
Country of applicant:Foreign country
マルチプロセッサシステム、マルチプロセッサシステムにおけるシステム構成方法及びそのプログラム
井上浩明 、酒井淳嗣 、阿部剛 、枝廣正人
More details
Patent/Registration no:5370936 Date registered:2013.9
Country of applicant:Domestic
並列ソート装置、方法、およびプログラム
枝廣正人 、山下慶子
More details
Patent/Registration no:5304251 Date registered:2013.7
Country of applicant:Domestic
経路探索方法および経路探索装置
枝廣正人 、山下慶子
More details
Patent/Registration no:5164028 Date registered:2012.12
Country of applicant:Domestic
情報通信処理装置、情報通信端末、情報通信システム、機能切替方法及び機能切替プログラム
井上浩明 、枝廣正人
More details
Patent/Registration no:5621191 Date registered:2014.10
Country of applicant:Domestic
半導体集積回路及びフィルタ制御方法
井上浩明 、高木将通 、上久保雅規 、鳥居淳 、枝廣正人
More details
Patent/Registration no:5287718 Date registered:2013.6
Country of applicant:Domestic
情報処理装置、実行環境転送方法及びそのプログラム
井上浩明 、阿部剛 、酒井淳嗣 、枝廣正人
More details
Patent/Registration no:5273043 Date registered:2013.5
Country of applicant:Domestic
半導体集積回路及びフィルタ制御方法
井上浩明 、高木将通 、上久保雅規 、鳥居淳 、枝廣正人
More details
Patent/Registration no:5246158 Date registered:2013.4
Country of applicant:Domestic
マルチプロセッサシステム、マルチプロセッサシステムにおけるシステム構成方法及びそのプログラム
井上浩明 、酒井淳嗣 、阿部剛 、枝廣正人
More details
Patent/Registration no:4947441 Date registered:2012.3
Country of applicant:Domestic
情報通信装置及びプログラム実行環境制御方法
井上浩明 、酒井淳嗣 、阿部剛 、枝廣正人
More details
Patent/Registration no:4811271 Date registered:2011.9
Country of applicant:Domestic
情報処理装置、復旧装置、プログラム及び復旧方法
井上浩明 、酒井淳嗣 、阿部剛 、上久保雅規 、鈴木紀章 、枝廣正人
More details
Patent/Registration no:4556144 Date registered:2010.7
Country of applicant:Domestic
並列処理システム及び並列処理プログラム
井上浩明 、伊藤義行 、酒井淳嗣 、枝廣正人
More details
Patent/Registration no:4196333 Date registered:2008.10
Country of applicant:Domestic
並列処理システム及び並列処理プログラム
井上浩明 、伊藤義行 、酒井淳嗣 、枝廣正人
More details
Patent/Registration no:4171910 Date registered:2008.8
Country of applicant:Domestic
並列処理システム及び並列処理プログラム
井上浩明 、伊藤義行 、酒井淳嗣 、枝廣正人
More details
Patent/Registration no:4062441 Date registered:2008.1
Country of applicant:Domestic
シングルプロセッサ向けOSによる並列処理システム、並列処理プログラム
井上浩明、伊藤義行、酒井淳嗣、枝廣正人
More details
Patent/Registration no:4051703 Date registered:2007.12
Country of applicant:Domestic
シングルプロセッサ向けOSによる並列処理システム
井上浩明、枝廣正人、伊藤義行、酒井淳嗣、皆上徹也
More details
Patent/Registration no:3969308 Date registered:2007.6
Country of applicant:Domestic
レーザ加工装置
尾野間香美、枝廣正人
More details
Patent/Registration no:3052928 Date registered:2000.4
Country of applicant:Domestic
クロック分配回路
枝廣正人
More details
Patent/Registration no:2778572 Date registered:1998.5
Country of applicant:Domestic
クロック分配回路
枝廣 正人
More details
Patent/Registration no:2699831 Date registered:1997.9
Country of applicant:Domestic
CONTROL DEVICE DESIGN METHOD AND CONTROL DEVICE
佐多宏太, トヨタ自動車, 加古純一, トヨタ自動車, 渡邊智(トヨタ自動車, 鈴木悠太, 枝廣正人
More details
Patent/Registration no:US10241483 Date issued:2019.3
CONTROL DEVICE
佐多宏太, トヨタ自動車, 加古純一, トヨタ自動車, 渡邊智(トヨタ自動車, 鈴木悠太, 枝廣正人
More details
Patent/Registration no:EP2960728 Date issued:2019.2
経路探索方法および経路探索装置
枝廣正人, 山下慶子
More details
Patent/Registration no:5164028 Date issued:2012.12
情報通信装置及びプログラム実行環境制御方法
井上浩明, 酒井淳嗣, 阿部剛, 枝廣正人
More details
Patent/Registration no:4811271 Date issued:2011.9
情報通信処理装置、情報通信端末、情報通信システム、機能切替方法及び機能切替プログラム
井上浩明, 枝廣正人
More details
Patent/Registration no:5621191 Date issued:2014.10
情報処理装置、復旧装置、プログラム及び復旧方法
井上浩明, 酒井淳嗣, 阿部剛, 上久保雅規, 鈴木紀章, 枝廣正人
More details
Patent/Registration no:4556144 Date issued:2010.7
情報処理装置、実行環境転送方法及びそのプログラム
井上浩明, 阿部剛, 酒井淳嗣, 枝廣正人
More details
Patent/Registration no:5273043 Date issued:2013.5
半導体集積回路及びフィルタ制御方法
井上浩明, 高木将通, 上久保雅規, 鳥居淳, 枝廣正人
More details
Patent/Registration no:5287718 Date issued:2013.6
半導体集積回路及びフィルタ制御方法
井上浩明, 高木将通, 上久保雅規, 鳥居淳, 枝廣正人
More details
Patent/Registration no:5246158 Date issued:2013.4
制御装置の設計方法及び制御装置
佐多宏太, トヨタ自動車, 加古純一, トヨタ自動車, 渡邊智(トヨタ自動車, 鈴木悠太, 枝廣正人
More details
Patent/Registration no:5932128 Date issued:2015.3
制御装置
佐多宏太, トヨタ自動車, 加古純一, トヨタ自動車, 渡邊智(トヨタ自動車, 鈴木悠太, 枝廣正人
More details
Patent/Registration no:5714622 Date issued:2015.3
並列処理システム及び並列処理プログラム
井上浩明, 伊藤義行, 酒井淳嗣, 枝廣正人
More details
Patent/Registration no:4196333 Date issued:2008.10
並列処理システム及び並列処理プログラム
井上浩明, 伊藤義行, 酒井淳嗣, 枝廣正人
More details
Patent/Registration no:4171910 Date issued:2008.8
並列処理システム及び並列処理プログラム
井上浩明, 伊藤義行, 酒井淳嗣, 枝廣正人
More details
Patent/Registration no:4062441 Date issued:2008.1
並列ソート装置、方法、およびプログラム
枝廣正人, 山下慶子
More details
Patent/Registration no:5304251 Date issued:2013.7
レーザ加工装置
尾野間香美, 枝廣正人
More details
Patent/Registration no:3052928 Date issued:2000.4
マルチプロセッサシステム、マルチプロセッサシステムにおけるシステム構成方法及びそのプログラム
井上浩明, 酒井淳嗣, 阿部剛, 枝廣正人
More details
Patent/Registration no:5370936 Date issued:2013.9
マルチプロセッサシステム、マルチプロセッサシステムにおけるシステム構成方法及びそのプログラム
井上浩明, 酒井淳嗣, 阿部剛, 枝廣正人
More details
Patent/Registration no:4947441 Date issued:2012.3
シングルプロセッサ向けOSによる並列処理システム、並列処理プログラム
井上浩明, 伊藤義行, 酒井淳嗣, 枝廣正人
More details
Patent/Registration no:4051703 Date issued:2007.12
シングルプロセッサ向けOSによる並列処理システム
井上浩明, 枝廣正人, 伊藤義行, 酒井淳嗣, 皆上徹也
More details
Patent/Registration no:3969308 Date issued:2007.6
クロック分配回路
枝廣正人
More details
Patent/Registration no:2778572 Date issued:1998.5
クロック分配回路
枝廣 正人
More details
Patent/Registration no:2699831 Date issued:1997.9
CONTROL DEVICE DESIGN METHOD AND CONTROL DEVICE
佐多宏太, トヨタ自動車, 加古純一, トヨタ自動車, 渡邊智(トヨタ自動車, 鈴木悠太, 枝廣正人
More details
Patent/Registration no:EP2960727 Date issued:2018.5
Informatics 1
2022
Logic Design 2
2022
Logic Design 2
2022
Logic Design 1
2022
Logic Design 1
2022
Computer Architecture A
2022
Introduction to Information Science
2021
Informatics 1
2021
Logic Design 2
2021
Logic Design 2
2021
Logic Design 1
2021
Logic Design 1
2021
Computer Architecture A
2021
Logic Circuits with Exercises
2021
Introduction to Information Science
2020
Logic Circuits with Exercises
2020
Logic Design 2
2020
Logic Design 2
2020
Logic Design 1
2020
Logic Design 1
2020
Informatics 1
2020
計算機アーキテクチャ特論A
2020
情報科学入門
2019
詳細を見る
情報科学に必要な基礎理論.自分自身は確率・統計を担当
インフォマティクス1
2019
論理設計及び演習1、2
2019
詳細を見る
論理回路の基本
基礎セミナー
2019
計算機アーキテクチャ特論A
2019
詳細を見る
並列アーキテクチャの基本
インフォマティクス1
2018
論理設計及び演習1、2
2018
詳細を見る
論理回路の基本
計算機アーキテクチャ特論A
2018
詳細を見る
並列アーキテクチャの基本
情報科学入門
2018
詳細を見る
情報科学に必要な基礎理論.自分自身は確率・統計を担当
情報リテラシ(理系)
2018
情報リテラシ(理系)
2017
基礎セミナー
2017
情報科学入門
2017
詳細を見る
情報科学に必要な基礎理論.自分自身は確率・統計を担当
論理回路及び演習
2017
詳細を見る
論理回路の基本
計算機アーキテクチャ特論A
2017
詳細を見る
並列アーキテクチャの基本
インフォマティクス1
2017
基礎セミナー
2016
情報科学入門
2016
詳細を見る
情報科学に必要な基礎理論.自分自身は確率・統計を担当
論理回路及び演習
2016
詳細を見る
論理回路の基本
計算機アーキテクチャ特論
2016
詳細を見る
並列アーキテクチャの基本
情報科学入門
2015
詳細を見る
情報科学に必要な基礎理論.自分自身は確率・統計を担当
情報リテラシ(理系)
2015
集積システム設計特論
2015
詳細を見る
特にハードウェアのシステム設計
計算機アーキテクチャ特論
2015
詳細を見る
並列アーキテクチャの基本
論理回路及び演習
2015
詳細を見る
論理回路の基本
情報科学入門
2014
詳細を見る
情報科学に必要な基礎理論.自分自身は確率・統計を担当
計算機アーキテクチャ特論
2014
詳細を見る
並列アーキテクチャの基本
論理回路及び演習
2014
詳細を見る
論理回路の基本
計算機アーキテクチャ特論
2013
詳細を見る
並列アーキテクチャの基本
情報リテラシ(理系)
2013
基礎セミナー
2013
論理回路及び演習
2013
詳細を見る
論理回路の基本
集積システム設計特論
2013
詳細を見る
特にハードウェアのシステム設計
計算機アーキテクチャ特論
2012
詳細を見る
並列アーキテクチャの基本
情報リテラシ(理系)
2012
基礎セミナー
2012
論理回路及び演習
2012
詳細を見る
論理回路の基本
集積システム設計特論
2011
詳細を見る
特にハードウェアのシステム設計
論理回路及び演習
2011
詳細を見る
論理回路の基本
出前授業
Role(s):Lecturer
愛知県立知立東高等学校 2019.8
More details
Audience: High school students
Type:Visiting lecture
出前授業
Role(s):Lecturer
愛知県立知立東高等学校 2018.8
More details
Audience: High school students
Type:Visiting lecture
模擬授業
Role(s):Lecturer
2016.12
More details
Audience: Junior students
Type:Visiting lecture
私立滝中学校向け
Copyright © Nagoya University