Publisher：Proceedings - 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024  

In this study, support vector machine (SVM) performance was assessed using a quantum-inspired complementary metal-oxide semiconductor (CMOS) annealer. During performance evaluation, the accuracy rate in binary classification problems was the primary focus. SVM performance, when running on a CPU (classical computation) and quantum-inspired annealer, was comparatively analyzed. The performance outcome was evaluated using a CMOS annealing machine, and accuracy rates of 93.7%, 92.7%, and 97.6% were obtained for linearly separable problem and nonlinearly separable problems 1 and 2, respectively. According to these results, a CMOS annealing machine can achieve an accuracy rate that closely rivals that of classical computation.

DOI： 10.1109/MCSoC64144.2024.00094

Scopus

Publisher：Proceedings - 2024 IEEE International Conference on Cluster Computing Workshops, CLUSTER Workshops 2024  

For future high-resolution atmospheric simulations, a dynamical core using the discontinuous Galerkin Method (DGM), called SCALE-DG [1], is being developed as an option for high-order fluid schemes in the SCALE library [2]. Compared to the traditional Finite Element Method (FEM), the DGM allows for discontinuities across element boundaries. When evaluating a first-order derivative operator, we use the values at nodes of own element and at common boundaries of neighbor elements. This feature allows most computations to be performed independently for each element. Thus, we can take full advantage of data locality. Additionally, the DGM can achieve high-order accuracy by choosing high-order polynomial basis functions within each element. Therefore, DGM is suitable for high-resolution atmospheric simulations with high-order numerical accuracy, and we expect the computational performance to be highly desirable on modern computer architectures.

DOI： 10.1109/CLUSTERWORKSHOPS61563.2024.00033

Web of Science

Scopus

Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/candar60563.2023.00031

Scopus

Language：Japanese   Publisher：The Japanese Society of Medical Imaging Technology  

<p>With the development of medical imaging technology, various techniques have been developed and used to visually understand the inside of the living body. However, these technologies can only directly obtain images and videos, and diagnosis is still performed by human hands, such as physicians. There are great expectations for software that can reduce such labor, and an increasing number of technologies are already being used in the field of medicine, but the target is limited because they require knowledge and skills in both medicine (medical imaging) and computing technology. Therefore, in this study, researchers in the medical imaging and high-performance computing fields are collaborating to accelerate and scale up the image reconstruction of PET. This paper describes the details of this effort and the results obtained so far.</p>

DOI： 10.11409/mit.41.150

CiNii Research

Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/IPDPSW59300.2023.00115

Web of Science

Scopus

Other Link： https://dblp.uni-trier.de/db/conf/ipps/ipdps2023w.html#HashinokiOKNH23

Publishing type：Research paper (scientific journal)   Publisher：Oxford University Press (OUP)  

Summary

Large-scale earthquake sequence simulations using the boundary element method (BEM) incur extreme computational costs through multiplying a dense matrix with a slip rate vector. Hierarchical matrices (H-matrices) have often been used to accelerate this multiplication. However, the complexity of the structures of the H-matrices and the communication costs between processors limit their scalability, and they therefore cannot be used efficiently in distributed memory computer systems. Lattice H-matrices have recently been proposed as a tool to improve the parallel scalability of H-matrices. In this study, we developed a method for earthquake sequence simulations applicable to 3D nonplanar faults with lattice H-matrices. We present a simulation example and verify the mesh convergence of our method for a 3D nonplanar thrust fault using rectangular and triangular discretizations. We also performed performance and scalability analyses of our code. Our simulations, using over ${10^5}$ degrees of freedom, demonstrated a parallel acceleration beyond ${10^4}$ MPI processors and a &amp;gt; 10-fold acceleration over the best performance when the normal H-matrices are used. Using this code, we can perform unprecedented large-scale earthquake sequence simulations on geometrically complex faults with supercomputers. The software is made an open-source and freely available.

DOI： 10.1093/gji/ggac386

arXiv

Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/CLUSTER51413.2022.00056

Other Link： https://dblp.uni-trier.de/db/conf/cluster/cluster2022.html#HoshinoIH22

CiNii Research

CiNii Research

CiNii Research

CiNii Research

Publishing type：Research paper (international conference proceedings)  

DOI： 10.1007/s11548-018-1766-y

Language：Japanese  

J-GLOBAL

Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

DOI： 10.1109/CLUSTER.2018.00016

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Springer Verlag  

Parallel Boundary Element Method (BEM) analyses are typically conducted using a purpose-built software framework called BEM-BB. This framework requires a user-defined function program that calculates the i-th row and the j-th column of the coefficient matrix arising from the convolution integral term in the fundamental BEM equation. Owing to this feature, the framework can encapsulate MPI and OpenMP hybrid parallelization with H-matrix approximation. Therefore, users can focus on implementing a fundamental solution or a Green’s function, which is the most important element in BEM and depends on the targeted physical phenomenon, as a user-defined function. However, the framework does not consider single instruction multiple data (SIMD) vectorization, which is important for high-performance computing and is supported by the majority of existing processors. Performing SIMD vectorization of a user-defined function is difficult because SIMD exploits instruction-level parallelization and is closely associated with the user-defined function. In this paper, a conceptual framework for enhancing SIMD vectorization is proposed. The proposed framework is evaluated using two BEM problems, namely, static electric field analysis with a perfect conductor and static electric field analysis with a dielectric, on Intel Broadwell (BDW) processor and Intel Xeon Phi Knights Landing (KNL) processor. It offers good vectorization performance with limited SIMD knowledge, as can be verified from the numerical results obtained herein. Specifically, in perfect conductor analyses conducted using the H-matrix, the framework achieved performance improvements of 2.22x and 4.34x compared to the original BEM-BB framework for the BDW processor and KNL, respectively.

DOI： 10.1007/978-3-319-93698-7_46

Scopus

Language：Japanese  

J-GLOBAL

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

J-GLOBAL

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Directive-based programming interfaces such as OpenACC and OpenMP are becoming more prevalent in application development targeting accelerators, in particular when porting existing CPU-only code. Unlike vendor-specific alternatives such as CUDA, they are designed to be portable across different accelerators, and therefore once necessary directives are added to an existing CPU-only code, it can be executed on different accelerator architectures depending on the availability of supporting compilers. However, it does not automatically mean that such code runs efficiently on different architectures, and in fact, architecture-specific coding such as choosing optimal data layouts is almost mandatory for optimal performance, imposing a significant burden if implemented manually. Towards realizing performance portability in accelerator programming, we propose a set of extended directives that allow the programmer to optimize data layouts for a given accelerator without modifying original program code. Unlike the manual approach, the code change is confined in the directives with the original code kept as it is. This paper evaluates the effectiveness of our proposed extensions in the OpenACC standard by extending UPACS and CCS-QCD OpenACC applications. A prototype source-to-source translator for the extensions achieves 123% and 120% of the baseline performance, respectively, which are comparable to manually tuned versions.

DOI： 10.1109/HPCC-SmartCity-DSS.2016.34

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

OpenACC is gaining momentum as an implicit and portable interface in porting legacy CPU-based applications to heterogeneous, highly parallel computational environment involving many-core accelerators such as GPUs and Intel Xeon Phi. OpenACC provides a set of loop directives similar to OpenMP for the parallelization and also to manage data movement, attaining functional portability across different heterogeneous devices
however, the performance portability of OpenACC is said to be insufficient due to the characteristics of different target devices, especially those regarding memory layouts, as automated attempts by the compilers to adapt is currently difficult. We are currently working to propose a set of directives to allow compilers to have better semantic information for adaptation
here, we particularly focus on data layout such as Structure of Arrays, advantageous data structure for GPUs, as opposed to Array of Structures, which exhibits good performance on CPUs. We propose a directive extension to OpenACC that allows the users to flexibility specify optimal layouts, even if the data structures are nested. Performance results show that we gain as much as 96 % in performance for CPUs and 165% for GPUs compared to programs without such directives, essentially attaining both functional and performance portability in OpenACC.

DOI： 10.1109/WACCPD.2014.12

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

OpenACC is a new accelerator programming interface that provides a set of OpenMP-like loop directives for the programming of accelerators in an implicit and portable way. It allows the programmer to express the offloading of data and computations to accelerators, such that the porting process for legacy CPU-based applications can be significantly simplified. This paper focuses on the performance aspects of OpenACC using two microbenchmarks and one real-world computational fluid dynamics application. Both evaluations show that in general OpenACC performance is approximately 50% lower than CUDA. However, for some applications it can reach up to 98% with careful manual optimizations. The results also indicate several limitations of the OpenACC specification that hamper full use of the GPU hardware resources, resulting in a significant performance gap when compared to a highly tuned CUDA code. The lack of a programming interface for the shared memory in particular results in as much as three times lower performance.

DOI： 10.1109/CCGrid.2013.12

Web of Science

J-GLOBAL

Language：Japanese   Publisher：小宮山印刷工業  

CiNii Books

Language：Japanese   Publisher：日本計算工学会  

J-GLOBAL

J-GLOBAL

J-GLOBAL

J-GLOBAL

Authorship：Lead author  

J-GLOBAL

J-GLOBAL

J-GLOBAL

Language：Japanese  

J-GLOBAL

Language：English  

Language：Japanese  

J-GLOBAL

Language：Japanese  

J-GLOBAL

Language：Japanese  

J-GLOBAL

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J-GLOBAL

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J-GLOBAL

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J-GLOBAL

Language：Japanese   Publisher：一般社団法人情報処理学会  

近年増加傾向にある GPU 等のアクセラレータを搭載した計算環境への既存プログラムの移植方法として，CUDA・OpenCL に代表されるローレベルなプログラミングモデルを用いる方法に対し，ディレクティブベースの OpenACC のようなハイレベルなプログラミングモデルを用いる方法が注目されている．このようなディレクティブベースのプログラミングモデルの利点として，元のプログラムを維持したまま移植を行えるために，デバイス間の機能的な可搬性が高いことがあげられる．しかし現状の OpenACC などの High-level なプログラミングモデルは，スカラプロセッサとメニーコアアクセラレータの得意とするデータレイアウトの相違に対応することが出来ず，異なる性質を持ったデバイス間の性能可搬性に問題がある．そこで本研究では，データレイアウトを抽象化し，異なるデバイス間での性能可搬性を向上させるための OpenACC の拡張ディレクティブを試作し，姫野ベンチマークのデータレイアウトをトランスレーターにより変更し，マルチコア CPU，Intex Xeon Phi，K20X GPU のそれぞれで評価を行った．その結果，オリジナルと同一のデータレイアウトと比較して，Intel Xeon Phi では 27%，K20X GPU では 24%の性能向上が得られることを確認した．

CiNii Books

Language：Japanese   Publisher：一般社団法人情報処理学会  

近年増加傾向にある GPU 等のアクセラレータを搭載した計算環境への既存プログラムの移植方法として，CUDA・OpenCL に代表される Low-level なプログラミングモデルを用いる方法に対し，ディレクティブベースの OpenACC のような High-level なプログラミングモデルを用いる方法が考えられる．このようなディレクティブベースのプログラミングモデルの利点として，元のプログラムを壊さずに移植を行えるために，デバイス間の可搬性が高いことがあげられる．しかし現状の OpenACC などのプログラミングモデルは，スカラプロセッサとメニーコアアクセラレータの得意とするデータレイアウトの相違等に対応することが出来ず，異なる性質を持ったデバイス間の性能可搬性に問題がある．そこで本研究では，データレイアウトを抽象化し，異なるデバイス間での性能可搬性を向上させるための OpenACC の拡張ディレクティブを試作し，評価を行った．

CiNii Books

Language：Japanese  

Language：Japanese  

地震や気象予測，航空機や高層ビル設計といったシミュレーションに利用される数値流体力学アプリケーションは，近年一般的になりつつある GPU を用いたスーパーコンピュータにおいて，目覚ましい成果を上げている．しかし，GPU を用いたプログラミングは，高い性能を得ること難しいと言われており，レガシープログラムの GPU 環境への移植が問題となっている．本稿では，実際に利用されている大規模流体アプリケーションである UPACS を手動により CUDA 化し，性能と移植コストの面から評価を行った．また，プログラムの移植性を解決すると期待されている，OpenACC の予備評価を行った．これら評価の結果を示し，今後解決すべき課題について述べる．Computational fluid dynamics (CFD) applications used for an earthquake and meteorological simulation are one of the most important application executed with high-speed supercomputers. Especially, GPU-based supercomputers have been showing remarkable performance of CFD applications. However, GPU-programing is still difficult to obtain high performance, which prevents legacy applications from being ported to GPU environment. We apply classical optimizations to a real-world CFD application UPACS and evaluate it&#039;s performance and porting costs, and we also evaluate OpenACC expected to provide portability across CPUs and GPUs. We demonstrate these results of evaluation and mention performance problems should be resolved in the future.

CiNii Books

Language：Japanese  

Language：English   Publisher：一般社団法人映像情報メディア学会  

DOI： 10.3169/itej.66.817

Scopus

CiNii Books