Updated on 2023/09/29

写真a

 
HOSHINO Tetsuya
 
Organization
Information Technology Center High Performance Computing division Associate professor
Graduate School
Graduate School of Informatics
Title
Associate professor

Research Areas 1

  1. Informatics / High performance computing

Research History 1

  1. The University of Tokyo   Information Technology Center   Assistant Professor

    2016.1 - 2022.12

 

Papers 16

  1. Implementation of Radio Wave Propagation using RT Cores and Consideration of Programming Models

    Hashinoki S., Ohshima S., Katagiri T., Nagai T., Hoshino T.

    2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023     page: 673 - 681   2023

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    Publisher:2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023  

    With the NVIDIA Turing architecture generation, several NVIDIA graphics processing units (GPUs) have introduced ray tracing acceleration hardware (RT cores). Ray tracing processing can be regarded as a simulation of wave and particle propagation, collision, and reflection. Therefore, it is expected to be applied to computational science and high-performance computing. However, few studies have been conducted using RT cores. The purpose of this research is to demonstrate the use of RT cores in the scientific and technical computing fields. We implemented a radio wave propagation loss calculation with the programmable ray tracing application framework OptiX and evaluated its performance. Furthermore, we investigated the challenges of reducing the description of framework-specific settings and the needs of hardware allocation. In the simple two spheres experiment, the RT core implementation showed the highest performance. Moreover, the acceleration was super linear scaling, between (10000, 5000) and (20000, 10000). In the experiment with a sphere and planes, the performance achieved by the RT cores was up to approximately 390 times higher than the parallel execution of the BVH search algorithm. We also proved that a large number of RT cores yielded higher performance. In the open data problem space experiment, we evaluated various GPUs and revealed that a larger number of RT cores is effective. These results show that RT cores are sufficiently effective for radio propagation calculations with an adequate number of ray projections. Through this research, we contributed to the RT core use in computational science by proposing an implementation method for ray tracing applications and revealing the effects of RT cores in radio wave propagation loss calculations.

    DOI: 10.1109/IPDPSW59300.2023.00115

    Scopus

  2. Large-scale earthquake sequence simulations on 3D nonplanar faults using the boundary element method accelerated by lattice H-matrices

    So Ozawa, Akihiro Ida, Tetsuya Hoshino, Ryosuke Ando

    Geophysical Journal International     2022.10

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    Publishing type:Research paper (scientific journal)   Publisher:Oxford University Press (OUP)  

    Summary

    Large-scale earthquake sequence simulations using the boundary element method (BEM) incur extreme computational costs through multiplying a dense matrix with a slip rate vector. Hierarchical matrices (H-matrices) have often been used to accelerate this multiplication. However, the complexity of the structures of the H-matrices and the communication costs between processors limit their scalability, and they therefore cannot be used efficiently in distributed memory computer systems. Lattice H-matrices have recently been proposed as a tool to improve the parallel scalability of H-matrices. In this study, we developed a method for earthquake sequence simulations applicable to 3D nonplanar faults with lattice H-matrices. We present a simulation example and verify the mesh convergence of our method for a 3D nonplanar thrust fault using rectangular and triangular discretizations. We also performed performance and scalability analyses of our code. Our simulations, using over ${10^5}$ degrees of freedom, demonstrated a parallel acceleration beyond ${10^4}$ MPI processors and a > 10-fold acceleration over the best performance when the normal H-matrices are used. Using this code, we can perform unprecedented large-scale earthquake sequence simulations on geometrically complex faults with supercomputers. The software is made an open-source and freely available.

    DOI: 10.1093/gji/ggac386

  3. Optimizations of H-matrix-vector Multiplication for Modern Multi-core Processors.

    Tetsuya Hoshino, Akihiro Ida, Toshihiro Hanawa

    CLUSTER     page: 462 - 472   2022

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/CLUSTER51413.2022.00056

    Other Link: https://dblp.uni-trier.de/db/conf/cluster/cluster2022.html#HoshinoIH22

  4. Fortran標準規格do concurrentを用いたGPUオフローディング手法の評価

    星野 哲也, 塙 敏博

    情報処理学会研究報告(Web)   Vol. 2022-HPC-183   page: 1 - 8   2022

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  5. A64FXにおける階層型行列演算の性能評価

    星野 哲也, 伊田 明弘, 塙 敏博

    情報処理学会研究報告(Web)   Vol. 2021-HPC-180   page: 1 - 8   2021

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  6. Large-scale earthquake sequence simulations of 3D geometrically complex faults using the boundary element method accelerated by lattice H-matrices on distributed memory computer systems

    伊田 明弘, 星野 哲也

    arXiv preprint   Vol. -   page: 1 - 26   2021

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  7. Preliminary development of training environment for deep learning on supercomputer system Reviewed

    Y. Nomura, I. Sato, T. Hanawa, S. Hanaoka, T. Nakao, T. Takenaga, D. Sato, T. Hoshino, Y. Sekiya, S. Ohshima, N. Hayashi, O. Abe

    International Journal of Computer Assisted Radiology and Surgery   Vol. 13 ( Issue 1 supplement ) page: S105 - S106   2018.6

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    Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1007/s11548-018-1766-y

  8. Optimization of generation process for sparse coefficient matrices in FEM on multicore/manycore architectures

    中島研吾, 中島研吾, 星野哲也, 星野哲也, 成瀬彰, 塙敏博, 三木洋平

    情報処理学会研究報告(Web)   Vol. 2018 ( HPC-163 ) page: Vol.2018‐HPC‐163,No.28,1‐8 (WEB ONLY)   2018.2

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    Language:Japanese  

    J-GLOBAL

  9. Load-Balancing-Aware Parallel Algorithms of H-Matrices with Adaptive Cross Approximation for GPUs. Reviewed

    Tetsuya Hoshino, Akihiro Ida, Toshihiro Hanawa, Kengo Nakajima

    IEEE International Conference on Cluster Computing, CLUSTER 2018, Belfast, UK, September 10-13, 2018     page: 35 - 45   2018

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    Publishing type:Research paper (international conference proceedings)   Publisher:IEEE Computer Society  

    DOI: 10.1109/CLUSTER.2018.00016

  10. Design of parallel BEM analyses framework for SIMD processors Reviewed

    Tetsuya Hoshino, Akihiro Ida, Toshihiro Hanawa, Kengo Nakajima

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)   Vol. 10860   page: 601 - 613   2018

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Springer Verlag  

    Parallel Boundary Element Method (BEM) analyses are typically conducted using a purpose-built software framework called BEM-BB. This framework requires a user-defined function program that calculates the i-th row and the j-th column of the coefficient matrix arising from the convolution integral term in the fundamental BEM equation. Owing to this feature, the framework can encapsulate MPI and OpenMP hybrid parallelization with H-matrix approximation. Therefore, users can focus on implementing a fundamental solution or a Green’s function, which is the most important element in BEM and depends on the targeted physical phenomenon, as a user-defined function. However, the framework does not consider single instruction multiple data (SIMD) vectorization, which is important for high-performance computing and is supported by the majority of existing processors. Performing SIMD vectorization of a user-defined function is difficult because SIMD exploits instruction-level parallelization and is closely associated with the user-defined function. In this paper, a conceptual framework for enhancing SIMD vectorization is proposed. The proposed framework is evaluated using two BEM problems, namely, static electric field analysis with a perfect conductor and static electric field analysis with a dielectric, on Intel Broadwell (BDW) processor and Intel Xeon Phi Knights Landing (KNL) processor. It offers good vectorization performance with limited SIMD knowledge, as can be verified from the numerical results obtained herein. Specifically, in perfect conductor analyses conducted using the H-matrix, the framework achieved performance improvements of 2.22x and 4.34x compared to the original BEM-BB framework for the BDW processor and KNL, respectively.

    DOI: 10.1007/978-3-319-93698-7_46

    Scopus

  11. スーパーコンピュータ上でのDeep Learning学習環境の初期構築

    野村行弘, 佐藤一誠, 佐藤一誠, 佐藤一誠, 塙敏博, 花岡昇平, 中尾貴祐, 竹永智美, 佐藤大介, 星野哲也, 関谷勇司, 大島聡史, 林直人, 阿部修

    電子情報通信学会技術研究報告   Vol. 117 ( 281(MI2017 47-62) ) page: 1‐2   2017.10

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    Language:Japanese  

    J-GLOBAL

  12. Pascal vs KNL: Performance Evaluation with ICCG Solve Reviewed

    Tetsuya Hoshino, Satoshi Ohshima, Toshihiro Hanawa, Kengo Nakaima, Akihiro Ida

    HPC in Asia Workshop Poster Session, ISC High Performance 2017     2017.6

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    Language:English   Publishing type:Research paper (international conference proceedings)  

  13. OpenACCを用いたICCG法ソルバーのPascal GPUにおける性能評価

    星野哲也, 大島聡史, 塙敏博, 中島研吾, 伊田明宏

    情報処理学会研究報告(Web)   Vol. 2017 ( HPC-158 ) page: Vol.2017‐HPC‐158,No.18,1‐9 (WEB ONLY)   2017.3

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    J-GLOBAL

  14. A Directive-based Data Layout Abstraction for Performance Portability of OpenACC Applications Reviewed

    Tetsuya Hoshino, Naoya Maruyama, Satoshi Matsuoka

    PROCEEDINGS OF 2016 IEEE 18TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS; IEEE 14TH INTERNATIONAL CONFERENCE ON SMART CITY; IEEE 2ND INTERNATIONAL CONFERENCE ON DATA SCIENCE AND SYSTEMS (HPCC/SMARTCITY/DSS)     page: 1147 - 1154   2016

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    Directive-based programming interfaces such as OpenACC and OpenMP are becoming more prevalent in application development targeting accelerators, in particular when porting existing CPU-only code. Unlike vendor-specific alternatives such as CUDA, they are designed to be portable across different accelerators, and therefore once necessary directives are added to an existing CPU-only code, it can be executed on different accelerator architectures depending on the availability of supporting compilers. However, it does not automatically mean that such code runs efficiently on different architectures, and in fact, architecture-specific coding such as choosing optimal data layouts is almost mandatory for optimal performance, imposing a significant burden if implemented manually. Towards realizing performance portability in accelerator programming, we propose a set of extended directives that allow the programmer to optimize data layouts for a given accelerator without modifying original program code. Unlike the manual approach, the code change is confined in the directives with the original code kept as it is. This paper evaluates the effectiveness of our proposed extensions in the OpenACC standard by extending UPACS and CCS-QCD OpenACC applications. A prototype source-to-source translator for the extensions achieves 123% and 120% of the baseline performance, respectively, which are comparable to manually tuned versions.

    DOI: 10.1109/HPCC-SmartCity-DSS.2016.34

    Web of Science

  15. An OpenACC extension for data layout transformation Reviewed

    Tetsuya Hoshino, Naoya Maruyama, Satoshi Matsuoka

    Proceedings of WACCPD 2014: 1st Workshop on Accelerator Programming Using Directives - Held in Conjunction with SC 2014: The International Conference for High Performance Computing, Networking, Storage and Analysis     page: 12 - 18   2015.4

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Institute of Electrical and Electronics Engineers Inc.  

    OpenACC is gaining momentum as an implicit and portable interface in porting legacy CPU-based applications to heterogeneous, highly parallel computational environment involving many-core accelerators such as GPUs and Intel Xeon Phi. OpenACC provides a set of loop directives similar to OpenMP for the parallelization and also to manage data movement, attaining functional portability across different heterogeneous devices
    however, the performance portability of OpenACC is said to be insufficient due to the characteristics of different target devices, especially those regarding memory layouts, as automated attempts by the compilers to adapt is currently difficult. We are currently working to propose a set of directives to allow compilers to have better semantic information for adaptation
    here, we particularly focus on data layout such as Structure of Arrays, advantageous data structure for GPUs, as opposed to Array of Structures, which exhibits good performance on CPUs. We propose a directive extension to OpenACC that allows the users to flexibility specify optimal layouts, even if the data structures are nested. Performance results show that we gain as much as 96 % in performance for CPUs and 165% for GPUs compared to programs without such directives, essentially attaining both functional and performance portability in OpenACC.

    DOI: 10.1109/WACCPD.2014.12

    Scopus

  16. CUDA vs OpenACC: Performance Case Studies with Kernel Benchmarks and a Memory-Bound CFD Application11 Reviewed

    Tetsuya Hoshino, Naoya Maruyama, Satoshi Matsuoka, Ryoji Takaki

    PROCEEDINGS OF THE 2013 13TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON CLUSTER, CLOUD AND GRID COMPUTING (CCGRID 2013)     page: 136 - 143   2013

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    OpenACC is a new accelerator programming interface that provides a set of OpenMP-like loop directives for the programming of accelerators in an implicit and portable way. It allows the programmer to express the offloading of data and computations to accelerators, such that the porting process for legacy CPU-based applications can be significantly simplified. This paper focuses on the performance aspects of OpenACC using two microbenchmarks and one real-world computational fluid dynamics application. Both evaluations show that in general OpenACC performance is approximately 50% lower than CUDA. However, for some applications it can reach up to 98% with careful manual optimizations. The results also indicate several limitations of the OpenACC specification that hamper full use of the GPU hardware resources, resulting in a significant performance gap when compared to a highly tuned CUDA code. The lack of a programming interface for the shared memory in particular results in as much as three times lower performance.

    DOI: 10.1109/CCGrid.2013.12

    Web of Science

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MISC 22

  1. A64FXにおけるテンポラルブロッキングの実装と性能評価

    星野 哲也, 塙 敏博

    研究報告ハイパフォーマンスコンピューティング(HPC)   Vol. 2021-HPC-178 ( 17 ) page: 1 - 8   2021.3

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    Authorship:Lead author  

  2. 「計算・データ・学習」融合スーパーコンピュータシステム「Wisteria/BDEC-01」の概要

    中島研吾, 塙敏博, 下川辺隆史, 伊田明弘, 芝隼人, 三木洋平, 星野哲也, 有間英志, 河合直聡, 坂本龍一, 近藤正章, 岩下武史, 八代尚, 長尾大道, 松葉浩也, 荻田武史, 片桐孝洋, 古村孝志, 鶴岡弘, 市村強, 藤田航平

    情報処理学会研究報告(Web)   Vol. 2021 ( HPC-179 )   2021

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  3. 「計算・データ・学習」融合スーパーコンピュータシステムWisteria/BDEC-01の性能評価

    塙敏博, 中島研吾, 中島研吾, 下川辺隆史, 芝隼人, 三木洋平, 星野哲也, 河合直聡, 似鳥啓吾, 今村俊幸, 工藤周平, 中尾昌広

    情報処理学会研究報告(Web)   Vol. 2021 ( HPC-180 )   2021

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  4. A64FXにおける階層型行列演算の性能評価

    星野哲也, 伊田明弘, 伊田明弘, 塙敏博

    情報処理学会研究報告(Web)   Vol. 2021 ( HPC-180 )   2021

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  5. An Optimization of H-matrix-vector Multiplication by Using Un-used Cores

    Tetsuya Hoshino, Toshihiro Hanawa, Akihiro Ida

    HPC Asia 2020     2020.1

  6. Numerical Linear Algebra Based on Lattice H-Matrices

    Akihiro Ida, Ichitaro Yamazaki, Rio Yokota, Satoshi Ohshima, Tasuku Hiraishi, Takeshi Iwashita, Tetsuya Hoshino, Toshihiro Hanawa

    HPC Asia 2020     2020.1

  7. メニーコアクラスタにおける階層型行列法の高速化に向けた性能評価

    星野哲也, 伊田明弘

    計算工学講演会論文集(CD-ROM)   Vol. 24   page: ROMBUNNO.C‐07‐02   2019.6

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    Language:Japanese  

    J-GLOBAL

  8. High-level Abstractions for High Performance Computing on Many-core Processors

    Hoshino Tetsuya

        2018.9

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  9. OpenCLを用いたFPGAによる階層型行列計算

    塙敏博, 伊田明弘, 星野哲也

    情報処理学会研究報告(Web)   Vol. 2018 ( HPC-163 ) page: Vol.2018‐HPC‐163,No.26,1‐8 (WEB ONLY)   2018.2

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    J-GLOBAL

  10. 階層型行列計算のFPGAへの適用

    塙敏博, 伊田明弘, 星野哲也

    情報処理学会研究報告(Web)   Vol. 2017 ( HPC-161 ) page: Vol.2017‐HPC‐161,No.10,1‐10 (WEB ONLY)   2017.9

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    J-GLOBAL

  11. 階層型行列法ライブラリHACApKを用いたアプリケーションのメニーコア向け最適化

    星野哲也, 伊田明弘, 塙敏博, 中島研吾

    情報処理学会研究報告(Web)   Vol. 2017 ( HPC-160 ) page: Vol.2017‐HPC‐160,No.15,1‐10 (WEB ONLY)   2017.7

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    J-GLOBAL

  12. GPU搭載スーパーコンピュータReedbush‐Hの性能評価

    塙敏博, 星野哲也, 中島研吾, 大島聡史, 伊田明弘

    情報処理学会研究報告(Web)   Vol. 2017 ( HPC-159 ) page: Vol.2017‐HPC‐159,No.9,1‐6 (WEB ONLY)   2017.4

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    J-GLOBAL

  13. Xeon Phi+OmniPath環境におけるOpenMP,MPI性能最適化

    塙敏博, 星野哲也, 中島研吾, 大島聡史, 伊田明弘

    情報処理学会研究報告(Web)   Vol. 2017 ( HPC-158 ) page: Vol.2017‐HPC‐158,No.21,1‐8 (WEB ONLY)   2017.3

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    J-GLOBAL

  14. Optimization of ICCG Solver for Intel Xeon Phi

    中島研吾, 中島研吾, 大島聡史, 大島聡史, 塙敏博, 星野哲也, 伊田明弘, 伊田明弘

    情報処理学会研究報告(Web)   Vol. 2016 ( HPC-157 ) page: Vol.2016‐HPC‐157,No.16,1‐8 (WEB ONLY)   2016.12

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    J-GLOBAL

  15. Performance Evaluation of Pipelined CG Method

    塙敏博, 中島研吾, 中島研吾, 大島聡史, 大島聡史, 星野哲也, 伊田明弘, 伊田明弘

    情報処理学会研究報告(Web)   Vol. 2016 ( HPC-157 ) page: Vol.2016‐HPC‐157,No.6,1‐9 (WEB ONLY)   2016.12

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    Language:Japanese  

    J-GLOBAL

  16. データ解析・シミュレーション融合スーパーコンピュータシステムReedbush‐Uの性能評価

    塙敏博, 中島研吾, 大島聡史, 伊田明弘, 星野哲也, 田浦健次朗

    情報処理学会研究報告(Web)   Vol. 2016 ( HPC-156 ) page: Vol.2016‐HPC‐156,No.10,1‐10 (WEB ONLY)   2016.9

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    J-GLOBAL

  17. OpenACCディレクティブ拡張によるデータレイアウト最適化

    星野哲也, 丸山直也, 松岡聡

    研究報告ハイパフォーマンスコンピューティング(HPC)   Vol. 2014 ( 45 ) page: 1 - 8   2014.7

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    Language:Japanese   Publisher:一般社団法人情報処理学会  

    近年増加傾向にある GPU 等のアクセラレータを搭載した計算環境への既存プログラムの移植方法として,CUDA・OpenCL に代表されるローレベルなプログラミングモデルを用いる方法に対し,ディレクティブベースの OpenACC のようなハイレベルなプログラミングモデルを用いる方法が注目されている.このようなディレクティブベースのプログラミングモデルの利点として,元のプログラムを維持したまま移植を行えるために,デバイス間の機能的な可搬性が高いことがあげられる.しかし現状の OpenACC などの High-level なプログラミングモデルは,スカラプロセッサとメニーコアアクセラレータの得意とするデータレイアウトの相違に対応することが出来ず,異なる性質を持ったデバイス間の性能可搬性に問題がある.そこで本研究では,データレイアウトを抽象化し,異なるデバイス間での性能可搬性を向上させるための OpenACC の拡張ディレクティブを試作し,姫野ベンチマークのデータレイアウトをトランスレーターにより変更し,マルチコア CPU,Intex Xeon Phi,K20X GPU のそれぞれで評価を行った.その結果,オリジナルと同一のデータレイアウトと比較して,Intel Xeon Phi では 27%,K20X GPU では 24%の性能向上が得られることを確認した.

    CiNii Books

  18. CPU-GPUそれぞれに最適なデータレイアウトを選択可能にするOpenACCディレクティブ拡張

    星野哲也, 丸山直也, 松岡聡

    研究報告ハイパフォーマンスコンピューティング(HPC)   Vol. 2014 ( 5 ) page: 1 - 5   2014.2

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    Language:Japanese   Publisher:一般社団法人情報処理学会  

    近年増加傾向にある GPU 等のアクセラレータを搭載した計算環境への既存プログラムの移植方法として,CUDA・OpenCL に代表される Low-level なプログラミングモデルを用いる方法に対し,ディレクティブベースの OpenACC のような High-level なプログラミングモデルを用いる方法が考えられる.このようなディレクティブベースのプログラミングモデルの利点として,元のプログラムを壊さずに移植を行えるために,デバイス間の可搬性が高いことがあげられる.しかし現状の OpenACC などのプログラミングモデルは,スカラプロセッサとメニーコアアクセラレータの得意とするデータレイアウトの相違等に対応することが出来ず,異なる性質を持ったデバイス間の性能可搬性に問題がある.そこで本研究では,データレイアウトを抽象化し,異なるデバイス間での性能可搬性を向上させるための OpenACC の拡張ディレクティブを試作し,評価を行った.

    CiNii Books

  19. ディレクティブベースプログラミング言語OpenACCの性能評価

    星野哲也, 丸山直也, 松岡聡

    ハイパフォーマンスコンピューティングと計算科学シンポジウム論文集   Vol. 2013   page: 91 - 91   2013.1

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  20. Evaluation of Portability for a Real-world CFD Application with CUDA and OpenACC

    星野 哲也, 丸山 直也, 松岡 聡

    研究報告ハイパフォーマンスコンピューティング(HPC)   Vol. 2012 ( 42 ) page: 1 - 9   2012.7

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    Language:Japanese  

    地震や気象予測,航空機や高層ビル設計といったシミュレーションに利用される数値流体力学アプリケーションは,近年一般的になりつつある GPU を用いたスーパーコンピュータにおいて,目覚ましい成果を上げている.しかし,GPU を用いたプログラミングは,高い性能を得ること難しいと言われており,レガシープログラムの GPU 環境への移植が問題となっている.本稿では,実際に利用されている大規模流体アプリケーションである UPACS を手動により CUDA 化し,性能と移植コストの面から評価を行った.また,プログラムの移植性を解決すると期待されている,OpenACC の予備評価を行った.これら評価の結果を示し,今後解決すべき課題について述べる.Computational fluid dynamics (CFD) applications used for an earthquake and meteorological simulation are one of the most important application executed with high-speed supercomputers. Especially, GPU-based supercomputers have been showing remarkable performance of CFD applications. However, GPU-programing is still difficult to obtain high performance, which prevents legacy applications from being ported to GPU environment. We apply classical optimizations to a real-world CFD application UPACS and evaluate it's performance and porting costs, and we also evaluate OpenACC expected to provide portability across CPUs and GPUs. We demonstrate these results of evaluation and mention performance problems should be resolved in the future.

    CiNii Books

  21. 大規模流体アプリケーションのGPUによる高速化手法の評価

    星野哲也, 丸山直也, 松岡聡

    先進的計算基盤システムシンポジウム論文集   Vol. 2012   page: 73 - 74   2012.5

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    Language:Japanese  

  22. “Open ACC Programming”

    Naoya Maruyama, Tetsuya Hoshino

    Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers   Vol. 66 ( 10 ) page: 817 - 822   2012

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    Language:English   Publisher:一般社団法人映像情報メディア学会  

    DOI: 10.3169/itej.66.817

    Scopus

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KAKENHI (Grants-in-Aid for Scientific Research) 1

  1. Construction of numerical linear algebra based on lattice H-matrices and its high-performance implementation on modern architectures

    Grant number:21H03447  2021.4 - 2024.3

    Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (B)

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    Authorship:Coinvestigator(s)