2022/06/08 更新

写真a

ウシダ ヤスヒサ
牛田 泰久
USHIDA Yasuhisa
所属
未来材料・システム研究所 豊田合成GaN先端デバイス応用産学協同研究部門 特任准教授
職名
特任准教授
連絡先
メールアドレス
外部リンク

学位 1

  1. 博士(理学) ( 2001年3月   名古屋大学 ) 

 

論文 2

  1. <p>The effect of dry etching condition on the performance of blue micro light-emitting diodes with reduced quantum confined Stark effect epitaxial layer</p>

    Park Jeong-Hwan, Cai Wentao, Cheong Heajeong, Ushida Yasuhisa, Lee Da-Hoon, Ando Yuto, Furusawa Yuta, Honda Yoshio, Lee Dong-Seon, Seong Tae-Yeon, Amano Hiroshi

    JOURNAL OF APPLIED PHYSICS   131 巻 ( 15 )   2022年4月

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    記述言語:日本語   出版者・発行元:Journal of Applied Physics  

    As the size of micro light-emitting diodes (μLEDs) decreases, μLEDs encounter etching damage especially at the sidewalls that critically affects their properties. In this study, we investigated the influence of etching bias power (Pbias) on the performance of μLEDs and found that the current-voltage and light output-current characteristics of μLEDs were enhanced when Pbias was reduced. It was shown that at low Pbias, the chemical reaction between etching gas and gallium nitride, rather than ion sputtering, dominated the etching process, leading to low plasma damage and rough surface morphology. Additionally, to understand the etching-induced surface roughening behaviors, various substrates with different threading dislocation densities were treated at low Pbias. It was found that for the sample (with p-contact size of 10 × 10 μm2), the efficiency droop was approximately 20%, although the current reached 10 mA due most probably to the suppressed polarization effect in the quantum well. It was further observed that the external quantum efficiency (EQE) was dependent on Pbias, where the lowest Pbias yielded the highest maximum EQE, indicating that the plasma damage was mitigated by reducing Pbias. Optimization of dry etching and polarization-suppression conditions could pave the way for realizing high-performance and brightness μLEDs for next-generation displays.

    DOI: 10.1063/5.0085384

    Web of Science

    Scopus

  2. Frequency Doubler Gate Drive Circuit Suitable for High-Frequency Applications

    Hattori Fumiya, Ushida Yasuhisa, Sumiya Kengo, Yanagisawa Yuta, Imaoka Jun, Noah Mostafa, Yamamoto Masayoshi

    IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS   10 巻 ( 1 ) 頁: 617 - 631   2022年2月

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    記述言語:日本語   出版者・発行元:IEEE Journal of Emerging and Selected Topics in Power Electronics  

    In megahertz (MHz) power converters, the gate drive loss becomes one of the main issues that should be addressed. In the relevant literature, several gate drive circuits had been proposed to reduce the gate drive losses. A literature survey is provided in the introduction section to summarize the merits and demerits of each circuit. These studies proposed innovative methods to reduce gate drive loss. Nonetheless, they did not propose any solution to reduce the loss of the buffer stage inside the drive IC. In this article, we present a frequency doubler gate drive circuit. The proposed gate drive circuit can double the frequency of the input PWM signal at the driver output stage, using the second harmonic of the input signal. Therefore, the loss of the buffer stage inside the drive IC can be significantly reduced, compared with the hard-switching, the inductive resonant, and multiresonant gate drive circuits. This article focuses on designing, simulating, and experimentally validating the frequency doubler gate drive circuit with a 6.78-MHz input frequency and 13.56-MHz driving frequency. The concept of a frequency tripler gate drive circuit is also introduced and discussed. For instance, the frequency tripler gate drive circuit can triple the frequency of the input PWM signal at the driver output stage using the third harmonic; in this scenario, a 20.34-MHz driving frequency can be obtained. The proposed frequency doubler gate drive circuit is experimentally tested in a 13.56-MHz class E inverter.

    DOI: 10.1109/JESTPE.2021.3089506

    Web of Science

    Scopus