研究者詳細 - 田中　雅光

論文 - 田中　雅光

分割表示 >> ／全件表示 65 件中 1 - 65 件目

Demonstration of low-power shift-register based on half-flux-quantum logic 招待有り査読有り

Masamitsu Tanaka, Toranosuke Nakayama, Shoma Tanemura, Masayuki Higashi, Feng Li, Akira Fujimaki

IEICE Transactions on Electronics E108-C 巻 ( 6 ) 2025年6月

Ferromagnetic π junctions on niobium four-layer structure for superconductor large-scale integrated circuits 査読有り

Akira Fujimaki, Daiki Hasegawa, Yuto Takeshita, Feng Li Taro Yamashita, Masamitsu Tanaka

IEICE Transactions on Electronics E108-C 巻 ( 6 ) 2025年6月

Low-power single-flux-quantum standard cell library using 250 A/cm² process for qubit control applications 査読有り

Masamitsu Tanaka, Yoshihiro Kitagawa, Tetsuro Satoh, Tsuyoshi Yamamoto

35 巻 ( 5 ) 頁： 1700405 2024年12月

C3-VQA: Cryogenic Counter-Based Co-Processor for Variational Quantum Algorithms 査読有り

Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

IEEE Transactions on Quantum Engineering 6 巻頁： 3100317 2024年12月

Intrinsic superconducting phase battery 査読有り

Feng Li, Masayuki Higashi, Taichi Sato, Masamitsu Tanaka, Akira Fujimaki

Applied Physics Letters 124 巻 ( 22 ) 頁： 222601 2024年5月

Investigation of timing margin in single-flux-quantum 4 bit adders for increasing clock frequency of gate-level-pipelined circuits 査読有り

Ikki Nagaoka1, Tomoki Nakano, Ryota Kashima, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

Applied Physics Express 17 巻 ( 5 ) 頁： 054501 2024年5月

NbN-based tunnel-type π-junctions for low-power half-flux-quantum circuits 査読有り

Duong Pham, Feng Li, Kenjiro Oba, Yuto Takeshita, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

Superconductor Science and Technology 37 巻 ( 5 ) 頁： 055004 2024年5月

Flux transfer circuits breaking conventional limit in transfer coefficient based on a negative inductance of a π-junction 査読有り

Masayuki Higashi, Feng Li, Masamitsu Tanaka and Akira Fujimaki

Superconductor Science and Technology 37 巻 ( 4 ) 頁： 045003 2024年4月

Inter-temperature bandwidth reduction in cryogenic QAOA machines 査読有り

Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, and Hiroshi Nakamura

IEEE Computer Architecture Letters 23 巻 ( 1 ) 頁： 9 - 12 2023年10月

Energy efficient half-flux-quantum circuit aiming at milli-kelvin stage operation 査読有り国際誌

F. Li, D. Pham, Y. Takeshita, M. Higashi, T. Yamashita, M. Tanaka, and A. Fujimaki

Superconductor Science and Technology 36 巻 ( 10 ) 頁： 105006 2023年10月

High-frequency operation of low-power single-flux-quantum circuits fabricated using 250 A/cm² Nb/AlOx/Nb planarization process 査読有り

Masamitsu Tanaka, Yoshihiro Kitagawa, Tetsuro Satoh, and Tsuyoshi Yamamoto

2023 International Conference on IC Design and Technology (ICICDT) 頁： 84 - 87 2023年9月

Analysis of the effect of 0-π SQUIDs for enhancing mutual coupling 査読有り国際誌

Masayuki Higashi, Yuto Takeshita, Kento Kato, Hinata Fujisawa, Feng Li, Masamitsu Tanaka, Taro Yamashita, and Akira Fujimaki

IEEE Transactions on Applied Superconductivity 33 巻 ( 5 ) 頁： 1600805 2023年8月

Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File 招待有り査読有り国際誌

Ryota Kashima, Ikki Nagaoka, Tomoki Nakano, Masamitsu Tanaka, Taro Yamashita, and Akira Fujimaki

IEEE Transactions on Applied Superconductivity 33 巻 ( 5 ) 頁： 1303306 2023年8月

Fabrication process for monolithic integration of a nitride superconductor-based superconducting qubit with a single flux quantum control circuit 査読有り国際誌

Shigeyuki Miyajima, Taro Yamashita, Masamitsu Tanaka, Naoki Takeuchi, Kunihiro Inomata, and Hirotaka Terai

IEEE Transactions on Applied Superconductivity 33 巻 ( 5 ) 頁： 1100204 2023年8月

Design and fabrication of low-power single-flux-quantum circuits toward quantum bit control 査読有り国際誌

Masamitsu Tanaka, Yoshihiro Kitagawa, Tetsuro Satoh, and Tsuyoshi Yamamoto

IEEE Transactions on Applied Superconductivity 33 巻 ( 5 ) 頁： 1700805 2023年8月

Optimization of half-flux-quantum circuits composed of π-shift and conventional Josephson junctions 査読有り国際誌

S. Tanemura, Y. Takeshita, F. Li, T. Nakayama, M. Tanaka, and A. Fujimaki

IEEE Transactions on Applied Superconductivity 33 巻 ( 5 ) 頁： 1701305 2023年8月

QIsim: Architecting 10+ K qubit QC interfaces toward quantum supremacy 査読有り国際共著

D. Min, J. Kim, J. Choi, I. Byun, M. Tanaka, K. Inoue, and J. Kim

Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA '23) 頁： 1 - 16 2023年6月

Circuit designs for practical-scale fault-tolerant quantum computing 招待有り査読有り

Y. Suzuki, Y. Ueno, W. Liao, M. Tanaka, and T. Tanimoto

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 頁： 1 - 2 2023年6月

50-GFLOPS floating-point adder and multiplier using gate-level-pipelined single-flux-quantum logic with frequency-increased clock distribution 査読有り国際誌

Ikki Nagaoka, Ryota Kashima, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Taro Yamashita, Koji Inoue, and Akira Fujimaki

IEEE Transactions on Applied Superconductivity 33 巻 ( 4 ) 頁： 1302711 2023年6月

Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency 査読有り国際誌

M. Tanaka, R. Sato, A. Fujimaki, K. Takagi, and N. Takagi

Applied Physics Letters 122 巻 ( 19 ) 頁： 192601 2023年5月

Superconductor digital circuits with π junctions alone 査読有り国際誌

F. Li, Y. Takeshita, M. Tanaka, and A. Fujimaki

Applied Physics Letters 122 巻 ( 16 ) 頁： 162601 2023年4月

Direct observations of π-leaps of superconducting phase differences in π-junction-based SQUIDs 査読有り国際誌

Yuto Takeshita, Feng Li, Masayuki Higashi, Masamitsu Tanaka, Taro Yamashita, and Akira Fujimaki

Superconductor Science and Technology 36 巻 ( 4 ) 頁： 045004 2023年4月

A high-throughput multiply-accumulate unit with long feedback loop using low-voltage rapid single-flux quantum circuits 査読有り国際誌

Ikki Nagaoka, Ryota Kashima, Koki Ishida, Masamitsu Tanaka, Taro Yamashita, Takatsugu Ono, Koji Inoue, and Akira Fujimaki

IEEE Transactions on Applied Superconductivity 33 巻 ( 3 ) 頁： 1301808 2023年4月

単一磁束量子回路のインタラクティブ可視化: 宇宙機での利用が期待されるデバイスに係る事例査読有り

三浦昭, 松崎恵一, 石田貴行 , 田中雅光, 井上弘士

宇宙航空研究開発機構研究開発報告: 宇宙科学情報解析論文誌 12 巻頁： 31 - 40 2023年2月

A 57.2GHz 11.2mW 8-bit General Purpose Superconductor Microprocessor with Dual-Clocking Scheme 査読有り国際誌

Ikki Nagaoka, Ryota Kashima, Tomoki Nakano, Masamitsu Tanaka, Taro Yamashita, Koji Inoue, and Akira Fujimaki

IEEE Asian Solid Circuits Conference (A-SSCC 2022) 2022年11月

XQsim: modeling cross-technology control processors for 10+K qubit quantum computers 査読有り国際共著国際誌

Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, and Jangwoo Kim

49th Annual International Symposium on Computer Architecture (ISCA '22) 頁： 366 - 382 2022年6月

量子コンピュータ超伝導周辺回路の現状と課題査読有り

田中雅光, 山梨裕希

電気学会論文誌Ａ（基礎・材料・共通部門誌） 142 巻 ( 5 ) 2022年5月

Weak spin-flip scattering in Pd89Ni11 interlayer of NbN-based ferromagnetic Josephson junctions 査読有り国際誌

Duong Pham, Riku Sugimoto, Kenjiro Oba, Yuto Takeshita, Feng Li, Masamitsu Tanaka, Taro Yamashita, and Akira Fujimaki

Scientific Reports 12 巻 ( 1 ) 頁： 6863 2022年4月

QULATIS: A quantum error correction methodology toward lattice surgery 査読有り国際誌

Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, and Yutaka Tabuchi

28th IEEE International Symposium on High-Performance Computer Architecture (HPCA-28) 頁： 274 - 287 2022年4月

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code 査読有り

Y. Ueno, M. Kondo, M. Tanaka, Y. Suzuki, and Y. Tabuchi

2021 58th ACM/IEEE Design Automation Conference (DAC) 頁： 451 - 456 2021年12月

Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation 査読有り国際誌

Shuichi Nagasawa, Masamitsu Tanaka, Naoki Takeuchi, Yuki Yamanashi, Shigeyuki Miyajima, Fumihiro China, Taiki Yamae, Koki Yamazaki, Yuta Somei, Naonori Sega, Yoshinao Mizugaki, Hiroaki Myoren, Hirotaka Terai, Mutsuo Hidaka, Nobuyuki Yoshikawa, Akira Fujimaki

IEICE Transactions on Electronics E104-C 巻 ( 9 ) 頁： 435 - 445 2021年9月

担当区分：責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

DOI： 10.1587/transele.2020SUP0001

Investigation of Timing Parameters in Single-Flux-Quantum Circuits Using Low Critical-Current Junctions and Low Bias Voltages 招待有り査読有り国際誌

M. Kuniyoshi, K. Murase, I. Nagaoka, K. Sano, M. Tanaka, T. Yamashita, and A. Fujimaki

IEEE Transactions on Applied Superconductivity 31 巻 ( 5 ) 頁： 1101405 2021年8月

Demonstration of a 52-GHz Bit-Parallel Multiplier Using Low-Voltage Rapid Single-Flux-Quantum Logic 招待有り査読有り国際誌

I. Nagaoka, K. Ishida, M. Tanaka, K. Sano, T. Yamashita, T. Ono, K. Inoue, and A. Fujimaki

IEEE Transactions on Applied Superconductivity 31 巻 ( 5 ) 頁： 1302505 2021年8月

High-Speed Memory Driven by SFQ Pulses Based on 0-π SQUID 査読有り国際誌

Yuto Takeshita, Feng Li, Daiki Hasegawa, Kyosuke Sano, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

IEEE Transactions on Applied Superconductivity 31 巻 ( 5 ) 頁： 1100906 2021年8月

記述言語：英語掲載種別：研究論文（学術雑誌）

We propose a new cryogenic high-speed and low-power matrix memory required for achieving a high-performance superconductor computing system. The memory cell is based on the 0-π SQUID with conventional Josephson junctions (0-junctions) and a π-shifted ferromagnetic Josephson junction (π-junction). The memory state is stored in the form of two stable states in the 0-π SQUID. The π shift feature of the π-junction eliminates the need for any bias current or magnetic field for the formation of two states, i.e., the memory is non-volatile. In this memory, an impulse-shaped voltage signal generated in single-flux-quantum (SFQ) circuits is used for the write and read operations of the memory state. By using the pulses propagating in passive transmission lines, high-speed and low-power operation can be achieved because a recharging process determining the operation speed and the dominant energy consumption can be eliminated. We fabricated the 0-π SQUID-based pulse-driven memory cells with an SFQ driver. From the static characteristics, we confirmed that the current needed for rewriting can be sufficiently reduced. In addition, we successfully demonstrated the correct write operation in the memory cell by the SFQ pulse train transmitted from the SFQ driver via the passive transmission line.

DOI： 10.1109/TASC.2021.3060351

64-GHz Datapath Demonstration for Bit-Parallel SFQ Microprocessors Based on a Gate-Level-Pipeline Structure 招待有り査読有り国際誌

Ryota Kashima, Ikki Nagaoka, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

IEEE Transactions on Applied Superconductivity 31 巻 ( 5 ) 頁： 1301006 2021年8月

記述言語：英語掲載種別：研究論文（学術雑誌）

We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic logic unit and register files for high-throughput oriented SFQ microprocessors based on a gate-level-pipeline structure. Achieving high-speed operation in the bit-parallel datapath is difficult because of feedback paths. We used concurrent-flow clocking and counter-flow clocking in combination to solve the timing problem at the feedback path in the datapath, and we optimized the number of JJs and pipeline stages in the register file for solving the timing issue. We designed the datapath with the cell library for the AIST 10 kA/cm 2 Advanced Process. The total number of pipeline stages, Josephson junctions, and circuit area of the designed datapath were 52, 18448, and 3.81 mm × 4.05 mm, respectively. We obtained a relatively wide bias margin of the designed datapath at the target clock frequency of 50 GHz, and it operated up to 64 GHz in on-chip high-speed testing.

DOI： 10.1109/TASC.2021.3061353

Synchronous SFQ address encoder for superconductor detector arrays 査読有り国際共著国際誌

Ali Bozbey, Eren Can Aydogan, Kubra Usenmez, Sasan Razmkhah, Masamitsu Tanaka, Akira Fujimaki

IEEE Transactions on Applied Superconductivity 2021年6月

記述言語：英語掲載種別：研究論文（学術雑誌）

With the advances in superconductor detectors and single flux quantum (SFQ) logic circuits, megapixel imagers have become possible. Various detectors such as superconducting stripline detectors (SSLD), kinetic inductance detectors (KID), nanowire single-photon detectors have quite matured in terms of speed and performance. However, scaling of the read-out electronics is still a challenge. We propose an SFQ based synchronous address encoder to read-out the response of an SSLD array. The encoder circuit provides two sets of outputs at each clock period: one is the time-division multiplexed, serial data output, and the other is the synchronized address output associated with the time-multiplexed data. So, the number of connections to the room temperature is substantially reduced. We experimentally demonstrate a 2-bit encoder. Then we present the scalability of the circuit to larger arrays and show the simulation results of a 4-bit encoder which is suitable to read-out a 16x16 detector array.

DOI： 10.1109/TASC.2021.3065000

超伝導プロセッサ・アーキテクチャ査読有り

井上弘士, 田中雅光, 石田浩貴

低温工学 56 巻 ( 2 ) 頁： 87 - 93 2021年3月

Low-power high-speed half-flux-quantum circuits driven by low bias voltages 査読有り国際誌

Feng Li, Yuto Takeshita, Daiki Hasegawa, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

Superconductor Science and Technology 34 巻 ( 2 ) 頁： 025013 2021年2月

記述言語：英語掲載種別：研究論文（学術雑誌）

Half-flux-quantum (HFQ) circuits store and propagate half-flux quanta. The basic circuit element is a 0-π SQUID, which is a superconducting quantum interference device with a conventional Josephson junction (0-junction) and a π-shifted ferromagnetic junction (π-junction). A 0-π SQUID achieves a small critical current in the absence of an external magnetic field, thus reducing power consumption. It is easy to set up 0-0-π SQUIDs with two 0-junctions and a π-junction which serves as a π phase-shifter. We simulated 0-0-π SQUID-based HFQ circuits driven by low bias voltages, referred to as LV-HFQ circuits. In these circuits, shunt resistors are not required for switching junctions because there is no hysteresis in the current–voltage characteristics of 0-0-π SQUIDs. We estimated the power consumption and maximum operating frequency of an HFQ Josephson transmission line based on 0-0-π SQUIDs. When operating at 43.5 GHz, the power dissipation of a single element composed of a 0-0-π SQUID and a bias resistor fell to about 0.165 nW when biased at 60 μV. The LV-HFQ circuit is potentially more power-efficient than all other currently available superconducting logic circuits.

DOI： 10.1088/1361-6668/abcaac

SFQ Parallel Encoders Promising for Video Imaging With Superconductor Stripline Detectors 査読有り国際共著国際誌

Masamitsu Tanaka, Misaki Kozaka, Kyohei Kamiya, Kübra Üsenmez, Eren Can Aydo ̆gan, Sasan Razmkhah, Ali Bozbey, Akira Fujimaki

IEEE Transactions on Applied Superconductivity 31 巻 ( 1 ) 頁： 1300106 2021年1月

担当区分：筆頭著者,　責任著者記述言語：英語掲載種別：研究論文（学術雑誌）

We report demonstration of a readout circuit with high-throughput single flux quantum (SFQ) based encoders for a large-scale video imaging system with a conventional frame rate. The encoders are fully parallel and integrated on the same chip as linear arrays of serially connected superconductor stripline detectors (SSLDs), superconducting quantum interference device (SQUID) based comparators, and SFQ synchronizers. Mutual coupling of parallel SSLDs and SQUID-based comparators allows the use of only one dc bias line; it is possible to use thousands of SSLDs without increasing the bias current or number of bias ports. To achieve crosstalk-free readout, the serially connected SSLDs are separated by low-pass filters or large inductors. We experimentally demonstrated crosstalk-free readout including SFQ parallel encoders from 1-D or 2-D serially connected SSLD arrays.

DOI： 10.1109/TASC.2020.3013385

Investigation of Timing Parameters in Single-Flux-Quantum Circuits Using Low Critical-Current Junctions and Low Bias Voltages 査読有り国際誌

Manami Kuniyoshi, Ken Murase, Ikki Nagaoka, Kyosuke Sano, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

IEEE Transactions on Applied Superconductivity 2021年

記述言語：英語掲載種別：研究論文（学術雑誌）

In this study, the trade-off among power consumptions, operating frequencies, and error rates in low-power single-flux-quantum (SFQ) circuit is investigated. The power consumption of SFQ circuits can be reduced by the lowering critical currents (Ic values) of the Josephson junctions (JJs), or the bias voltage (Vb). The shifts and spreads of timing parameter fluctuations when Ic and Vb were lowered were numerically analyzed, with consideration of thermal noise at 4.2 K. The timing behaviors after Ic was lowered were relatively simple, being based on the signal-to-noise ratio, whereas those for lowered Vb values were complicated because of the dynamic behaviors of JJs driven at reduced voltage. The simulation results imply that the operating frequencies decreased because the timing windows narrowed, but the highest energy efficiency was obtained when we lowered Ic or Vb to 6.25% of their conventional values, and the energy reduction after lowering of Vb was 26% better than that after lowering of Ic. Moreover, if a small error rate (for example 10-6) is acceptable, further improvement in energy efficiency would be expected at significantly higher clock frequencies than would be the case if the SFQ circuit must exhibit error-free operation.

DOI： 10.1109/TASC.2021.3067827

Demonstration of a 52-GHz Bit-Parallel Multiplier Using Low-Voltage Rapid Single-Flux-Quantum Logic 査読有り国際誌

Ikki Nagaoka, Koki Ishida, Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita, Takatsugu Ono, Koji Inoue, Akira Fujimaki

IEEE Transactions on Applied Superconductivity 2021年

SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices 査読有り国際共著

Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, Koji Inoue

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 頁： 58 - 72 2020年10月

32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic 査読有り国際誌

Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue

2020 IEEE Symposium on VLSI Circuits 2020年6月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

A Single-Flux-Quantum (SFQ) 4-bit throughput-oriented processor has successfully been demonstrated at up to 32 GHz with the measured power consumption of 6.5 mW. This is the first implementation of the gate-level-pipelined processor, and it achieves 2.5 Tera-Operations Per Watt (TOPS/W) by circuit and architectural optimizations.

DOI： 10.1109/VLSICircuits18222.2020.9162826

ムーアの法則の限界が見えた今，デバイス研究はどこに向かうのか ―コンピュータアーキテクチャの視点から― 査読有り

井上弘士, 川上哲志, 田中雅光

電子情報通信学会誌 102 巻 ( 10 ) 頁： 957-962 2019年10月

Fundamental Study on the Nanocryotron Properties by the Numerical Calculation

Inoue Masumi, Izaki Kazuki, Goto Yuki, Sano Kyosuke, Yamashita Taro, Tanaka Masamitsu, Fujimaki Akira

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 29 巻 ( 5 ) 2019年8月

A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic 査読有り国際誌

Nagaoka Ikki, Tanaka Masamitsu, Inoue Koji, Fujimaki Akira

2019 IEEE International Solid-State Circuits Conference (ISSCC) 62 巻頁： 460 2019年2月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8-bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0-μm, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.

DOI： 10.1109/ISSCC.2019.8662351

Web of Science

Magnetic Josephson Junctions on Nb Four-layer Structure for Half Flux Quantum Circuits

Hasegawa Daiki, Takeshita Yuto, Sano Kyosuke, Tanaka Masamitsu, Fujimaki Akira, Yamashita Taro

2019 IEEE INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2019年

Demonstration of an Energy-Efficient, Gate-Level-Pipelined 100 TOPS/W Arithmetic Logic Unit Based on Low-Voltage Rapid Single-Flux-Quantum Logic

Nagaoka Ikki, Tanaka Masamitsu, Sano Kyosuke, Yamashita Taro, Fujimaki Akira, Inoue Koji

2019 IEEE INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) 2019年

超伝導単一磁束量子回路による50 GHzビット並列演算マイクロプロセッサに向けた要素回路設計招待有り査読有り

田中雅光, 佐藤諒, 石田浩貴, 畑中湧貴, 松井裕一, 小野貴継, 井上弘士, 藤巻朗

電子情報通信学会論文誌C 101-C 巻 ( 10 ) 頁： 389-399 2018年9月

Energy/Space-Efficient Rapid Single-Flux-Quantum Circuits by Using pi-Shifted Josephson Junctions

Kamiya Tomohiro, Tanaka Masamitsu, Sano Kyosuke, Fujimaki Akira

IEICE TRANSACTIONS ON ELECTRONICS E101C 巻 ( 5 ) 頁： 385-390 2018年5月

Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing 招待有り査読有り

Ishida Koki, Tanaka Masamitsu, Ono Takatsugu, Inoue Koji

IEICE Transactions on Electronics E101C 巻 ( 5 ) 頁： 359-369 2018年5月

Thermally Assisted Superconductor Transistors for Josephson-CMOS Hybrid Memories 招待有り査読有り

Sano Kyosuke, Suzuki Masato, Maruyama Kohei, Taniguchi Soya, Tanaka Masamitsu, Fujimaki Akira, Inoue Masumi, Yoshikawa Nobuyuki

IEICE Transactions on Electronics E101C 巻 ( 5 ) 頁： 370-377 2018年5月

単一磁束量子回路に基づくマイクロプロセッサの動向と展望査読有り

田中雅光, 藤巻朗, 井上弘士

低温工学 52 巻 ( 5 ) 頁： 323-331 2017年9月

Investigation Into the Individual Configuration of Superconducting Phase Shift Elements Made of Ferromagnetic Patterns for Reconfigurable Circuits 査読有り

Taniguchi Soya, Ito Hiroshi, Ishikawa Kouta, Kurokawa Sota, Tanaka Masamitsu, Akaike Hiroyuki, Fujimaki Akira

IEEE Transactions on Applied Superconductivity 27 巻 ( 4 ) 2017年6月

Josephson-CMOS Hybrid Memory With Nanocryotrons 査読有り

Tanaka Masamitsu, Suzuki Masato, Konno Gen, Ito Yuki, Fujimaki Akira, Yoshikawa Nobuyuki

IEEE Transactions on Applied Superconductivity 27 巻 ( 4 ) 2017年6月

High-Speed Operation of Random-Access-Memory-Embedded Microprocessor With Minimal Instruction Set Architecture Based on Rapid Single-Flux-Quantum Logic 招待有り査読有り

Sato Ryo, Hatanaka Yuki, Ando Yuki, Tanaka Masamitsu, Fujimaki Akira, Takagi Kazuyoshi, Takagi Naofumi

IEEE Transactions on Applied Superconductivity 27 巻 ( 4 ) 頁： 1300505 2017年6月

単一磁束量子回路向けマイクロプロセッサのアーキテクチャ探索査読有り

石田浩貴, 田中雅光, 小野貴継, 井上弘士

情報処理学会論文誌 58 巻 ( 3 ) 頁： 629–643 2017年3月

強磁性パターンを用いた磁束量子パラメトロンの論理機能切り替え査読有り

伊藤大, 谷口壮耶, 黒川綜太, 田中雅光, 赤池宏之, 藤巻朗

電気学会論文誌Ａ（基礎・材料・共通部門誌） 136 巻 ( 12 ) 頁： 753-758 2016年12月

Development of an Optimizer for Vortex Transitional Memory Using Particle Swarm Optimization 招待有り査読有り

Karamuftuoglu Mustafa Altay, Demirhan Seda, Komura Yuto, Celik Mustafa Eren, Tanaka Masamitsu, Bozbey Ali, Fujimaki Akira

IEEE Transactions on Applied Superconductivity 26 巻 ( 8 ) 2016年12月

シャント抵抗を排した低電圧駆動単一磁束量子回路の低エネルギー化査読有り

田中雅光, 佐藤諒, 畑中湧貴, 藤巻朗

電気学会論文誌Ａ（基礎・材料・共通部門誌） 136 巻 ( 12 ) 頁： 740-746 2016年12月

High-Density Shift-Register-Based Rapid Single-Flux-Quantum Memory System for Bit-Serial Microprocessors 査読有り

Tanaka Masamitsu, Sato Ryo, Hatanaka Yuki, Fujimaki Akira

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 26 巻 ( 5 ) 2016年8月

Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4 査読有り

Ando Yuki, Sato Ryo, Tanaka Masamitsu, Takagi Kazuyoshi, Takagi Naofumi, Fujimaki Akira

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 26 巻 ( 5 ) 2016年8月

High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation 査読有り

Tanaka Masamitsu, Takagi Kazuyoshi, Takagi Naofumi

IEICE Transactions on Electronics E99C 巻 ( 6 ) 頁： 703-709 2016年6月

Development of an Advanced Circuit Model for Superconducting Strip Line Detector Arrays 査読有り

Bozbey Ali, Kita Yuma, Kamiya Kyohei, Kozaka Misaki, Tanaka Masamitsu, Ishida Takekazu, Fujimaki Akira

IEICE TRANSACTIONS ON ELECTRONICS E99C 巻 ( 6 ) 頁： 676-682 2016年6月

Rapid Single-Flux-Quantum Circuits Fabricated Using 20-kA/cm² Nb/AlOx/Nb Process 査読有り

Masamitsu Tanaka, Misaki Kozaka, Yuma Kita, Akira Fujimaki, Shuichi Nagasawa, Mutsuo Hidaka

IEEE Trans. Appl. Supercond. 25 巻 ( 3 ) 頁： 1100304 2015年6月

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