Country：Japan

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Authorship：Lead author   Language：English  

DOI： https://doi.org/10.21820/23987073.2019.10.44

Language：English   Publisher：Fuji Technology Press Ltd.  

<p>The three-dimensional (3D) normal distributions transform (NDT) is a popular scan registration method for 3D point cloud datasets. It has been widely used in sensor-based localization and mapping applications. However, the NDT cannot entirely utilize the computing power of modern many-core processors, such as graphics processing units (GPUs), because of the NDT’s linear nature. In this study, we investigated the use of NVIDIA’s GPUs and their programming platform called compute unified device architecture (CUDA) to accelerate the NDT algorithm. We proposed a design and implementation of our GPU-accelerated 3D NDT (GPU NDT). Our methods can achieve a speedup rate of up to 34 times, compared with the NDT implemented in the point cloud library (PCL).</p>

DOI： 10.20965/jrm.2023.p0445

Web of Science

CiNii Research

Authorship：Last author   Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ICECET55527.2022.9873044

Authorship：Last author   Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.24297/ijct.v22i.9231

Other Link： https://rajpub.com/index.php/ijct/article/view/9231

Language：English  

Web of Science

Language：English  

DOI： 10.3390/s22052067

Web of Science

Language：English   Publisher：Information Processing Society of Japan  

DOI： 10.2197/ipsjjip.30.141

CiNii Research

Authorship：Lead author,　Last author,　Corresponding author   Language：Japanese   Publisher：THE INSTITUTE OF SYSTEMS, CONTROL AND INFORMATION ENGINEERS  

DOI： 10.11509/isciesci.66.1_21

CiNii Research

Language：English   Publisher：Fuji Technology Press Ltd.  

<p>The perception of the surrounding circumstances is an essential task for fully autonomous driving systems, but its high computational and network loads typically impede a single host machine from taking charge of the systems. Decentralized processing is a candidate to decrease such loads; however, it has not been clear that this approach fulfills the requirements of onboard systems, including low latency and low power consumption. Embedded oriented graphics processing units (GPUs) are attracting great interest because they provide massively parallel computation capacity with lower power consumption compared to traditional GPUs. This study explored the effects of decentralized processing on autonomous driving using embedded oriented GPUs as decentralized units. We implemented a prototype system that off-loaded image-based object detection tasks onto embedded oriented GPUs to clarify the effects of decentralized processing. The results of experimental evaluation demonstrated that decentralized processing and network quantization achieved approximately 27 ms delay between the feeding of an image and the arrival of detection results to the host as well as approximately 7 W power consumption on each GPU and network load degradation in orders of magnitude. Judging from these results, we concluded that decentralized processing could be a promising approach to decrease processing latency, network load, and power consumption toward the deployment of autonomous driving systems.</p>

DOI： 10.20965/jrm.2021.p0686

Web of Science

CiNii Research

Language：Japanese  

Web of Science

Language：English   Publisher：The Institute of Electronics, Information and Communication Engineers  

<p>We present an accurate and easy-to-use multi-sensor fusion toolbox for autonomous vehicles. It includes a ‘target-less’ multi-LiDAR (Light Detection and Ranging), and Camera-LiDAR calibration, sensor fusion, and a fast and accurate point cloud ground classifier. Our calibration methods do not require complex setup procedures, and once the sensors are calibrated, our framework eases the fusion of multiple point clouds, and cameras. In addition we present an original real-time ground-obstacle classifier, which runs on the CPU, and is designed to be used with any type and number of LiDARs. Evaluation results on the KITTI dataset confirm that our calibration method has comparable accuracy with other state-of-the-art contenders in the benchmark.</p>

DOI： 10.1587/transfun.2019tsp0005

Web of Science

CiNii Research

Language：Japanese  

DOI： 10.1109/PDP50117.2020.00034

Web of Science

Language：Japanese  

DOI： 10.1109/ACCESS.2020.3027023

Web of Science

Language：Japanese  

DOI： 10.1109/ACCESS.2020.3040432

Web of Science

Language：Japanese  

Web of Science

Language：Japanese  

DOI： 10.1016/j.robot.2018.10.004

Web of Science

Language：Japanese  

Web of Science

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Web of Science

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Web of Science

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DOI： 10.1109/TPDS.2017.2677451

Web of Science

Language：Japanese  

Web of Science

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Web of Science

Language：English   Publisher：富士技術出版株式会社  

<p>This paper describes our approach to perform robust monocular camera metric localization in the dynamic environments of Tsukuba Challenge 2016. We address two issues related to vision-based navigation. First, we improved the coverage by building a custom vocabulary out of the scene and improving upon place recognition routine which is key for global localization. Second, we established possibility of lifelong localization by using previous year's map. Experimental results show that localization coverage was higher than 90% for six different data sets taken in different years, while localization average errors were under 0.2 m. Finally, the average of coverage for data sets tested with maps taken in different years was of 75%.</p>

DOI： 10.20965/jrm.2017.p0685

Language：English   Publisher：Fuji Technology Press Ltd.  

<p>For the 2015 Tsukuba Challenge, we realized an implementation of vision-based localization based on ORB-SLAM. Our method combined mapping based on ORB-SLAM and Velodyne LIDAR SLAM, and utilized these maps in a localization process using only a monocular camera. We also apply sensor fusion method of odometer and ORB-SLAM from all maps. The combined method delivered better accuracy than the original ORB-SLAM, which suffered from scale ambiguities and map distance distortion. This paper reports on our experience when using ORB-SLAM for visual localization, and describes the difficulties encountered.</p>

DOI： 10.20965/jrm.2016.p0479

CiNii Research

Language：Japanese  

Web of Science

Language：Japanese  

DOI： 10.1109/TPDS.2015.2453962

Web of Science

Language：Japanese  

DOI： 10.1109/MCSoC.2016.40

Web of Science

Language：Japanese  

DOI： 10.1109/CPSNA.2016.10

Web of Science

Language：English   Publisher：一般社団法人 情報処理学会  

In this paper, we propose a system-level design method for control systemsthat enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequencyof interrupts. As a result, the processor load increases, leading to a deterioration in thelatency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by aninterrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicatedhardware to be developed using a model that abstracts an interrupt, interruptprocessing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates thetarget implementation from the model. Case studies on a motor control system show that the proposed methodreduces the processor load, improves the latency of the interrupt processing,and enables the design space exploration for the control system.In this paper, we propose a system-level design method for control systemsthat enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequencyof interrupts. As a result, the processor load increases, leading to a deterioration in thelatency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by aninterrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicatedhardware to be developed using a model that abstracts an interrupt, interruptprocessing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates thetarget implementation from the model. Case studies on a motor control system show that the proposed methodreduces the processor load, improves the latency of the interrupt processing,and enables the design space exploration for the control system.

DOI： 10.2197/ipsjjip.23.532

Language：English   Publisher：一般社団法人 情報処理学会  

DOI： 10.2197/ipsjjip.23.117

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

近年,制御の分野では制御の高精度化が進んでいる.しかし,高精度な制御はシングルコアで処理するには演算負荷が大きい.そこでマルチ・メニーコアの使用が考えられる.高精度な制御として,モデル予測制御がある.この手法では,制御対象の振る舞いをある一定の範囲先まで計算を行う.この計算は制御対象のモデルを用いて行われ,漸化式となる.この漸化式が非線形の場合,漸化式計算は行列計算として表すことができず,計算負荷が大きい上,並列化が難しい.そこで本研究では,この時間かかる非線形漸化式や,それを含む制御の計算の並列実行を検討する.まず漸化式の計算をSimulinkモデルにより記述し,その構造を元にタスク(関数)に分割されたCコードと,そのタスクグラフを生成する.このタスクグラフに対し,CP/MISF法を使用してスケジューリングを行う.16コアのメニーコアシミュレータ上で評価した結果,CP/MISF法を使用すると,非線形漸化式の計算を16コアで10.5倍高速化できることがわかった.また,Simulated Annealing法と比較したところ,並列性能が良く,スケジューリング時間も6桁程度高速であり,CP/MISF法が,非線形漸化式の並列実行に適していることを示した.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

近年,制御の分野では制御の高精度化が進んでいる.しかし,高精度な制御はシングルコアで処理するには演算負荷が大きい.そこでマルチ・メニーコアの使用が考えられる.高精度な制御として,モデル予測制御がある.この手法では,制御対象の振る舞いをある一定の範囲先まで計算を行う.この計算は制御対象のモデルを用いて行われ,漸化式となる.この漸化式が非線形の場合,漸化式計算は行列計算として表すことができず,計算負荷が大きい上,並列化が難しい.そこで本研究では,この時間かかる非線形漸化式や,それを含む制御の計算の並列実行を検討する.まず漸化式の計算をSimulinkモデルにより記述し,その構造を元にタスク(関数)に分割されたCコードと,そのタスクグラフを生成する.このタスクグラフに対し,CP/MISF法を使用してスケジューリングを行う.16コアのメニーコアシミュレータ上で評価した結果,CP/MISF法を使用すると,非線形漸化式の計算を16コアで10.5倍高速化できることがわかった.また,Simulated Annealing法と比較したところ,並列性能が良く,スケジューリング時間も6桁程度高速であり,CP/MISF法が,非線形漸化式の並列実行に適していることを示した.

Language：Japanese   Publisher：一般社団法人情報処理学会  

近年,制御の分野では制御の高精度化が進んでいる.しかし,高精度な制御はシングルコアで処理するには演算負荷が大きい.そこでマルチ・メニーコアの使用が考えられる.高精度な制御として,モデル予測制御がある.この手法では,制御対象の振る舞いをある一定の範囲先まで計算を行う.この計算は制御対象のモデルを用いて行われ,漸化式となる.この漸化式が非線形の場合,漸化式計算は行列計算として表すことができず,計算負荷が大きい上,並列化が難しい.そこで本研究では,この時間かかる非線形漸化式や,それを含む制御の計算の並列実行を検討する.まず漸化式の計算を Simulink モデルにより記述し,その構造を元にタスク (関数) に分割された C コードと,そのタスクグラフを生成する.このタスクグラフに対し,CP/MISF 法を使用してスケジューリングを行う.16 コアのメニーコアシミュレータ上で評価した結果,CP/MISF法 を使用すると,非線形漸化式の計算を 16 コアで 10.5 倍高速化できることがわかった.また,Simulated Annealing 法と比較したところ,並列性能が良く,スケジューリング時間も 6 桁程度高速であり,CP/MISF 法が,非線形漸化式の並列実行に適していることを示した.

CiNii Research

Language：Japanese   Publisher：一般社団法人情報処理学会  

近年,制御の分野では制御の高精度化が進んでいる.しかし,高精度な制御はシングルコアで処理するには演算負荷が大きい.そこでマルチ・メニーコアの使用が考えられる.高精度な制御として,モデル予測制御がある.この手法では,制御対象の振る舞いをある一定の範囲先まで計算を行う.この計算は制御対象のモデルを用いて行われ,漸化式となる.この漸化式が非線形の場合,漸化式計算は行列計算として表すことができず,計算負荷が大きい上,並列化が難しい.そこで本研究では,この時間かかる非線形漸化式や,それを含む制御の計算の並列実行を検討する.まず漸化式の計算を Simulink モデルにより記述し,その構造を元にタスク (関数) に分割された C コードと,そのタスクグラフを生成する.このタスクグラフに対し,CP/MISF 法を使用してスケジューリングを行う.16 コアのメニーコアシミュレータ上で評価した結果,CP/MISF法 を使用すると,非線形漸化式の計算を 16 コアで 10.5 倍高速化できることがわかった.また,Simulated Annealing 法と比較したところ,並列性能が良く,スケジューリング時間も 6 桁程度高速であり,CP/MISF 法が,非線形漸化式の並列実行に適していることを示した.

CiNii Research

Language：Japanese   Publisher：一般社団法人情報処理学会  

Language：English   Publisher：Information and Media Technologies Editorial Board  

This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can be various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by single binary operating systems. Proposed method automatically synthesizes the inter-heterogeneous-processor communications at an application layer from a general model description. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs the system on heterogeneous multiprocessors.

DOI： 10.11185/imt.10.415

CiNii Research

Language：Japanese  

DOI： 10.1109/CPSNA.2015.18

Web of Science

Language：English   Publisher：Information Processing Society of Japan  

DOI： 10.2197/ipsjjip.23.531

CiNii Research

Language：Japanese  

Web of Science

Language：Japanese  

Web of Science

Language：English   Publisher：Information Processing Society of Japan  

This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can be various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by single binary operating systems. Proposed method automatically synthesizes the inter-heterogeneous-processor communications at an application layer from a general model description. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs the system on heterogeneous multiprocessors.

DOI： 10.2197/ipsjtsldm.8.95

CiNii Research

Language：Japanese  

DOI： 10.1109/CPSNA.2015.20

Web of Science

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

本論文ではシステムレベル設計における制御システム向けのプロファイル機構を述べる.制御システムを設計する際,センサーやアクチュエータから非同期で通知される割込みと,割込みにより優先的に処理を開始する割込み処理を考慮する必要がある.但し,既存のプロファイル機構は割込みの関連情報を取得できない.本論文では,制御システムの開発を支援するために,割込みの関連情報を取得可能なプロファイル手法を提案する.提案手法を設計事例に適用し,効果を評価した.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

本論文は,割込みで駆動する専用HWを設計可能な,制御システム向けのシステムレベル設計ツールについて述べる.制御システムは複雑化,処理の高度化が進み,それに伴い割込み処理の頻度が増加したことで,プロセッサ負荷の増加,消費電力の増加,割込み処理レイテンシの悪化といった問題が生じている.これらの問題を解決するため,割込みにより処理を開始し,処理中はセンサや入出力ハードウェアといったデバイスへ直接アクセスする専用ハードウェアが求められている.提案手法は,処理とデバイス間の通信,割込み,割込み処理を抽象化した制御システムモデルから,割込みで駆動するハードウェアを含む制御システムを設計可能である.モータ制御システムを対象とした評価実験により,提案手法を用いることで,プロセッサ負荷の削減,消費電力の削減,レイテンシの改善が可能なことを示す.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

本論文は,割込みで駆動する専用HWを設計可能な,制御システム向けのシステムレベル設計ツールについて述べる.制御システムは複雑化,処理の高度化が進み,それに伴い割込み処理の頻度が増加したことで,プロセッサ負荷の増加,消費電力の増加,割込み処理レイテンシの悪化といった問題が生じている.これらの問題を解決するため,割込みにより処理を開始し,処理中はセンサや入出力ハードウェアといったデバイスへ直接アクセスする専用ハードウェアが求められている.提案手法は,処理とデバイス間の通信,割込み,割込み処理を抽象化した制御システムモデルから,割込みで駆動するハードウェアを含む制御システムを設計可能である.モータ制御システムを対象とした評価実験により,提案手法を用いることで,プロセッサ負荷の削減,消費電力の削減,レイテンシの改善が可能なことを示す.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

本論文ではシステムレベル設計における制御システム向けのプロファイル機構を述べる.制御システムを設計する際,センサーやアクチュエータから非同期で通知される割込みと,割込みにより優先的に処理を開始する割込み処理を考慮する必要がある.但し,既存のプロファイル機構は割込みの関連情報を取得できない.本論文では,制御システムの開発を支援するために,割込みの関連情報を取得可能なプロファイル手法を提案する.提案手法を設計事例に適用し,効果を評価した.

Language：Japanese   Publisher：一般社団法人情報処理学会  

近年,半導体技術の進展によって 1 つの LSI 上に複数のプロセッサが搭載されたマルチコアや,数十,数百のプロセッサが搭載されたメニーコアが広く使われている.また,スケーラビリティをさらに高めるために階層構造を持つメニーコアも登場している.階層型メニーコアアーキテクチャは,将来組込みプロセッサにおいても主流になると考えられている.そこで,階層構造を考慮したタスクマッピング手法を提案し,既存手法との比較評価を行った.提案手法は NN Embed 法,Topo-LB 法,Cluster-Based ILP 法と比較してそれぞれ 44%,32%,26%通信コストの少ないマッピング結果を示した.

CiNii Research

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

多種多様なメニーコアアーキテクチャが提案されてきており,今後ますます増える傾向にある.このような状況において,ソフトウェア開発ツール等がアーキテクチャ毎に個別に対応することは非効率である.これをなくすため我々は,マルチ・メニーコア標準プラットフォームの開発を進め,ソフトウェア視点での性能情報を含むハードウェア記述の標準化を提案している.本研究では,組込みメニーコアプロセッサの一つを用い,標準記述による性能見積りと実際の処理時間の差異を評価し,精度を高めるための手法及び課題について述べる.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

近年,組込み制御分野でマルチ・メニーコアの使用が主流となりつつある.複数のコアで制御プログラムを並列に動作させる場合,コア間通信のオーバーヘッドが大きな問題である.そこで,我々は単方向1:1高速同期機構とよぶ高速な通信メカニズムを提案し,その改善を図っている.本稿では,提案機構向けに新たに考案したハードウェア支援手法とFPGAによる評価結果を報告する.モーター制御アプリケーションを用いた評価では,提案手法はマルチコアRTOSの通信APIと比べ,通信時間が約12分の1に短縮された.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

近年,組込み制御分野でマルチ・メニーコアの使用が主流となりつつある.複数のコアで制御プログラムを並列に動作させる場合,コア間通信のオーバーヘッドが大きな問題である.そこで,我々は単方向1:1高速同期機構とよぶ高速な通信メカニズムを提案し,その改善を図っている.本稿では,提案機構向けに新たに考案したハードウェア支援手法とFPGAによる評価結果を報告する.モーター制御アプリケーションを用いた評価では,提案手法はマルチコアRTOSの通信APIと比べ,通信時間が約12分の1に短縮された.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

多種多様なメニーコアアーキテクチャが提案されてきており,今後ますます増える傾向にある.このような状況において,ソフトウェア開発ツール等がアーキテクチャ毎に個別に対応することは非効率である.これをなくすため我々は,マルチ・メニーコア標準プラットフォームの開発を進め,ソフトウェア視点での性能情報を含むハードウェア記述の標準化を提案している.本研究では,組込みメニーコアプロセッサの一つを用い,標準記述による性能見積りと実際の処理時間の差異を評価し,精度を高めるための手法及び課題について述べる.

Language：Japanese  

Web of Science

Language：Japanese  

Web of Science

Language：Japanese   Publisher：The Society of Instrument and Control Engineers  

DOI： 10.11499/sicejl.53.1111

CiNii Research

Language：Japanese  

DOI： 10.1109/IPDPS.2014.23

Web of Science

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heterogeneous multiprocessors. Along with the increase in the use of heterogeneous multiprocessors such as FPGAs with processor cores, the cost for design and implement of the inter-processor communication becomes a problem. Focusing on that typical heterogeneous multiprocessors have inter-processor interrupts and shared memories, we propose an implementation of inter-processor communication using them. In order to increase the design efficiency, we also propose a method that automatically generates the inter-processor communication for target systems. The case study shows that automatically generated inter-processor communication exactly runs on the system with heterogeneous multiprocessors.

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

We propose a system level design methodology for control systems that have both input and output by abstraction of interrupt handling. Since control systems are increasing their complexity, the designers have to design them on higher level of abstraction to increase design efficiency. System level design is known as one of the way to realize that. However, they cannot handle control systems because they do not consider interrupt handling. We propose a model that deals with control systems at system level by abstraction of interrupt handling. The case study shows that our proposing model has few overhead on memory usage and execution time.

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

We propose a system level design methodology for control systems that have both input and output by abstraction of interrupt handling. Since control systems are increasing their complexity, the designers have to design them on higher level of abstraction to increase design efficiency. System level design is known as one of the way to realize that. However, they cannot handle control systems because they do not consider interrupt handling. We propose a model that deals with control systems at system level by abstraction of interrupt handling. The case study shows that our proposing model has few overhead on memory usage and execution time.

Language：Japanese   Publisher：一般社団法人情報処理学会  

組込み制御領域において,マルチ・メニーコア化とこれを活用するための制御ソフトウェアの並列化が進められている.しかし期待される処理性能のボトルネックとして,タスクスケジューリングやプロセッサ間通信のオーバヘッドが存在する.1 コア 1 タスクに静的割付けし,単方向 1:1 高速同期機構による通信を用いることで,モータ制御モデルを用いた性能評価において,メニーコア向け高機能 OS 利用と比較して通信時間を 25 分の 1 とし,実行サイクルを逐次実行よりも 25% 程度低減することができた.

Language：Japanese   Publisher：一般社団法人情報処理学会  

組込み制御領域において,マルチ・メニーコア化とこれを活用するための制御ソフトウェアの並列化が進められている.しかし期待される処理性能のボトルネックとして,タスクスケジューリングやプロセッサ間通信のオーバヘッドが存在する.1 コア 1 タスクに静的割付けし,単方向 1:1 高速同期機構による通信を用いることで,モータ制御モデルを用いた性能評価において,メニーコア向け高機能 OS 利用と比較して通信時間を 25 分の 1 とし,実行サイクルを逐次実行よりも 25% 程度低減することができた.

Language：Japanese   Publisher：一般社団法人情報処理学会  

近年,マルチコア・メニーコアが組込みシステムにおいても主流となりつつある.また,制御システムの大規模複雑化による開発工数の増大が課題となっている.そのため,メニーコアであるイベントドリブンプロセッサを用い,タスクをコアに対応させることで制御モデルの実装を行うことを考える.これにより,同一コア内でのタスクスケジューリングが不要となり,開発工数の削減が期待できる.このとき,複数の制御周期が混在するマルチレートモデル,特に制御周期が動的に変化する場合が課題となる.本論文ではマルチレート制御モデルをイベントドリブンプロセッサに実現する手法を提案し,ベンチマークとして制御モデルを実装することで,提案手法の有効性を評価した.

Language：Japanese   Publisher：一般社団法人情報処理学会  

本研究では,組込み制御システムにおいて近年研究が進められているモデルベース並列化に着目し,制御系の離散実装時に多くあらわれる差分方程式に対して,並列化前後の誤差を 0 にする,前進差分型・後退差分型の各並列化手法とそのモデリング手法を提案する.提案手法を用いて MATLAB/Simulink で記述された実際のモータ制御モデルを並列設計し,前進差分型と比較して後退差分型の並列性の性能向上を示すと共に,従来経験的に与えられていた遅延要素の初期値設定に関して,解析的な導出方法を提案する.従来のアプローチを適用できないモデルに対して,提案手法の有効性を実証する.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

近年,マルチコア・メニーコアが組込みシステムにおいても主流となりつつある.また,制御処理を記述する上で有効なソフトウェアモデルとして,CSP (Communicating Sequential Processes)があげられる.本論文では,汎用マイクロコントローラベースのマルチコアシステムをターゲットとし,CSPにより記述されたモーター制御モデルの実装を行い,実行時間が最小となるタスク割当てパターンを非線形計画問題によって発見した.また,従来手法から得られたタスク割り当てパターンと性能比較を行った結果,従来手法に比べ15%性能を改善することができた.

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

近年,マルチコア・メニーコアが組込みシステムにおいても主流となりつつある.また,制御処理を記述する上で有効なソフトウェアモデルとして,CSP (Communicating Sequential Processes)があげられる.本論文では,汎用マイクロコントローラベースのマルチコアシステムをターゲットとし,CSPにより記述されたモーター制御モデルの実装を行い,実行時間が最小となるタスク割当てパターンを非線形計画問題によって発見した.また,従来手法から得られたタスク割り当てパターンと性能比較を行った結果,従来手法に比べ15%性能を改善することができた.

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Our society faces a core challenge to societal problems, including environmental pollution and aging population, and industrial problems. This raises the need of integrated infrastructure systems that bring innovations to both the society and industrial technology. One of such systems is a cyber-physical systems (CPS), which tightly coordinates computation and communication with real-world elements. CPS represents multidisciplinary computer systems and its systematic model has not been well explored. Each individual technology of CPS also faces a core challenge to meet the performance and functional requirements. In this paper. we argue a possible research direction of applying LSI design technologies to CPS in terms of optimization problems of platforms and applications, introducing cutting-edge CPS technology in the state of the art.

Language：English   Publisher：一般社団法人電子情報通信学会  

Language：English   Publisher：一般社団法人電子情報通信学会  

Language：English   Publisher：一般社団法人電子情報通信学会  

Language：Japanese  

DOI： 10.1109/ICPADS.2013.47

Web of Science

Language：Japanese  

Web of Science

Language：Japanese  

Web of Science

Language：English   Publisher：一般社団法人電子情報通信学会  

本研究ではマルチスカラー倍算における非対称数字表現の平均的な効率を定める手法を提案する。マルチスカラー倍算は楕円曲線デジタル署名アルゴリズム(ECDSA)において最も計算時間を要する演算であるため、表現数字集合拡大をはじめ様々な研究がされている。表現数字集合を拡大するとマルチスカラー倍算は高速化されるが、前処理に長い時間を要する。そこで、我々は非対称数字表現を提案し、マルコフ連鎖やグラフ理論を利用して解析を行った。その結果、非対称数字表現は前処理を拡大数字集合ほど必要とせず、効率も高いと確認できた。

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FPGA and STP engine in order to confirm their performance whether they can substitute the dedicated hardware of SoC. We selected AES and ADPCM applications to compare the performance of FPGA and STP engine. The applications were synthesized with the same behavioral synthesis tools. Then, we implemented them onto FPGA and STP engine using the integrated development environments. For the evaluation, we compared them in terms of hardware area, the number of states, the number of cycles, frequency, and execution time.

Language：English   Publisher：一般社団法人情報処理学会  

A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice.

DOI： 10.2197/ipsjtsldm.5.133

Language：English   Publisher：The Institute of Electronics, Information and Communication Engineers  

CiNii Research

Authorship：Last author   Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Society of Automotive Engineers of Japan, INC  

ABSTRACT: Ego-vehicle localization is a critical technology in autonomous driving systems, and one of the widely used methods for localization is scan matching between a 3D map and real-time LiDAR scan. This method is known to fail due to factors such as an incorrect initial position and orientation for scan matching. In this paper, we propose a simulator-based localization evaluation framework to verify the robustness of localization. By using a simulator, localization can be evaluated without driving a real vehicle, and can be evaluated by creating disturbances such as traffic jams. Our framework also allows to evaluate the robustness of localization by using multiple particles with random errors of the initial position and orientation for scan matching to simulate dead reckoning errors caused by multiple factors such as road surface conditions and tire diameter. In the evaluation experiments, we confirmed that the robustness of localization can be evaluated by applying this method to factors such as sensor setup, disturbances in the traffic environment, and the amount of 3D features in the environment.

DOI： 10.20485/jsaeijae.13.4_206

CiNii Research

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Part of collection (book)  

Language：Japanese   Publishing type：Part of collection (book)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Fuji Technology Press Ltd.  

<p>Clustering is the task of dividing an input dataset into groups of objects based on their similarity. This process is frequently required in many applications. However, it is computationally expensive when running on traditional CPUs due to the large number of connections and objects the system needs to inspect. In this paper, we investigate the use of NVIDIA graphics processing units and their programming platform CUDA in the acceleration of the Euclidean clustering (EC) process in autonomous driving systems. We propose GPU-accelerated algorithms for the EC problem on point cloud datasets, optimization strategies, and discuss implementation issues of each method. Our experiments show that our solution outperforms the CPU algorithm with speedup rates up to 87X on real-world datasets.</p>

DOI： 10.20965/jrm.2020.p0548

CiNii Research

Language：English   Publishing type：Research paper (scientific journal)  

DOI： https://doi.org/10.1587/transfun.2019TSP0005

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

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Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

DOI： https://doi.org/10.1016/j.robot.2018.10.004

Language：English   Publishing type：Research paper (scientific journal)  

DOI： https://doi.org/10.1109/ACCESS.2019.2895701

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1016/j.robot.2018.10.004

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/ACCESS.2019.2895701

Web of Science

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1109/ACCESS.2018.2883415

Web of Science

Language：English   Publishing type：Research paper (scientific journal)  

DOI： https://doi.org/10.1109/ACCESS.2018.2883415

Language：English  

Language：English   Publishing type：Research paper (other academic)  

Language：English  

DOI： https://doi.org/10.1109/HPCS.2018.00046

Language：English  

Language：English   Publishing type：Research paper (other academic)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (other academic)  

DOI： 10.1109/HPCS.2018.00046

Web of Science

Other Link： https://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2018.html#NguyenEK18

Publishing type：Research paper (international conference proceedings)  

DOI： 10.1145/3217189.3217194

Other Link： https://dblp.uni-trier.de/db/conf/hpdc/ross2018.html#LiuKE18

Language：English  

Language：English   Publishing type：Research paper (other academic)  

Language：Japanese   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Fuji Technology Press  

This paper describes our approach to perform robust monocular camera metric localization in the dynamic environments of Tsukuba Challenge 2016. We address two issues related to vision-based navigation. First, we improved the coverage by building a custom vocabulary out of the scene and improving upon place recognition routine which is key for global localization. Second, we established possibility of lifelong localization by using previous year’s map. Experimental results show that localization coverage was higher than 90% for six different data sets taken in different years, while localization average errors were under 0.2 m. Finally, the average of coverage for data sets tested with maps taken in different years was of 75%.

DOI： 10.20965/jrm.2017.p0685

Scopus

Language：English  

Language：English  

Language：English  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE COMPUTER SOC  

Object detection is a fundamental challenge facing intelligent applications. Image processing is a promising approach to this end, but its computational cost is often a significant problem. This paper presents schemes for accelerating the deformable part models (DPM) on graphics processing units (GPUs). DPM is a well-known algorithm for image-based object detection, and it achieves high detection rates at the expense of computational cost. GPUs are massively parallel compute devices designed to accelerate dataparallel compute-intensive workload. According to an analysis of execution times, approximately 98 percent of DPM code exhibits loop processing, which means that DPM could be highly parallelized by GPUs. In this paper, we implement DPM on the GPU by exploiting multiple parallelization schemes. Results of an experimental evaluation of this GPU-accelerated DPM implementation demonstrate that the best scheme of GPU implementations using an NVIDIA GPU achieves a speed up of 8.6x over a naive CPU-based implementation.

DOI： 10.1109/TPDS.2015.2453962

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing manycore processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor.
We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the twodimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.

DOI： 10.1109/MCSoC.2016.40

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper presents a parallelization method utilizing dead time to implement higher precision feedback control systems in multicore processors. The feedback control system is known to be difficult to parallelize, and it is difficult to deal with the dead time in control systems. In our method, the dead time is explicitly represented as delay elements. Then, these delay elements are distributed to the overall systems with equivalent transformation so that the system can be simulated or executed in parallel pipeline operation. In addition, we introduce a method of delay-element addition for parallelization. For a spring-mass-damper model with a dead time, parallel execution of the model using our technique achieves 3.4 times performance acceleration compared with its sequential execution on an ideal four-core simulation and 1.8 times on a cycle-accurate simulator of a four-core embedded processor as a threaded application on a real-time operating system.

DOI： 10.1587/transele.e99.c.491

Web of Science

CiNii Research

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

In this paper, we aim to explore path following. We implement a path following component by referring to the existing Pure Pursuit algorithm. Using the simulation and field operational test, we identified the problem in the path following component. The main problems identified were with respect to vehicles meandering off the path, turning a corner, and the instability of steering control. Therefore, we apply some modifications to the Pure Pursuit[1] algorithm. We have also conducted the simulation and field operational tests again to evaluate these modifications.

DOI： 10.1109/CPSNA.2016.10

Web of Science

Language：Japanese  

Language：Japanese   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Information Processing Society of Japan  

In this paper, we propose a system-level design method for control systems that enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to a deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates the target implementation from the model. Case studies on a motor control system show that the proposed method reduces the processor load, improves the latency of the interrupt processing, and enables the design space exploration for the control system.

DOI： 10.2197/ipsjjip.23.532

Scopus

Language：English   Publishing type：Research paper (scientific journal)  

Language：English  

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Language：English   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：English  

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Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Language：English  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

In this paper, we propose a system-level design tool for control systems that enables the development of hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. Case studies on a motor control system show that the proposed method enables the designer to explore design space of control system, reduces the processor load and improves the latency of the interrupt processing.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Accurate perception information of the surroundings is a desirable feature in any cyber-physical system for autonomous robotics. Besides, providing a cost-wise solution to this need, is also useful for developing other kinds of applications such as mapping, decision-making, self-localization, among others. In this work, we present and benchmark a cost-effective camera device with six image sensors attached to a custom built FPGA board. The perception information is delivered on the host side, thanks to a HOG based object detector executed on the GPU. Our conclusion is that the low cost prototype is able to acquire and extract the perception data in 9.41 frames per second.

DOI： 10.1109/CPSNA.2015.18

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

The development of visualization tools that help us assimilate the information that surrounds us is essential in business environments and most research fields. Data visualization is a powerful tool that lets us recognize patterns and trends easily, allows us to extract sensible information faster, stimulates hypothesis generation, and helps us make effective decisions. This paper describes the design and implementation of a web application that displays moving objects in real-time using Google Maps. This web application was done as part of an integrated system that addresses issues related to the automated driver assistance field. Moreover, this work seeks to be a reference framework that will provide visual support for researchers in the area of mobility looking to analyze moving object trajectories, evaluate prediction models, or explain their results.

DOI： 10.1109/CPSNA.2015.20

Web of Science

Authorship：Lead author   Language：Japanese  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Association for Computing Machinery  

Recently General-Purpose Computing on Graphics Processing Units (GPGPU) has been used to reduce the processing time of various applications, but the degree of acceleration by the Graphical Processing Unit (GPU) depends on the application. This study focuses on data analysis as an application example of GPGPU, specifically, the design and implementation of GPGPU computation libraries for data-intensive workloads. The effects of efficient memory allocation and high-speed read-only memories on the execution time are evaluated. In addition to employing a single GPU, the scalability using multiple GPUs is also evaluated. Compared to a Central Processing Unit (CPU) alone, the memory allocation method reduces the execution time for memory copies by approximately 60% when a GPU is used, while utilizing read-only memories results in an approximately 20% reduction in the overall program execution time. Moreover, expanding the number of GPUs from one to four reduces the execution time by approximately 10%.

DOI： 10.1145/2676585.2676616

Scopus

Language：English  

Language：English  

Language：English  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Language：English  

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

The multi core processors are becoming norm and a processor with even more than a hundred of cores are emerging. These inherently require wide range of software tools to help software developers. However, supporting these complex hardware by the tools require significant effort by the tool vendors, and each invest in adapting the new hardware by modifying their tools or creating proprietary configuration files, while often the similar set of hardware architectural information are needed. The SHIM, Software-Hardware Interface for Multi-many-core, is a joint industrial and academic effort to standardize the interface between the multicore hardware and the software tools. This extended abstract introduces SHIM, the overall architecture, the schema used, the use-cases, and a prototype tool to foster the adaption of the interface.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Graphics processing units (GPUs) provide an order-of-magnitude improvement on peak performance and performance-per-watt as compared to traditional multicore CPUs. However, GPU-accelerated systems currently lack a generalized method of power and performance prediction, which prevents system designers from an ultimate goal of dynamic power and performance optimization. This is due to the fact that their power and performance characteristics are not well captured across architectures, and as a result, existing power and performance modeling approaches are only available for a limited range of particular GPUs. In this paper, we present power and performance characterization and modeling of GPU-accelerated systems across multiple generations of architectures. Characterization and modeling both play a vital role in optimization and prediction of GPU-accelerated systems. We quantify the impact of voltage and frequency scaling on each architecture with a particularly intriguing result that a cutting-edge Kepler-based GPU achieves energy saving of 75% by lowering GPU clocks in the best scenario, while Fermi-and Tesla-based GPUs achieve no greater than 40% and 13%, respectively. Considering these characteristics, we provide statistical power and performance modeling of GPU-accelerated systems simplified enough to be applicable for multiple generations of architectures. One of our findings is that even simplified statistical models are able to predict power and performance of cutting-edge GPUs within errors of 20% to 30% for any set of voltage and frequency pair.

DOI： 10.1109/IPDPS.2014.23

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.

Web of Science

Language：English  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Graphics processing units (GPUs) embrace many-core compute devices where massively parallel compute threads are offloaded from CPUs. This heterogeneous nature of GPU computing raises non-trivial data transfer problems especially against latency-critical real-time systems. However even the basic characteristics of data transfers associated with GPU computing are not well studied in the literature. In this paper, we investigate and characterize currently-achievable data transfer methods of cutting-edge GPU technology. We implement these methods using open-source software to compare their performance and latency for real-world systems. Our experimental results show that the hardware-assisted direct memory access (DMA) and the I/O read-and-write access methods are usually the most effective, while on-chip microcontrollers inside the GPU are useful in terms of reducing the data transfer latency for concurrent multiple data streams. We also disclose that CPU priorities can protect the performance of GPU data transfers.

DOI： 10.1109/ICPADS.2013.47

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

Vision-based object detection using camera sensors is an essential piece of perception for autonomous vehicles. Various combinations of features and models can be applied to increase the quality and the speed of object detection. A well-known approach uses histograms of oriented gradients (HOG) with deformable models to detect a car in an image [15]. A major challenge of this approach can be found in computational cost introducing a real-time constraint relevant to the real world. In this paper, we present an implementation technique using graphics processing units (GPUs) to accelerate computations of scoring similarity of the input image and the pre-defined models. Our implementation considers the entire program structure as well as the specific algorithm for practical use. We apply the presented technique to the real-world vehicle detection program and demonstrate that our implementation using commodity GPUs can achieve speedups of 3x to 5x in frame-rate over sequential and multithreaded implementations using traditional CPUs. © 2013 IEEE.

DOI： 10.1109/CPSNA.2013.6614255

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper evaluates an automatic power reduction scheme of OSCAR automatic parallelizing compiler having power reduction control capability when multiple media applications parallelized by the OSCAR compiler are executed simultaneously on RP2, a 8-core multicore processor developed by Renesas Electronics, Hitachi, and Waseda University. OSCAR compiler enables the hierarchical multigrain parallel processing and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating and power gating for each processor core using the OSCAR multi-platform API. The RP2 has eight SH4A processor cores, each of which has power control mechanisms such as DVFS, clock gating and power gating. First, multiple applications with relatively light computational load are executed simultaneously on the RP2. The average power consumption of power controlled eight AAC encoder programs, each of which was executed on one processor, was reduced by 47%, (to 1.01W), against one AAC encoder execution on one processor (from 1.89W) without power control. Second, when multiple intermediate computational load applications are executed, the power consumptions of an AAC encoder executed on four processors with the power reduction control was reduced by 57% (to 0.84W) against an AAC encoder execution on one processor (from 1.95W). Power consumptions of one MPEG2 decoder on four processors with power reduction control was reduced by 49% (to 1.01W) against one MPEG2 decoder execution on one processor (from 1.99W). Finally, when a combination of a high computational load application program and an intermediate computational load application program are executed simultaneously, the consumed power reduced by 21% by using twice number of cores for each application. This paper confirmed parallel processing and power reduction by OSCAR compiler are efficient for multiple application executions. In execution of multiple light computational load applications, power consumption increases only 12% for one application. Parallel processing being applied to intermediate computational load applications, power consumption of executing one application on one processor core (1.49W) is almost same power consumption of two applications on eight processor cores (1.46W). © 2013 Springer-Verlag.

DOI： 10.1007/978-3-642-36036-7_3

Scopus

Language：English   Publishing type：Research paper (scientific journal)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English  

Language：English  

Language：English   Publishing type：Research paper (other academic)  

Language：English  

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Language：English   Publishing type：Research paper (scientific journal)  

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Language：English   Publishing type：Research paper (international conference proceedings)  

In this paper, we propose an algorithm to calculate the efficiency of number representations in elliptic curve cryptography, average joint Hamming weight. The method uses Markov chains generated from a minimal weight conversion algorithm of d integers using the minimal weight conversion. With redundant representations using digit sets like {0, ±1}, it is possible to reduce computation time of the cryptosystem. Although larger digit sets make the computation time shorter, it requires longer preprocessing time. Therefore, the average joint Hamming weight is useful to evaluate digit sets. The Markov chains to find the average joint Hamming weight are derived automatically from the conversions. However, the number of states in these Markov chains is generally infinite. In [8], we propose an algorithm to reduce the number of states, but it is still unclear which representations the method can be applied for. In this paper, the finiteness of Markov chain with the existence of a stationary distribution is proven in a class of representation whose digit set D S be a finite set such that there exists a natural number Λ where D S ⊆ {0, ±1, ..., ±Λ} and {0,±1, ±Λ} ⊆ D S. The class covers most of the representation practically used in elliptic curve cryptography such as the representation which digit set are {0, ±1} and {0, ±1, ±3}. © 2012 Springer-Verlag.

DOI： 10.1007/978-3-642-28076-4_23

Scopus

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (scientific journal)  

A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice. © 2012 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.5.133

Scopus

Language：English   Publishing type：Research paper (scientific journal)  

Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization. © 2012 IEEE.

DOI： 10.1109/LES.2012.2193660

Scopus

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (other academic)  

Language：English   Publishing type：Research paper (scientific journal)  

Language：English  

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)  

DPR (Dynamic Partial Reconfiguration) capability found in some of modern FPGAs allows implementation of a concept of a HW (Hardware) task, which similarly to its software counterpart has its state and shares time-multiplexed resources with the other tasks. While the new technology presents many advantages for embedded systems where run-time adaptability is an additional requirement, their efficient and easily portable implementations require a control software or an OS which would manage all the complexities of the underlying technology, providing an abstracted interface for the application programmer. This paper presents a novel and robust hardware multitasking extension for a conventional OS, managing task scheduling and configurations, and providing easy-to-use API (Application Programming Interface) for the application programmer. Scheduling is priority-based and takes advantage of task caching. Moreover, the extension is based on a developed design flow and embedded hardware platform allowing efficient task preemption, which can be utilized whenever it presents any benefits to the application. © 2011 IEEE.

DOI： 10.1109/ReConFig.2011.73

Scopus

Language：English   Publishing type：Research paper (scientific journal)   Publisher：ASSOC COMPUTING MACHINERY  

We propose a robust seamless communication architecture that enables legacy mobile terminal software designed for single-CPU processors to be run on multi-CPU processors without any software modifications. This architecture features two new technologies: proxy processes, which help achieve the design of its user-level system-call hooking and a robust design method, which reduces bandwidth variation by systematic parameter optimization. Our evaluations confirmed that this architecture achieves fundamental features with satisfactory performance, that we have succeeded in getting actual mobile terminal software to run on three CPUs without modifying the software, and that the robust design method reduces bandwidth variation by 21%.

DOI： 10.1145/1698772.1698777

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Fundamental algorithms should be parallelized to accelerate EDA software on multi-core architecture. In this paper, we introduce scalable algorithms that have scalability on multi-cores. As an example, a sorting algorithm, called Map Sort, is presented. This algorithm uses a map from subsets of input data to intervals on data range. Experimental results show that, in comparison with quick sort on a single CPU, processing time of Map Sort is comparable on a CPU and three times faster on four CPUs.

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：ASSOC COMPUTING MACHINERY  

We propose a secure platform on a chip multiprocessor, FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multigrained separation mechanisms. Four new technologies support the FIDES platform: bus filter logic, XIP kernels, policy separation, and dynamic access control. With these technologies, the FIDES platform can tolerate both application-level and kernel-level bugs on an actual download subsystem. Thus, the best-suited platform to secure next generation mobile terminals is FIDES.

DOI： 10.1145/1457246.1457247

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE COMPUTER SOC  

EMBEDDED APPLIANCES SUCH AS HIGH-END CELL PHONES REQUIRE NOT ONLY HIGH PERFORMANCE BUT ALSO A PERFORMANCE GUARANTEE. THE AUTHORS DEMONSTRATE A PERFORMANCE GUARANTEE FRAMEWORK USING AN ASYMMETRIC MULTIPROCESSING APPROACH. THEY IMPLEMENTED THE PROPOSED METHOD ON A MULTICORE PROCESSOR USING LINUX. EVALUATION RESULTS SHOW THAT THE METHOD IMPROVES THE PERFORMANCE GUARANTEE WHILE MAINTAINING SOFTWARE COMPATIBILITY.

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：ASSOC COMPUTING MACHINERY  

We propose a processor virtualization architecture, VIRTUS, to provide a dedicated domain for preinstalled applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies, namely, VMM asymmetrization, dynamic interdomain communication (IDC), and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor. Evaluations have shown that VMM asymmetrization results in significantly less performance degradation and LOC increase than do other VMMs. Further, dynamic IDC overhead is low enough, and virtualization-assist logic can be implemented in a sufficiently small area.

DOI： 10.1145/1367045.1367057

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Reliability of embedded systems can be enhanced by multicore and partitioning approaches. Physical partitioning based on ANW multicore achieves runtime stability of multiple applications in a system and prevents the whole system shutdown as well even when a malicious code creeps in. Combined with logical partitioning by processor virtualization and SMP technologies, the multicore architecture could realize more flexible and more scalable platform for future embedded systems.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ASSOC COMPUTING MACHINERY  

We propose a new processor virtualization architecture, VIRTUS, to provide a dedicated domain for pre-installed applications and virtualized domains for downloaded native applications. With it security-oriented next-generation mobile terminals can provide any number of domains for native applications. VIRTUS features three new technologies: VMM asymmetrization, dynamic inter-domain communication and virtualization-assist logic, and it is first in the world to virtualize an ARM-based multiprocessor.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ASSOC COMPUTING MACHINERY  

We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multi-grained separation mechanisms: coarse-grained processor-level separation of the basic-function domain from other domains for such downloaded applications, medium-grained OS-level separation, and fine-grained process-level separation within SELinux. Four new technologies, which include three enhancements to SELinux, support the FIDES platform: 1) bus filter logic for processor-level separation can be implemented as a small logic, 2) XIP kernels for memory-efficient OS-level separation can reduce memory requirements by 182%, 3) policy separation for enhanced process-level separation can apply policies 2.1 times faster at system boot-up, and 4) dynamic access control can provide secure Inter-Domain Communications (IDCs) with an overhead of only 4% for IDC system calls. We implemented SELinuxes on an ARM-based multiprocessor. Therefore, the best-suited platform to secure next generation mobile terminals is the FIDES platform, which can provide higher security as well as higher performance and lower power consumption on chip multiprocessors leading the current technology trend of microprocessors.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

As the interconnection delays control the LSI performance, the LSI performance estimation at higher design level becomes more difficult. In this paper a new LSI performance model for the estimation is described, which is made up by adopting a new clack-skew model to the SUSPENS (Stanford University System Performance Simulator) model. Using the model, it is cleared that a specific block size, where the line delay overcomes the block cycle time, becomes shorter as the LSI generation proceeds.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ASSOC COMPUTING MACHINERY  

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：KLUWER ACADEMIC PUBL  

This article presents a discrete cosine transform (DCI) processor for high definition television (HDTV) by using an extended version of DSP Silicon Compiler. The extension is mainly concerned with module generation functions.A matrix-vector product module composed of multiply-accumulators (MACs) is newly added to the silicon compiler. The compiler accomplishes placement of leaf-cells and routing between the cells, referring to a prototype layout for the MAC. The prototype, which consists of a Booth multiplier and a carry look ahead adder, is carefully designed to attain high operation speed. The processor developed by the silicon compiler carries out 8 x 8 DCT and its inverse transform (IDCT). In order to evaluate the newly extended functions in the compiler, the architecture employed for the processor is based on the matrix-vector product method. By using DSP Silicon Compiler and 0.8 mum triple metal CMOS technology, the DCT processor is easily implemented with error-free environment and achieves a 50MHz data rate, which meets Japanese HDTV base line signal processing. The chip is implemented on a 12.80 x 12.57 mm2 area.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ASSOC COMPUTING MACHINERY  

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：I E E E, COMPUTER SOC PRESS  

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：SPRINGER VERLAG  

DOI： 10.1007/BF01553879

Web of Science

Language：English   Publishing type：Research paper (scientific journal)  

Techniques for using “buckets” to improve the efficiency of several computational-geometrical algorithms are described, together with examples illustrating the practical importance of the bucketing techniques. Specifically, they are applied to the problems of minimum-weight perfect matchings in the plane, two-dimensional Voronoi diagrams, point location and range search in the plane, and shortest paths in networks. © 1985, Elsevier Inc. All rights reserved.

DOI： 10.1016/B978-0-444-87806-9.50011-6

Scopus

DOI： 10.1145/357337.357338

Responsible for pages：(10群3編「システムオンチップ技術」編のとりまとめと一部執筆を担当)   Language：Japanese

Language：Japanese

Responsible for pages：(第8章の執筆を除く全体を担当)   Language：Japanese

Language：Japanese

Responsible for pages：(第4章「ハードウェア要素技術」を担当)   Language：Japanese

Language：Japanese

Responsible for pages：(「幾何学的アルゴリズム」の項目を担当)   Language：Japanese

Language：Japanese

Responsible for pages：(「VLSIマルチスキャンチェイン最適化アルゴリズム」の項目を担当)   Language：Japanese

Language：English

Responsible for pages：153-195   Language：English

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publisher：IEEE  

Language：Japanese   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)   Publisher：Fuji Technology Press  

This paper describes our approach to perform robust monocular camera metric localization in the dynamic environments of Tsukuba Challenge 2016. We address two issues related to vision-based navigation. First, we improved the coverage by building a custom vocabulary out of the scene and improving upon place recognition routine which is key for global localization. Second, we established possibility of lifelong localization by using previous year’s map. Experimental results show that localization coverage was higher than 90% for six different data sets taken in different years, while localization average errors were under 0.2 m. Finally, the average of coverage for data sets tested with maps taken in different years was of 75%.

DOI： 10.20965/jrm.2017.p0685

Scopus

Language：Japanese  

Language：Japanese  

Language：Japanese  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)  

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)   Publisher：IEEE COMPUTER SOC  

Object detection is a fundamental challenge facing intelligent applications. Image processing is a promising approach to this end, but its computational cost is often a significant problem. This paper presents schemes for accelerating the deformable part models (DPM) on graphics processing units (GPUs). DPM is a well-known algorithm for image-based object detection, and it achieves high detection rates at the expense of computational cost. GPUs are massively parallel compute devices designed to accelerate dataparallel compute-intensive workload. According to an analysis of execution times, approximately 98 percent of DPM code exhibits loop processing, which means that DPM could be highly parallelized by GPUs. In this paper, we implement DPM on the GPU by exploiting multiple parallelization schemes. Results of an experimental evaluation of this GPU-accelerated DPM implementation demonstrate that the best scheme of GPU implementations using an NVIDIA GPU achieves a speed up of 8.6x over a naive CPU-based implementation.

DOI： 10.1109/TPDS.2015.2453962

Web of Science

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing manycore processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor.
We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the twodimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.

DOI： 10.1109/MCSoC.2016.40

Web of Science

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

In this paper, we aim to explore path following. We implement a path following component by referring to the existing Pure Pursuit algorithm. Using the simulation and field operational test, we identified the problem in the path following component. The main problems identified were with respect to vehicles meandering off the path, turning a corner, and the instability of steering control. Therefore, we apply some modifications to the Pure Pursuit[1] algorithm. We have also conducted the simulation and field operational tests again to evaluate these modifications.

DOI： 10.1109/CPSNA.2016.10

Web of Science

Language：Japanese   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)   Publisher：Information Processing Society of Japan  

In this paper, we propose a system-level design method for control systems that enables the development of Hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to a deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with the above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. We have developed a system-level design tool which automatically generates the target implementation from the model. Case studies on a motor control system show that the proposed method reduces the processor load, improves the latency of the interrupt processing, and enables the design space exploration for the control system.

DOI： 10.2197/ipsjjip.23.532

Scopus

Language：Japanese   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.

Web of Science

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

The development of visualization tools that help us assimilate the information that surrounds us is essential in business environments and most research fields. Data visualization is a powerful tool that lets us recognize patterns and trends easily, allows us to extract sensible information faster, stimulates hypothesis generation, and helps us make effective decisions. This paper describes the design and implementation of a web application that displays moving objects in real-time using Google Maps. This web application was done as part of an integrated system that addresses issues related to the automated driver assistance field. Moreover, this work seeks to be a reference framework that will provide visual support for researchers in the area of mobility looking to analyze moving object trajectories, evaluate prediction models, or explain their results.

DOI： 10.1109/CPSNA.2015.20

Web of Science

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

Accurate perception information of the surroundings is a desirable feature in any cyber-physical system for autonomous robotics. Besides, providing a cost-wise solution to this need, is also useful for developing other kinds of applications such as mapping, decision-making, self-localization, among others. In this work, we present and benchmark a cost-effective camera device with six image sensors attached to a custom built FPGA board. The perception information is delivered on the host side, thanks to a HOG based object detector executed on the GPU. Our conclusion is that the low cost prototype is able to acquire and extract the perception data in 9.41 frames per second.

DOI： 10.1109/CPSNA.2015.18

Web of Science

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

In this paper, we propose a system-level design tool for control systems that enables the development of hardware-implemented interrupt handler. The increasing complexity of control systems has led to a rise in the frequency of interrupts. As a result, the processor load increases, leading to deterioration in the latency of interrupt processing. To solve these problems, we require dedicated hardware that is activated by an interrupt and can directly access devices during its processing. The proposed method enables control systems with above dedicated hardware to be developed using a model that abstracts an interrupt, interrupt processing, and communication between the control processing and devices. Case studies on a motor control system show that the proposed method enables the designer to explore design space of control system, reduces the processor load and improves the latency of the interrupt processing.

Web of Science

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)   Publisher：IEEE  

This paper introduces an automatic synthesis technique and tool to implement inter-heterogeneous-processor communication for programmable system-on-chips (PSoCs). PSoCs have an ARM-based hard processor system connected to an FPGA fabric by the high-bandwidth interconnect. By implementing the soft processors in the FPGA fabric, PSoCs realize heterogeneous multiprocessors. Since the number and type of soft processors are configurable, PSoCs can realize various heterogeneous multiprocessors. However, the inter-heterogeneous-processor communications are not supported by operating systems running on different types of processors. The problem is the cost to design and implement such communications. In order to overcome the problem and increase the design efficiency, we propose an automatic synthesis of inter-heterogeneous-processor communications from a general model description. The inter-heterogeneous-processor communications are realized using a shared memory and inter-processor interrupts. The case study shows that automatically generated inter-heterogeneous-processor communication exactly runs on the system with heterogeneous multiprocessors.

Web of Science

Language：Japanese   Publishing type：Article, review, commentary, editorial, etc. (scientific journal)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：Association for Computing Machinery  

Recently General-Purpose Computing on Graphics Processing Units (GPGPU) has been used to reduce the processing time of various applications, but the degree of acceleration by the Graphical Processing Unit (GPU) depends on the application. This study focuses on data analysis as an application example of GPGPU, specifically, the design and implementation of GPGPU computation libraries for data-intensive workloads. The effects of efficient memory allocation and high-speed read-only memories on the execution time are evaluated. In addition to employing a single GPU, the scalability using multiple GPUs is also evaluated. Compared to a Central Processing Unit (CPU) alone, the memory allocation method reduces the execution time for memory copies by approximately 60% when a GPU is used, while utilizing read-only memories results in an approximately 20% reduction in the overall program execution time. Moreover, expanding the number of GPUs from one to four reduces the execution time by approximately 10%.

DOI： 10.1145/2676585.2676616

Scopus

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

本論文ではシステムレベル設計における制御システム向けのプロファイル機構を述べる.制御システムを設計する際,センサーやアクチュエータから非同期で通知される割込みと,割込みにより優先的に処理を開始する割込み処理を考慮する必要がある.但し,既存のプロファイル機構は割込みの関連情報を取得できない.本論文では,制御システムの開発を支援するために,割込みの関連情報を取得可能なプロファイル手法を提案する.提案手法を設計事例に適用し,効果を評価した.

CiNii Books

Language：Japanese   Publisher：一般社団法人電子情報通信学会  

本論文は,割込みで駆動する専用HWを設計可能な,制御システム向けのシステムレベル設計ツールについて述べる.制御システムは複雑化,処理の高度化が進み,それに伴い割込み処理の頻度が増加したことで,プロセッサ負荷の増加,消費電力の増加,割込み処理レイテンシの悪化といった問題が生じている.これらの問題を解決するため,割込みにより処理を開始し,処理中はセンサや入出力ハードウェアといったデバイスへ直接アクセスする専用ハードウェアが求められている.提案手法は,処理とデバイス間の通信,割込み,割込み処理を抽象化した制御システムモデルから,割込みで駆動するハードウェアを含む制御システムを設計可能である.モータ制御システムを対象とした評価実験により,提案手法を用いることで,プロセッサ負荷の削減,消費電力の削減,レイテンシの改善が可能なことを示す.

CiNii Books

Language：Japanese  

本論文ではシステムレベル設計における制御システム向けのプロファイル機構を述べる．制御システムを設計する際，センサーやアクチュエータから非同期で通知される割込みと，割込みにより優先的に処理を開始する割込み処理を考慮する必要がある．但し，既存のプロファイル機構は割込みの関連情報を取得できない．本論文では，制御システムの開発を支援するために，割込みの関連情報を取得可能なプロファイル手法を提案する．提案手法を設計事例に適用し，効果を評価した．

CiNii Books

Language：Japanese  

本論文は，割込みで駆動する専用HWを設計可能な，制御システム向けのシステムレベル設計ツールについて述べる．制御システムは複雑化，処理の高度化が進み，それに伴い割込み処理の頻度が増加したことで，プロセッサ負荷の増加，消費電力の増加，割込み処理レイテンシの悪化といった問題が生じている．これらの問題を解決するため，割込みにより処理を開始し，処理中はセンサや入出力ハードウェアといったデバイスへ直接アクセスする専用ハードウェアが求められている．提案手法は，処理とデバイス間の通信，割込み，割込み処理を抽象化した制御システムモデルから，割込みで駆動するハードウェアを含む制御システムを設計可能である．モータ制御システムを対象とした評価実験により，提案手法を用いることで，プロセッサ負荷の削減，消費電力の削減，レイテンシの改善が可能なことを示す．

CiNii Books

Language：Japanese   Publisher：一般社団法人情報処理学会  

近年，半導体技術の進展によって 1 つの LSI 上に複数のプロセッサが搭載されたマルチコアや，数十，数百のプロセッサが搭載されたメニーコアが広く使われている．また，スケーラビリティをさらに高めるために階層構造を持つメニーコアも登場している．階層型メニーコアアーキテクチャは，将来組込みプロセッサにおいても主流になると考えられている．そこで，階層構造を考慮したタスクマッピング手法を提案し，既存手法との比較評価を行った．提案手法は NN Embed 法，Topo-LB 法，Cluster-Based ILP 法と比較してそれぞれ 44%，32%，26%通信コストの少ないマッピング結果を示した．

CiNii Books

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

The multi core processors are becoming norm and a processor with even more than a hundred of cores are emerging. These inherently require wide range of software tools to help software developers. However, supporting these complex hardware by the tools require significant effort by the tool vendors, and each invest in adapting the new hardware by modifying their tools or creating proprietary configuration files, while often the similar set of hardware architectural information are needed. The SHIM, Software-Hardware Interface for Multi-many-core, is a joint industrial and academic effort to standardize the interface between the multicore hardware and the software tools. This extended abstract introduces SHIM, the overall architecture, the schema used, the use-cases, and a prototype tool to foster the adaption of the interface.

Web of Science

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

Graphics processing units (GPUs) provide an order-of-magnitude improvement on peak performance and performance-per-watt as compared to traditional multicore CPUs. However, GPU-accelerated systems currently lack a generalized method of power and performance prediction, which prevents system designers from an ultimate goal of dynamic power and performance optimization. This is due to the fact that their power and performance characteristics are not well captured across architectures, and as a result, existing power and performance modeling approaches are only available for a limited range of particular GPUs. In this paper, we present power and performance characterization and modeling of GPU-accelerated systems across multiple generations of architectures. Characterization and modeling both play a vital role in optimization and prediction of GPU-accelerated systems. We quantify the impact of voltage and frequency scaling on each architecture with a particularly intriguing result that a cutting-edge Kepler-based GPU achieves energy saving of 75% by lowering GPU clocks in the best scenario, while Fermi-and Tesla-based GPUs achieve no greater than 40% and 13%, respectively. Considering these characteristics, we provide statistical power and performance modeling of GPU-accelerated systems simplified enough to be applicable for multiple generations of architectures. One of our findings is that even simplified statistical models are able to predict power and performance of cutting-edge GPUs within errors of 20% to 30% for any set of voltage and frequency pair.

DOI： 10.1109/IPDPS.2014.23

Web of Science

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.

Web of Science

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)   Publisher：IEEE  

This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation, so that the system can be simulated or executed in pipeline parallel. With a spring-mass-damper model, our technique accomplishes x3.4 performance acceleration on an ideal four-core simulation, and x1.8 on cycle-accurate simulator of a four-core embedded processor as a threaded application on a real time operating system.

Web of Science

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heterogeneous multiprocessors. Along with the increase in the use of heterogeneous multiprocessors such as FPGAs with processor cores, the cost for design and implement of the inter-processor communication becomes a problem. Focusing on that typical heterogeneous multiprocessors have inter-processor interrupts and shared memories, we propose an implementation of inter-processor communication using them. In order to increase the design efficiency, we also propose a method that automatically generates the inter-processor communication for target systems. The case study shows that automatically generated inter-processor communication exactly runs on the system with heterogeneous multiprocessors.

CiNii Books

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

We propose a system level design methodology for control systems that have both input and output by abstraction of interrupt handling. Since control systems are increasing their complexity, the designers have to design them on higher level of abstraction to increase design efficiency. System level design is known as one of the way to realize that. However, they cannot handle control systems because they do not consider interrupt handling. We propose a model that deals with control systems at system level by abstraction of interrupt handling. The case study shows that our proposing model has few overhead on memory usage and execution time.

CiNii Books

Language：English   Publisher：The Institute of Electronics, Information and Communication Engineers  

CiNii Books

Language：English   Publisher：The Institute of Electronics, Information and Communication Engineers  

CiNii Books

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE  

Graphics processing units (GPUs) embrace many-core compute devices where massively parallel compute threads are offloaded from CPUs. This heterogeneous nature of GPU computing raises non-trivial data transfer problems especially against latency-critical real-time systems. However even the basic characteristics of data transfers associated with GPU computing are not well studied in the literature. In this paper, we investigate and characterize currently-achievable data transfer methods of cutting-edge GPU technology. We implement these methods using open-source software to compare their performance and latency for real-world systems. Our experimental results show that the hardware-assisted direct memory access (DMA) and the I/O read-and-write access methods are usually the most effective, while on-chip microcontrollers inside the GPU are useful in terms of reducing the data transfer latency for concurrent multiple data streams. We also disclose that CPU priorities can protect the performance of GPU data transfers.

DOI： 10.1109/ICPADS.2013.47

Web of Science

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)  

Dynamic Partial Reconfiguration technology coupled with an Operating System for Reconfigurable Systems (OS4RS) allows for implementation of a hardware task concept, that is, an active computing object which can contend for reconfigurable computing resources and request OS services in a way software task does in a conventional OS. In this work, we show a complete model and implementation of a lightweight OS4RS supporting preemptable and clock-scalable hardware tasks. We also propose a novel, lightweight scheduling mechanism allowing for timely and priority-based reservation of reconfigurable resources, which aims at usage of preemption only at the time it brings benefits to the performance of a system. The architecture of the scheduler and the way it schedules allocations of the hardware tasks result in shorter latency of system calls, thereby reducing the overall OS overhead. Finally, we present a novel model and implementation of a channel-based intertask communication and synchronization suitable for software-hardware multitasking with preemptable and clock-scalable hardware tasks. It allows for optimizations of the communication on per task basis and utilizes point-to-point message passing rather than shared-memory communication, whenever it is possible. Extensive overhead tests of the OS4RS services as well as application speedup tests show efficiency of our approach. © 2013 Krzysztof Jozwik et al.

DOI： 10.1155/2013/789134

Scopus

Language：English   Publishing type：Research paper, summary (national, other academic conference)   Publisher：IEEE Computer Society  

Vision-based object detection using camera sensors is an essential piece of perception for autonomous vehicles. Various combinations of features and models can be applied to increase the quality and the speed of object detection. A well-known approach uses histograms of oriented gradients (HOG) with deformable models to detect a car in an image [15]. A major challenge of this approach can be found in computational cost introducing a real-time constraint relevant to the real world. In this paper, we present an implementation technique using graphics processing units (GPUs) to accelerate computations of scoring similarity of the input image and the pre-defined models. Our implementation considers the entire program structure as well as the specific algorithm for practical use. We apply the presented technique to the real-world vehicle detection program and demonstrate that our implementation using commodity GPUs can achieve speedups of 3x to 5x in frame-rate over sequential and multithreaded implementations using traditional CPUs. © 2013 IEEE.

DOI： 10.1109/CPSNA.2013.6614255

Scopus

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

This paper evaluates an automatic power reduction scheme of OSCAR automatic parallelizing compiler having power reduction control capability when multiple media applications parallelized by the OSCAR compiler are executed simultaneously on RP2, a 8-core multicore processor developed by Renesas Electronics, Hitachi, and Waseda University. OSCAR compiler enables the hierarchical multigrain parallel processing and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating and power gating for each processor core using the OSCAR multi-platform API. The RP2 has eight SH4A processor cores, each of which has power control mechanisms such as DVFS, clock gating and power gating. First, multiple applications with relatively light computational load are executed simultaneously on the RP2. The average power consumption of power controlled eight AAC encoder programs, each of which was executed on one processor, was reduced by 47%, (to 1.01W), against one AAC encoder execution on one processor (from 1.89W) without power control. Second, when multiple intermediate computational load applications are executed, the power consumptions of an AAC encoder executed on four processors with the power reduction control was reduced by 57% (to 0.84W) against an AAC encoder execution on one processor (from 1.95W). Power consumptions of one MPEG2 decoder on four processors with power reduction control was reduced by 49% (to 1.01W) against one MPEG2 decoder execution on one processor (from 1.99W). Finally, when a combination of a high computational load application program and an intermediate computational load application program are executed simultaneously, the consumed power reduced by 21% by using twice number of cores for each application. This paper confirmed parallel processing and power reduction by OSCAR compiler are efficient for multiple application executions. In execution of multiple light computational load applications, power consumption increases only 12% for one application. Parallel processing being applied to intermediate computational load applications, power consumption of executing one application on one processor core (1.49W) is almost same power consumption of two applications on eight processor cores (1.46W). © 2013 Springer-Verlag.

DOI： 10.1007/978-3-642-36036-7_3

Scopus

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC. We have evaluated FPGA and STP engine in order to confirm their performance whether they can substitute the dedicated hardware of SoC. We selected AES and ADPCM applications to compare the performance of FPGA and STP engine. The applications were synthesized with the same behavioral synthesis tools. Then, we implemented them onto FPGA and STP engine using the integrated development environments. For the evaluation, we compared them in terms of hardware area, the number of states, the number of cycles, frequency, and execution time.

CiNii Books

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

In this paper, we propose an algorithm to calculate the efficiency of number representations in elliptic curve cryptography, average joint Hamming weight. The method uses Markov chains generated from a minimal weight conversion algorithm of d integers using the minimal weight conversion. With redundant representations using digit sets like {0, ±1}, it is possible to reduce computation time of the cryptosystem. Although larger digit sets make the computation time shorter, it requires longer preprocessing time. Therefore, the average joint Hamming weight is useful to evaluate digit sets. The Markov chains to find the average joint Hamming weight are derived automatically from the conversions. However, the number of states in these Markov chains is generally infinite. In [8], we propose an algorithm to reduce the number of states, but it is still unclear which representations the method can be applied for. In this paper, the finiteness of Markov chain with the existence of a stationary distribution is proven in a class of representation whose digit set D S be a finite set such that there exists a natural number Λ where D S ⊆ {0, ±1, ..., ±Λ} and {0,±1, ±Λ} ⊆ D S. The class covers most of the representation practically used in elliptic curve cryptography such as the representation which digit set are {0, ±1} and {0, ±1, ±3}. © 2012 Springer-Verlag.

DOI： 10.1007/978-3-642-28076-4_23

Scopus

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)  

A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice. © 2012 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.5.133

Scopus

Language：English   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)  

Preemption techniques for hardware (HW) tasks have been studied in order to improve system responsiveness at the task level and improve utilization of the FPGA area. This letter presents a fair comparison of existing state-of-the-art preemption approaches from the point of view of their capabilities and limitations as well as impact on static and dynamic properties of the task. In comparison, we use a set of cryptographic, image, and audio processing HW tasks and perform tests on a common platform based on a Virtex-4 FPGA from Xilinx. Furthermore, we propose the preemption as a method which can effectively increase FPGA utilization in case of HW tasks used as CPU accelerators in systems with memory protection and virtualization. © 2012 IEEE.

DOI： 10.1109/LES.2012.2193660

Scopus

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

Language：Japanese  

CiNii Books

Other Link： http://id.nii.ac.jp/1001/00073084/

Language：English   Publishing type：Research paper, summary (national, other academic conference)  

DPR (Dynamic Partial Reconfiguration) capability found in some of modern FPGAs allows implementation of a concept of a HW (Hardware) task, which similarly to its software counterpart has its state and shares time-multiplexed resources with the other tasks. While the new technology presents many advantages for embedded systems where run-time adaptability is an additional requirement, their efficient and easily portable implementations require a control software or an OS which would manage all the complexities of the underlying technology, providing an abstracted interface for the application programmer. This paper presents a novel and robust hardware multitasking extension for a conventional OS, managing task scheduling and configurations, and providing easy-to-use API (Application Programming Interface) for the application programmer. Scheduling is priority-based and takes advantage of task caching. Moreover, the extension is based on a developed design flow and embedded hardware platform allowing efficient task preemption, which can be utilized whenever it presents any benefits to the application. © 2011 IEEE.

DOI： 10.1109/ReConFig.2011.73

Scopus

Language：Japanese  

CiNii Books

Other Link： http://id.nii.ac.jp/1001/00067851/

Language：Japanese   Publisher：Information Processing Society of Japan (IPSJ)  

CiNii Books

Other Link： http://id.nii.ac.jp/1001/00065529/

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

In this report, we present a new Clock Tree Synthesis(CTS)for shrinking a chip design. It minimizes clock skew of the chip through scaling by executing the traditional CTS with two tuned parameters for the target process instead of those for the current process. Since the program and design libraries of CTS do not need to be modified at all and it is executed with the original design data, we can take the advantage of reusing all optimized scripts for CAD which have been already designed. Then, evaluation shows our CTS keeps the skew minimized regardless of shrinking the chip and has sufficient effects on reducing clock skew compared with the traditional one. Consequently, it enables us to extend the application of scaling to LSI design.

CiNii Books

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